JPS6083344A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6083344A
JPS6083344A JP19153683A JP19153683A JPS6083344A JP S6083344 A JPS6083344 A JP S6083344A JP 19153683 A JP19153683 A JP 19153683A JP 19153683 A JP19153683 A JP 19153683A JP S6083344 A JPS6083344 A JP S6083344A
Authority
JP
Japan
Prior art keywords
chip
corners
pads
semiconductor integrated
monitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19153683A
Other languages
Japanese (ja)
Other versions
JPH0658929B2 (en
Inventor
Tadao Kadowaki
忠雄 門脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58191536A priority Critical patent/JPH0658929B2/en
Publication of JPS6083344A publication Critical patent/JPS6083344A/en
Publication of JPH0658929B2 publication Critical patent/JPH0658929B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To economize space by dispersing and arranging monitor patterns checking semiconductor parameters to a plurality of positions in the four corners of a chip. CONSTITUTION:Functional pads 2 and monitor patterns 3-6 are disposed on a chip 1 for a semiconductor integrated circuit. Special spaces for arranging the monitor patterns are unnecessitated by dispersing and disposing the monitor patterns 3-6 at the four corners, to which the pads 2 are not arranged, of the chip 1. When the pads 2 are disposed while avoiding the four corners of the chip 1, spaces in size larger than the pads 2 can be ensured at the four corners of the chip.

Description

【発明の詳細な説明】 本発明け、半漕体集精回路の、半導体バラノー４検定用
のモニタパターン配置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a monitor pattern arrangement for semiconducting integrated circuits for semiconductor Barano 4 test.

半導体集積回路のモニタパターン配置に関しては、従来
よりチップの外周部などの任意の位置に所にまとめて配
置するのが一般的であるが１次のような欠点を有してい
る。モニタパターンを配置する為のスペースが必要であ
り、その分だけチップ→イズが太き（ｆｒ−でしまう。Regarding the arrangement of monitor patterns in semiconductor integrated circuits, it has conventionally been common to arrange them all together at arbitrary positions such as on the outer periphery of a chip, but this has the following drawbacks. A space is required to arrange the monitor pattern, and the chip size becomes thicker (fr-) accordingly.

制約されたスペースの中にモニターパターンを入れこも
うとするので、モニタパターンのパ９ド位置などの標準
化が困難である。Since the monitor pattern is tried to fit into a limited space, it is difficult to standardize the pad positions of the monitor pattern.

本発明けかかる欠点を除告したものであり、チップサイ
ズを大きくせずにモニタパターンを配置し、モニタパタ
ーンのバッド配置ｆｌｊの標準化を容易にするものであ
る、 以下実施例に基づいて本発明の詳細な説明する。The present invention eliminates the drawbacks of the present invention, and facilitates the standardization of monitor pattern pad placement flj by arranging monitor patterns without increasing the chip size. Detailed explanation of.

第１図は、本発明の概略図である。１は半導体集積回路
のチップ外周を示す。２け半導体集積回路の機能パッド
、３，４，５．（！ｔｔ−ｊ、各々チップの四隅に分散
して配置されたモニターパーンケ示す。FIG. 1 is a schematic diagram of the invention. 1 indicates the chip outer periphery of the semiconductor integrated circuit. Functional pads of two semiconductor integrated circuits, 3, 4, 5. (!tt-j shows monitors distributed at each of the four corners of the chip.

バッド２が装置されていないチップの四隅に、モニタパ
ターンを分散配置することによって、モニタパターン配
置の為の特別なスペースは不要である。また、前述のよ
うにバッド２をチップの四隅を避けて配置−ｉれば、チ
ップの四隅には少なくとも、パッド２の大きさ以上のス
ペースが確保できる、モニタパターン検定用のモニタパ
ー、１−Ｎ−ｔ、一般的に轡卵パ・ソド２のイル％程度
の大きさで充分であるので、前述したチップ四隅のスペ
ースがあれば、容易にモニクパヴド位置の梗準化が可卵
である。By distributing the monitor patterns in the four corners of the chip where the pads 2 are not installed, no special space is required for arranging the monitor patterns. In addition, if the pads 2 are arranged avoiding the four corners of the chip as described above, at least a space larger than the size of the pads 2 can be secured at the four corners of the chip. In general, a size of approximately the same size as 2% is sufficient, so if there is space at the four corners of the chip, it is possible to easily standardize the position of the moniker.

チップを実装する方式によっては、チ９プの四隅に機卵
パッドを置けない場合があり、この場合に本発明は特に
不動である。Depending on the method of mounting the chip, it may not be possible to place the machine pads at the four corners of the chip, and the present invention is particularly effective in this case.

館２図は、ウェハ状態でのモニタパターン配置を示す。Figure 2 shows the monitor pattern arrangement in a wafer state.

第１図のように、モニタパターンをチップに四隅に分散
しても、モニタパターンの検定はウェハで行う為、第２
図のようにモニタパターン３．４，５．６Ｖｉ１ケ所に
集中する。従ってモニタパターン検定作秦は従来に変り
なく行う事がで＾る。As shown in Figure 1, even if the monitor pattern is distributed to the four corners of the chip, the verification of the monitor pattern is performed on the wafer, so the second
As shown in the figure, monitor patterns 3.4 and 5.6Vi are concentrated at one location. Therefore, the monitor pattern verification process can be performed as before.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示すチップ状態の図である
。第２図はウェハ状態を示す図である。 筑３図はチップの隅に配置されたモニタパターンの一実
施例を示す。 １・・チップ外周 ２・・機卯パッド ６〜６・・モニタパターン ７・・モニ々パリド ８・・パラメータ検定用モニタトランジスタ以　上 出願人　株式会社　諏訪精工舎 代理人　弁理士　最上　務 箇１図 蓄２図 第　３図FIG. 1 is a diagram of a chip state showing an embodiment of the present invention. FIG. 2 is a diagram showing the state of the wafer. Fig. 3 shows an example of a monitor pattern placed at a corner of the chip. 1. Chip outer circumference 2. Mechanical pads 6 to 6. Monitor pattern 7. Monitor pad 8. Monitor transistor for parameter verification. Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] トランジヌタのスレッシュホールド電圧、あるいけ電流
増幅率などの半導体パラメータを検定するモニタパター
ン金倉む半導体集積回路において前記モニタパターンを
、チップの四隅のうちの複数ケ所以上に分散して配置す
ることを特徴とする半導体集積回路。A monitor pattern for verifying semiconductor parameters such as the threshold voltage of a transistor and a current amplification factor.In a semiconductor integrated circuit according to Kanakura, the monitor pattern is distributed and arranged at more than one of the four corners of the chip. semiconductor integrated circuits.
JP58191536A 1983-10-13 1983-10-13 Process monitor pattern Expired - Lifetime JPH0658929B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58191536A JPH0658929B2 (en) 1983-10-13 1983-10-13 Process monitor pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58191536A JPH0658929B2 (en) 1983-10-13 1983-10-13 Process monitor pattern

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP15915295A Division JPH0851135A (en) 1995-06-26 1995-06-26 Wafer and verifying method therefor

Publications (2)

Publication Number Publication Date
JPS6083344A true JPS6083344A (en) 1985-05-11
JPH0658929B2 JPH0658929B2 (en) 1994-08-03

Family

ID=16276297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58191536A Expired - Lifetime JPH0658929B2 (en) 1983-10-13 1983-10-13 Process monitor pattern

Country Status (1)

Country Link
JP (1) JPH0658929B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH058950U (en) * 1991-07-16 1993-02-05 日本電気株式会社 Semiconductor integrated circuit
US5956567A (en) * 1994-12-19 1999-09-21 Matsushita Electric Industrial Co., Ltd. Semiconductor chip and semiconductor wafer having power supply pads for probe test
US8063468B2 (en) 2007-09-21 2011-11-22 Fujitsu Semiconductor Limited Semiconductor device, method for manufacturing semiconductor device, and method for designing manufacturing semiconductor device
JP2012516650A (en) * 2009-01-28 2012-07-19 アップル インコーポレイテッド Dynamic voltage and frequency management
US8334533B2 (en) 2005-03-16 2012-12-18 Fujitsu Semiconductor Limited Semiconductor device including a circuit area and a monitor area having a plurality of monitor layers and method for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5861639A (en) * 1981-10-08 1983-04-12 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5861639A (en) * 1981-10-08 1983-04-12 Toshiba Corp Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH058950U (en) * 1991-07-16 1993-02-05 日本電気株式会社 Semiconductor integrated circuit
US5956567A (en) * 1994-12-19 1999-09-21 Matsushita Electric Industrial Co., Ltd. Semiconductor chip and semiconductor wafer having power supply pads for probe test
US8334533B2 (en) 2005-03-16 2012-12-18 Fujitsu Semiconductor Limited Semiconductor device including a circuit area and a monitor area having a plurality of monitor layers and method for manufacturing the same
US8673657B2 (en) 2005-03-16 2014-03-18 Fujitsu Semiconductor Limited Semiconductor device including a circuit area and a monitor area having a plurality of monitor layers and method for manufacturing the same
US8063468B2 (en) 2007-09-21 2011-11-22 Fujitsu Semiconductor Limited Semiconductor device, method for manufacturing semiconductor device, and method for designing manufacturing semiconductor device
JP2012516650A (en) * 2009-01-28 2012-07-19 アップル インコーポレイテッド Dynamic voltage and frequency management
US8493088B2 (en) 2009-01-28 2013-07-23 Apple Inc. Dynamic voltage and frequency management
US9218049B2 (en) 2009-01-28 2015-12-22 Apple Inc. Dynamic voltage and frequency management
US9407262B2 (en) 2009-01-28 2016-08-02 Apple Inc. Dynamic voltage and frequency management

Also Published As

Publication number Publication date
JPH0658929B2 (en) 1994-08-03

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