JPS6083344A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6083344A
JPS6083344A JP19153683A JP19153683A JPS6083344A JP S6083344 A JPS6083344 A JP S6083344A JP 19153683 A JP19153683 A JP 19153683A JP 19153683 A JP19153683 A JP 19153683A JP S6083344 A JPS6083344 A JP S6083344A
Authority
JP
Japan
Prior art keywords
chip
corners
pads
integrated circuit
monitor patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19153683A
Other versions
JPH0658929B2 (en
Inventor
Tadao Kadowaki
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP58191536A priority Critical patent/JPH0658929B2/en
Publication of JPS6083344A publication Critical patent/JPS6083344A/en
Publication of JPH0658929B2 publication Critical patent/JPH0658929B2/en
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/24Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests

Abstract

PURPOSE:To economize space by dispersing and arranging monitor patterns checking semiconductor parameters to a plurality of positions in the four corners of a chip. CONSTITUTION:Functional pads 2 and monitor patterns 3-6 are disposed on a chip 1 for a semiconductor integrated circuit. Special spaces for arranging the monitor patterns are unnecessitated by dispersing and disposing the monitor patterns 3-6 at the four corners, to which the pads 2 are not arranged, of the chip 1. When the pads 2 are disposed while avoiding the four corners of the chip 1, spaces in size larger than the pads 2 can be ensured at the four corners of the chip.
JP58191536A 1983-10-13 1983-10-13 Process monitoring pattern Expired - Lifetime JPH0658929B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58191536A JPH0658929B2 (en) 1983-10-13 1983-10-13 Process monitoring pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58191536A JPH0658929B2 (en) 1983-10-13 1983-10-13 Process monitoring pattern

Publications (2)

Publication Number Publication Date
JPS6083344A true JPS6083344A (en) 1985-05-11
JPH0658929B2 JPH0658929B2 (en) 1994-08-03

Family

ID=16276297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58191536A Expired - Lifetime JPH0658929B2 (en) 1983-10-13 1983-10-13 Process monitoring pattern

Country Status (1)

Country Link
JP (1) JPH0658929B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH058950U (en) * 1991-07-16 1993-02-05 日本電気エンジニアリング株式会社 The semiconductor integrated circuit
US5956567A (en) * 1994-12-19 1999-09-21 Matsushita Electric Industrial Co., Ltd. Semiconductor chip and semiconductor wafer having power supply pads for probe test
US8063468B2 (en) 2007-09-21 2011-11-22 Fujitsu Semiconductor Limited Semiconductor device, method for manufacturing semiconductor device, and method for designing manufacturing semiconductor device
JP2012516650A (en) * 2009-01-28 2012-07-19 アップル インコーポレイテッド Dynamic voltage and frequency management
US8334533B2 (en) 2005-03-16 2012-12-18 Fujitsu Semiconductor Limited Semiconductor device including a circuit area and a monitor area having a plurality of monitor layers and method for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5861639A (en) * 1981-10-08 1983-04-12 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5861639A (en) * 1981-10-08 1983-04-12 Toshiba Corp Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH058950U (en) * 1991-07-16 1993-02-05 日本電気エンジニアリング株式会社 The semiconductor integrated circuit
US5956567A (en) * 1994-12-19 1999-09-21 Matsushita Electric Industrial Co., Ltd. Semiconductor chip and semiconductor wafer having power supply pads for probe test
US8334533B2 (en) 2005-03-16 2012-12-18 Fujitsu Semiconductor Limited Semiconductor device including a circuit area and a monitor area having a plurality of monitor layers and method for manufacturing the same
US8673657B2 (en) 2005-03-16 2014-03-18 Fujitsu Semiconductor Limited Semiconductor device including a circuit area and a monitor area having a plurality of monitor layers and method for manufacturing the same
US8063468B2 (en) 2007-09-21 2011-11-22 Fujitsu Semiconductor Limited Semiconductor device, method for manufacturing semiconductor device, and method for designing manufacturing semiconductor device
JP2012516650A (en) * 2009-01-28 2012-07-19 アップル インコーポレイテッド Dynamic voltage and frequency management
US8493088B2 (en) 2009-01-28 2013-07-23 Apple Inc. Dynamic voltage and frequency management
US9218049B2 (en) 2009-01-28 2015-12-22 Apple Inc. Dynamic voltage and frequency management
US9407262B2 (en) 2009-01-28 2016-08-02 Apple Inc. Dynamic voltage and frequency management

Also Published As

Publication number Publication date
JPH0658929B2 (en) 1994-08-03

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