JP3213525B2 - Automatic placement of power pads - Google Patents
Automatic placement of power padsInfo
- Publication number
- JP3213525B2 JP3213525B2 JP29683095A JP29683095A JP3213525B2 JP 3213525 B2 JP3213525 B2 JP 3213525B2 JP 29683095 A JP29683095 A JP 29683095A JP 29683095 A JP29683095 A JP 29683095A JP 3213525 B2 JP3213525 B2 JP 3213525B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- input
- cells
- power supply
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、集積回路を設計す
る際の自動レイアウト方式に係るものであり、特には、
電源パッドの自動配置方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout system for designing an integrated circuit.
The present invention relates to a method for automatically arranging power pads.
【０００２】[0002]
【従来の技術および発明が解決しようとする課題】従来
の技術は、特開平０４−２５６３３８“集積回路の自動
レイアウト方式”のように、パッドとパッドブロックと
を独立に自動配線するという方法などである。具体的に
は、使用するリードフレーム図と予想されるチップサイ
ズから最適パッド位置座標を求め、最適パッド位置座標
にボンディングパッドを配置し、次に、パッドからパッ
ドブロックまでの配線を自動配置・配線ツールにより第
１の自動レイアウトを行なう。そして、このパッド・パ
ッドブロック間の配線を行なった結果、パッドブロック
の絶対座標が決まる。この座標を元に、パッドブロック
および内部領域の自動レイアウトを第２の自動配置配線
ツールにより行なう。これにより、パッドの位置の制限
をなくし、１チップ全体の自動レイアウトが可能とな
る。パッド配置を行ない、パッドブロックとパッド間を
自動配置・配線ツールにより自動レイアウトを行なうと
いう方法である。2. Description of the Related Art The prior art is based on a method of automatically wiring pads and pad blocks independently, as disclosed in Japanese Patent Application Laid-Open No. 04-256338 "Automatic Layout Method for Integrated Circuits". is there. Specifically, the optimum pad position coordinates are obtained from the lead frame diagram to be used and the expected chip size, bonding pads are arranged at the optimum pad position coordinates, and then wiring from the pad to the pad block is automatically arranged and wired. A first automatic layout is performed by the tool. Then, as a result of wiring between the pad and the pad block, the absolute coordinates of the pad block are determined. Based on the coordinates, the automatic layout of the pad block and the internal area is performed by the second automatic placement and routing tool. As a result, the position of the pad is not restricted, and the automatic layout of the entire one chip can be performed. This is a method of arranging pads and automatically laying out between pad blocks and pads using an automatic arrangement / wiring tool.
【０００３】この方法によれば、パッドとパッドブロッ
クとを独立に自動配線することにより、パッドをチップ
のコーナ近傍に配置しなければならない場合でも、人手
修正を行なわずに１チップレベルの自動レイアウト処理
ができるようにしていた。また、内部ブロックとパッド
との位置関係が第１・第２の２段階の自動レイアウトで
レイアウトされるため、パッドの位置については内部ブ
ロックからの制約が少なくなっており、自由なパッド配
置ができるようになっている。According to this method, the pads and the pad blocks are automatically wired independently, so that even when the pads have to be arranged near the corners of the chip, automatic layout of one chip level is performed without manual correction. The processing was made possible. In addition, since the positional relationship between the internal block and the pad is laid out by the first and second automatic layouts in two stages, the position of the pad is less restricted from the internal block, and the pad can be freely arranged. It has become.
【０００４】しかしながら、この技術では使用するリー
ドフレームと予想チップサイズだけから最適パッド位置
を決定するようになっており、電流消費量と電源パッド
との関係については自動レイアウトツールが無視してい
る。つまり、電流消費量と電源パッドの配置については
設計者の技量によっているところが問題である。However, in this technique, an optimum pad position is determined only from a lead frame to be used and an expected chip size, and an automatic layout tool ignores a relationship between a current consumption and a power supply pad. In other words, the current consumption and the arrangement of the power supply pads depend on the skill of the designer.
【０００５】電流消費量を考慮した電源パッドの自動配
置方法が存在すれば、前述のような問題点が解決され
る。The above-mentioned problem can be solved if there is a method for automatically arranging power supply pads in consideration of current consumption.
【０００６】[0006]
【課題を解決するための手段】本発明の電源パッドの自
動配置方法は、ＩＣチップ上に配置される入出力パッド
セルが、その配置順に順次配列されたパッドリストを有
し、合計の消費電流量が一組の電源パッド（Ｖｄｄ，Ｇ
ｎｄ）で駆動可能な上限値を超えない範囲内に於いて、
上記パッドリストより順次入出力パッドセルを選択し、
該選択された一群の入出力パッドセルをＩＣチップ上に
配置すると共に、該選択された一群のパッドセルに対し
て一組の電源パッド（Ｖｄｄ，Ｇｎｄ）を配置すること
を特徴とするものである。According to the method of automatically arranging power supply pads of the present invention, input / output pad cells arranged on an IC chip have a pad list sequentially arranged in the arrangement order, and the total current consumption Is a set of power supply pads (Vdd, G
nd), within a range not exceeding the upper limit that can be driven,
Select input / output pad cells sequentially from the above pad list,
The selected group of input / output pad cells is arranged on an IC chip, and a set of power supply pads (Vdd, Gnd) is arranged for the selected group of pad cells.
【０００７】更に、本発明の電源パッドの自動配置方法
は、上記自動配置方法に於いて、上記一群のパッドセル
の中央部に上記一組の電源パッドを配置することを特徴
とするものである。Further, the method of automatically arranging power pads according to the present invention is characterized in that, in the above-described automatic arranging method, the set of power pads is arranged at the center of the group of pad cells.
【０００８】かかる本発明によれば、一組の電源パッド
に対して、その駆動能力を超える入出力パッドセルが割
り当てられることが無く、また、必要数以上に電源パッ
ドが設けられることもない。したがって、最適の電源パ
ッド配置が得られるものである。更に、一組の電源パッ
ドを、該電源パッドにより駆動される一群の入出力パッ
ドセルの中央部に配置する構成とすることにより、例え
ば、端部に配置した場合と比較して、各入出力パッドセ
ルの駆動をより均等に行うことができるものである。According to the present invention, an input / output pad cell exceeding the driving capability is not assigned to a set of power supply pads, and a power supply pad is not provided in a number larger than a required number. Therefore, an optimum power supply pad arrangement can be obtained. Further, by arranging a set of power supply pads at the center of a group of input / output pad cells driven by the power supply pads, for example, each input / output pad cell Can be driven more evenly.
【０００９】[0009]
【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１０】本発明が適用される集積回路は、特に限定
されないが、以下に於いては、集積回路の一例としてス
タンダードセル方式ＬＳＩを例にとり説明を進める。The integrated circuit to which the present invention is applied is not particularly limited, but the following description will be made by taking a standard cell LSI as an example of the integrated circuit.
【００１１】図２はスタンダードセル方式ＬＳＩの概略
図である。チップ２１の中央部には、それぞれ複数個の
スタンダードセル２２，…が配列された複数のセル列２
３，…が配置されており、周辺部には、パッド部分と、
入力、出力または入出力バッファ部分とを含む入出力パ
ッドセル（入力パッドセル、出力パッドセル又は入力・
出力共用パッドセル）２４1，２４2，…，２４n及び電
源パッドセル（Ｖｄｄ，Ｇｎｄ）２５（２５1，２５2）
が配置されている。上記各セル間は配線領域２６，…に
形成される配線により接続されている。FIG. 2 is a schematic diagram of a standard cell type LSI. In the center of the chip 21, a plurality of cell rows 2 in which a plurality of standard cells 22,.
3, ... are arranged, and a pad portion and
An input / output pad cell (input pad cell, output pad cell or input / output pad cell) including an input, output or input / output buffer portion.
Output the shared pad cells) 24 1, 24 2, ... , 24 n and the power supply pad cells (Vdd, Gnd) 25 (25 1, 25 2)
Is arranged. The cells are connected to each other by wires formed in the wiring regions 26,.
【００１２】本発明に於いては、まず、ＬＳＩチップ上
に配置される入出力パッドセルが、その配置順に順次配
列されたパッドリストが設けられる。各入出力パッドセ
ルは予め設定されている電流消費量をもつ。図２に示す
スタンダードセル方式ＬＳＩの場合のパッドリストを図
３に示す。このパッドリストはＬＳＩの種類毎に異な
る。In the present invention, first, a pad list is provided in which input / output pad cells arranged on an LSI chip are sequentially arranged in the arrangement order. Each input / output pad cell has a preset current consumption. FIG. 3 shows a pad list in the case of the standard cell LSI shown in FIG. This pad list differs for each type of LSI.
【００１３】上記パッドリストより、合計の消費電流量
が一組の電源パッド（Ｖｄｄ，Ｇｎｄ）で駆動可能な上
限値を超えない範囲内に於いて、順次入出力パッドセル
を選択し、該選択された複数個の入出力パッドセル（例
えば、２４1，…，２４6）をチップ上に配置する。その
際、例えば、該一群の入出力パッドセルの中央部に一組
の電源パッドセル２５1，２５2（Ｖｄｄ，Ｇｎｄ）を配
置する。配置状態を図４に示す。更に続けて、上記パッ
ドリストより、合計の消費電流量が一組の電源パッド
（Ｖｄｄ，Ｇｎｄ）で駆動可能な上限値を超えない範囲
内に於いて、順次入出力パッドセルを選択し、該選択さ
れた複数個の入出力パッドセル（例えば、２４7，…，
２４13）を、チップ周辺部の次の領域に配置する。電源
パッドセルは、上と同様に、該一群の入出力パッドセル
の中央部に配置する（図４参照）。上記のことを最終の
入出力パッドセル（２４n）の配置が完了するまで繰り
返す。From the pad list, input / output pad cells are sequentially selected within a range where the total current consumption does not exceed an upper limit value drivable by a set of power supply pads (Vdd, Gnd). A plurality of input / output pad cells (for example, 24 1 ,..., 24 6 ) are arranged on a chip. At this time, for example, a set of power supply pad cells 25 1 and 25 2 (Vdd, Gnd) is arranged at the center of the group of input / output pad cells. FIG. 4 shows the arrangement state. Subsequently, input / output pad cells are sequentially selected from the pad list as long as the total current consumption does not exceed an upper limit value drivable by a set of power supply pads (Vdd, Gnd). , A plurality of input / output pad cells (for example, 24 7 ,.
24 13 ) is arranged in the next area around the chip. The power supply pad cells are arranged at the center of the group of input / output pad cells in the same manner as above (see FIG. 4). The above is repeated until the arrangement of the final input / output pad cell (24 n ) is completed.
【００１４】なお、電源パッドは、入出力パッドセルだ
けではなく、ＬＳＩ内部回路にも電流を供給するが、そ
の値は、入出力パッドセル（特に、出力パッドセル及び
入力・出力共用パッドセル）の消費電流量と比較して極
めて小さい。したがって、実質的に、入出力パッドセル
に於ける消費電流量のみを考慮すればよいものである。The power supply pad supplies a current not only to the input / output pad cells but also to the LSI internal circuit. The value of the power supply pad is the amount of current consumed by the input / output pad cells (particularly, the output pad cells and the input / output shared pad cells). Very small compared to. Therefore, only the amount of current consumption in the input / output pad cells needs to be considered substantially.
【００１５】以上により、入出力パッドセル及び電源パ
ッドセルの配置が完了する。Thus, the arrangement of the input / output pad cells and the power supply pad cells is completed.
【００１６】なお、電源パッドセルの配置位置は必ずし
も一群入出力パッドセルの中央部に限定されない。中央
部に配置する方が、各入出力パッドセルをより均等に駆
動することができるが、端部或いは、その他の位置でも
よい。The arrangement position of the power supply pad cells is not necessarily limited to the central portion of the group of input / output pad cells. Although the input / output pad cells can be driven more uniformly by arranging them at the center, the input / output pad cells may be located at the end or other positions.
【００１７】図１は、本発明に係るパッドセルの自動配
置方法のフローチャートである。FIG. 1 is a flowchart of a method for automatically arranging pad cells according to the present invention.
【００１８】○ステップＳ１ パッドリストから、合計の消費電流Ｉ1が上限の電流ＩN
を超えない範囲内で入出力パッドセルの一群を選択す
る。この一群の入出力パッドセルは、一組の電源パッド
セルで同時駆動可能である。Step S1 From the pad list, the total current consumption I 1 is the upper limit current I N
Is selected within a range not exceeding. This group of input / output pad cells can be driven simultaneously by a set of power supply pad cells.
【００１９】○ステップＳ２ 選択した入出力パッドセルをチップ上に配置する。この
とき、一組の電源パッドセル（Ｖｄｄ，Ｇｎｄ）が中央
部に挿入される形で、上記入出力パッドセルを配置す
る。Step S2 The selected input / output pad cell is arranged on the chip. At this time, the input / output pad cells are arranged such that a set of power supply pad cells (Vdd, Gnd) is inserted into the center.
【００２０】○ステップＳ３ パッドリスト内の未配置入出力パッドセルが無くなるま
で、ステップＳ１及びＳ２を繰り返す。Step S3 Steps S1 and S2 are repeated until there are no unplaced input / output pad cells in the pad list.
【００２１】本発明の自動配置方法により配置された各
部分だけを考えると、消費電流が一組の電源パッドセル
で供給できる電流量を超えることはない。つまり、各部
分の入出力パッドセルが一度に動作した場合でも、その
電流消費量の合計は一組の電源パッドセルで供給できる
上限の電流量を超えることはない。したがって、各部分
で上限の消費電流量を超えることはないのであるから、
チップ全体でも上限の消費電流量を超えることはない。
また、各部分で、最低必要な一組だけの電源パッドセル
が配置されているので、チップ全体で電源パッドセルの
数も必要最低限となっている。さらに、配置された場所
を考えても、最適となっている。つまり、消費電流の多
い出力パッドセルを多用している箇所では少ない数で上
限の電流量ＩNを超えてしまうため、結果としてたくさ
んの電源パッドセルが配置されることになる。また、逆
に消費電流の少ない入力パッドセルが多用されている箇
所では、結果として少ない数の電源パッドセルが配置さ
れることになる。Considering only the parts arranged by the automatic arrangement method of the present invention, the current consumption does not exceed the amount of current that can be supplied by a set of power supply pad cells. That is, even when the input / output pad cells of each part operate at once, the total current consumption does not exceed the upper limit of the amount of current that can be supplied by one set of power supply pad cells. Therefore, since the current consumption does not exceed the upper limit in each part,
The entire chip does not exceed the upper limit of current consumption.
In addition, since at least one set of power supply pad cells required at least is arranged in each part, the number of power supply pad cells in the entire chip is also minimum. Furthermore, it is optimal even in consideration of the place where it is arranged. That is, exceed the upper limit of the amount of current I N a small number at the location of the intensive high output pad cell current consumption, so that a lot of power pad cells as a result is arranged. Conversely, where input pad cells with low current consumption are frequently used, a small number of power supply pad cells are arranged as a result.
【００２２】以上のように、本発明によれば、必要なだ
けの電源パッドセルを必要なところに配置することが可
能となる。As described above, according to the present invention, it is possible to dispose as many power supply pad cells as necessary.
【００２３】[0023]
【発明の効果】以上詳細に説明したように、本発明の電
源パッドの自動配置方法によれば、電源パッドセル（Ｖ
ｄｄ，Ｇｎｄ）を必要最少限で、かつ最適な位置に配置
することができるものである。As described in detail above, according to the method for automatically arranging power supply pads of the present invention, power supply pad cells (V
dd, Gnd) can be arranged at the minimum necessary and optimal position.
【図１】本発明に係る電源パッドの自動配置方法のフロ
ーチャートである。FIG. 1 is a flowchart of a method for automatically arranging power pads according to the present invention.
【図２】スタンダードセル方式ＬＳＩの概略図である。FIG. 2 is a schematic diagram of a standard cell LSI.
【図３】パッドリストを示す図である。FIG. 3 is a diagram showing a pad list.
【図４】本発明によりパッドセル配置がなされたスタン
ダードセル方式ＬＳＩの概略図である。FIG. 4 is a schematic diagram of a standard cell type LSI in which pad cells are arranged according to the present invention.
２１ チップ ２４1，… 入出力パッドセル ２５1，２５2 電源パッドセル21 chips 24 1 ,... Input / output pad cells 25 1 , 25 2 power supply pad cells
Claims (2)
セルが、その配置順に順次配列されたパッドリストを有
し、合計の消費電流量が一組の電源パッドで駆動可能な
上限値を超えない範囲内に於いて、上記パッドリストよ
り順次入出力パッドセルを選択し、該選択された一群の
入出力パッドセルをＩＣチップ上に配置すると共に、該
選択された一群の入出力パッドセルに対して一組の電源
パッドを配置することを特徴とする、電源パッドの自動
配置方法。1. An input / output pad cell arranged on an IC chip has a pad list sequentially arranged in the arrangement order, and a total current consumption does not exceed an upper limit value that can be driven by a set of power supply pads. Within the range, input / output pad cells are sequentially selected from the pad list, the selected group of input / output pad cells are arranged on the IC chip, and one set of input / output pad cells is selected for the selected group of input / output pad cells. A method for automatically arranging power pads, comprising arranging power pads.
組の電源パッドを配置することを特徴とする、請求項１
に記載の電源パッドの自動配置方法。2. The power supply pad according to claim 1, wherein the set of power supply pads is arranged at a central portion of the group of pad cells.
The method for automatically arranging power supply pads according to the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29683095A JP3213525B2 (en) | 1995-11-15 | 1995-11-15 | Automatic placement of power pads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29683095A JP3213525B2 (en) | 1995-11-15 | 1995-11-15 | Automatic placement of power pads |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09139432A JPH09139432A (en) | 1997-05-27 |
| JP3213525B2 true JP3213525B2 (en) | 2001-10-02 |
Family
ID=17838718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29683095A Expired - Fee Related JP3213525B2 (en) | 1995-11-15 | 1995-11-15 | Automatic placement of power pads |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3213525B2 (en) |
-
1995
- 1995-11-15 JP JP29683095A patent/JP3213525B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09139432A (en) | 1997-05-27 |
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