JPS6081989A - Flicker preventing circuit in field signal and frame signal conversion - Google Patents

Abstract

PURPOSE:To prevent flicker without influenced by temperature characteristic and secular change by controlling a gain automatically by the difference in peak value between even number field and odd number field, and controlling a pedestal level by the average value of each horizontal period. CONSTITUTION:The same reproduced field signal 17 is converted to a frame signal, by selecting alternately field signals of 0.5H delay and a through signal by a switch 16 every one vertical scanning period. The converted frame signal is switch-controlled by switch controlling pulse 35 and an inverter 36 and inputted to a peak detectors 27, 28, and, for instance, the difference in peak value between even number field and odd number field is detected and an automatic gain controller 24 is controlled by the difference signal. The pedestal level of each horizontal scanning period is sampled by a switch 31, averaged by an integrating circuit 32 and clamping circuits 33, 34 are controlled. In such a way, flicker can be prevented without influenced by temperature characteristic and secular change.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that completely prevents flickers that occur when converting a field signal into an interlaced scanning frame signal.
The present invention is designed to prevent 7-point errors without being affected by the temperature characteristics or aging of each part of the field degree/frame conversion circuit, and without requiring severe adjustments.

In television scanning, so-called interlaced scanning is performed in which horizontal scanning lines are skipped every few lines in order to reduce flickering to the eyes. In general, [2:1] interlaced scanning in which every other line is skipped is widely used. [:2:1:] In the interlaced scanning method, two coarse screens (fields) created by one vertical scan are overlapped to create one screen (c frame). 60 times per second, and the frame repetition rate is 30 per second.
One frame is generally represented by 525 horizontal scanning lines. Also, in odd and even fields, the starting point of horizontal scanning is the horizontal scanning period (7 of h).
That is, it is shifted by 0.5H. Figure 1 shows a typical example of a composite video signal (frame No. 1g) with a frame signal. In the figure, 1 and 2 are composite video signals (field signals) representing fields, where 1 is for an odd field and 2 is for an even field. 3 is a vertical blanking period, 4 is a front equalization pulse, 5 is a vertical synchronization signal, 6 is a cutting pulse, 7 is a pack equalization i4 pulse, 8 is a horizontal synchronization signal, and 9 is a video signal. Section A in FIG. 1 is enlarged and shown in FIG. 2. 10 is the horizontal blanking period, 11 is the front porch, 12 is the back porch -I+-, 13'f
1 is a pedestal level, and 14 is a sink level.

By the way, when recording video signals on audio/magnetic tape, magnetic disks, or other recording media, it is common to allocate one field of signals to one track, or one frame of signals to one track. It is. Even in the 1-fee IB H-4 track recording,
There are rack recording, in which odd and even fields are recorded one after another, and field recording, in which only one field, even or odd, is completely recorded.

In the case of field recording, playback takes full advantage of the strong video signal and scans the same transfer twice to create a frame signal system from 91 types of field signals.
+i F79 The F7 frame conversion formula is often used. This is mainly to improve the wiring density, making it possible to record for a long time in the case of movies, and increasing the number of frames in the case of methyl. possible. However, when converting from a field signal to a frame signal, is it interlaced scanning even if the same field signal is simply repeated twice and reproduced? It cannot be realized. The reason for this is that for interlaced scanning 9, as can be seen from FIG. In this case, it is necessary to deviate by Q, 5BI, whereas simply repeating the same field signal will easily cause a time lag in Q, 51.
It is et al.

Therefore, as shown in FIG. The field signal is converted into a frame signal by alternately selecting the delay field signal 8 and every vertical scanning period (IV). Incidentally, up to this point, the interval between the vertical synchronizing signals deviates from 1v to Q, 51-1, so for example, it is possible to select contacts c and d of the analog switch 16 as shown in Fig. 4. There is.

tp, through field signal 17 Of the selected periods, field signal 18 with a delay of 0.511 is selected only in the portion 19 from the front equalization/2 pulse section to the pack equalization pulse section. However, in order to convert the field signal 9j' into a frame signal, a circuit is used which selects the through signal and the Q, 5H delay signal, as shown in FIG.

However, the delay line 15 not only attenuates the transmission time but also considerably attenuates the signal, and the analog switch 16
Since the offset lightning and pressure differ at the contact point C2d, a difference occurs in the signal level and pedestal level between the even field and the odd field in the converted frame No. 1, causing flicker on the screen. In order to prevent frizz and chipping, a circuit shown in FIG. 5 has conventionally been adopted. In Fig. 5, 20 is an amplifier, 21 and 22 are clamp circuits, and ■R1
is a gain adjustment potentiometer, and 1'L2 is a clamp level adjustment potentiometer. This anti-flicker circuit uses VJ, ?, so that the signal level is equal for each field in the converted frame. , , the gain 'd of the amplifier 20: a'l , rm le, and vi so that the destabilized level is equal for each field.
i2 makes Krande level k R”l V. However,
Since the above-mentioned h) 31 adjustment is performed manually, a severe nl"A of -40 dB or more is required to prevent flicker.
It is unsuitable for alignment and lacks mass productivity. Also, Q
, 5I-1 delay line 15, analog switch 16
, the amplifier 20 and the clamp circuits 21 and 22 have temperature characteristics and also change over time, so even if VRl
Even if the amount of flicker was suppressed by polishing , Vl(, z), it was not possible to suppress the flicker caused by temperature characteristics or changes over time.

In view of the problems of the prior art described above, the present invention
It is an object of the present invention to provide a circuit that can automatically prevent frizz that occurs in a signal/input signal conversion circuit without being affected by temperature characteristics or aging.

This purpose? The configuration of the present invention achieves the same) yield °
In a circuit that converts a frame signal into an F-frame signal by repeating the entire signal, a field signal delayed by 100 horizontal scanning periods and a through field signal alternately selected every vertical scanning period by switching the frame switch. A circuit that detects the negative value of the lattice-through field signal and a peak value of the delayed field signal?
A detection circuit, a differential amplifier that outputs the difference between the detection values of both peak detection circuits, and a sink level that is inserted into the delay or through line and controlled by the peak value difference signal.
An automatic gain controller that keeps it constant, a switch that samples the pedestal level of the frame signal every horizontal scanning period, a circuit that calculates the average value of each sample value, and a circuit that calculates the average value of each sample value connected to each delay and through line. All features include a feedback-clamp circuit which is controlled by a signal to maintain a constant base level of the frame signal.

Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 6 shows an embodiment of the flicker prevention circuit of the present invention.

FIG. 7 is an explanatory diagram of the operation of the part shown in FIG. 6. In Figure 6, 15 is a 0.5H delay line, 16 is an analog switch for field selection, 23 is an AGC loop, 3
0 is a feedback clamp loop. The AGC loop 23 includes an automatic gain controller 24, a field selection switch 16, an input selection switch 25, 26, a peak detector 27, 28, and a differential amplifier 29.

The feedback clamp loop 30 includes a field selection switch 16, a sampler switch 31, an integrating circuit 32, and a foot-notch clamp circuit 33, 34.
It consists of

It operates so that the AGC Luzo IR sync level (numeral 14 in Fig. 2) is constant, and the - single value of an even field detected by one peak detector 27 is detected by the other peak detector 28. For example, the detected peak value of the odd field is manually inputted to the differential Q IIXΔ device 29, and the difference signal 29,1 is used to control the automatic gain controller 24'.The peak value is made to match between all even and odd fields. There is. If the peak value is constant, the sync level and signal level will be constant. Regarding the time constant, a time constant is selected that responds at least in field units so that the signal level of the prayer field matches the letter level of the previous field. By the way, FIG. 7I(a) shows the frame signal system, and the input selection switch 25 in FIG.
．． 26 is the switch control node 35 of the 71st W (b)
and inverter 36, respectively in Fig. 7(C) and 1
7(e) and 7(e) for each peak detector 27 and 28, respectively.
As shown in f), a signal is input every 1V.

On the other hand, the feedback clamp loop operates so that the pedestal level (reference numeral 13 in FIG. 2) remains constant, and the switch 31 samples the pedestal level in each horizontal scanning period, and the sample value integrator circuit 32 The feedback Φ clamp circuits 33 and 34 whose outputs give the pedestal level are controlled by the average value signal 32a, and the four deskle levels are made to match each horizontal scanning period. . The time constant of this feedback clamp loop is set to be several II or less at most, so that when the field is switched, the clamp is stabilized between 1H and 2H. This is engineering p12
two feedback clamp circuits 33. Even if there are variations in the characteristics of '34, the flicker becomes η quickly. Furthermore, FIG. 7(g) shows the sampling timing of the switch 31.

As explained above, the automatic gain controller is fully controlled by the signal detected by the difference between the peak values of the even and odd fields, and the C signal level is kept constant between fields and for each horizontal scanning period. When the pedestal level is sampled and the average value is increased, the clamp level is controlled using the average value signal and the pedestal level is kept constant, so the circuit that converts the field signal to the frame signal has temperature characteristics and changes over time. Flicker can also be suppressed without being affected by these factors. In addition, since the signal level and pedestal level are automatically adjusted, it is highly suitable for mass production.

In the embodiment of FIG. 6, the automatic gain controller 24 is
I (Although it is placed on the same line as delay line 15, it may be placed on the through side line.

In this case, it is preferable to reverse the inputs of the differential amplifier 29 as shown in FIG. Capacitor 37 in Figures 6 and 8
．． 38 is for DC cut.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a frame signal, Fig. 2 is an explanation of the first operation, Fig. 5 is a circuit diagram showing a conventional flicker prevention circuit, and Fig. 6 is a diagram showing a final embodiment of the present invention. The circuit diagram, Fig. 7 is an explanatory diagram of the operation of the inner part in Fig. 6, and Fig. 8 is the main part of another embodiment?
FIG. In the drawing, 15 is a Q, 5H delay line, 16 is a field changeover switch, 23 is an AGC loop, 24 is an automatic gain controller, 25 and 26 are input selection switches, 27.28 is a peak detector, and 29 is a Differential amplifier, 30ij fee 1. ``The pack clamp loop 31 is a sampling switch, 32 is an integrating circuit, 33 and 34 are feedback clamp circuits, and 35 is an inverter. Patent applicant: Fuji Photo Film Co., Ltd. Patent attorney: Shibu Mitsuishi (and 1 others) Figure 2 d Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] The same field signal is repeated and converted into a υ frame signal by selecting a field ° signal delayed by one horizontal scanning period, a through field signal, and each other by switching the t switch every one vertical scanning period. In the circuit that detects the peak value of the through field signal of the frame signal, the circuit that detects the peak value of the delayed field signal, and the difference between the detection values of both the peak detection circuits is output. A differential amplifier, an automatic gain controller that is inserted into the delay or through line and controlled by the peak value difference signal to keep the sync level constant, and a switch that samples the frame signal's disk level every horizontal scanning period. And the average value of each sample value? A feedback circuit is connected to the average value signal of the sampled values and is controlled by C to keep it constant at the pedestal level of the C frame signal.
A flicker prevention circuit in field signal/frame signal conversion having a clamp circuit.