JPH0478072B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention relates to a circuit that prevents flicker that occurs when converting a field signal to an interlaced scanning frame signal, and which has particularly good responsiveness and which is capable of controlling each part of the field/frame conversion circuit. Flicker can be prevented without being affected by the temperature characteristics or aging of the film, and without requiring severe adjustment.

<Background Art> In television scanning, so-called interlaced scanning is performed in which horizontal scanning lines are skipped every few lines in order to reduce flickering to the eyes. Generally, skip every other line [2:1]
Interlaced scanning is widely used. [2:1] In the interlaced scanning method, one screen (frame) is created by overlapping two rough screens (fields) created by one vertical scan.The number of field repetitions is, for example,
In the NTSC system, the rate is 60 times per second, the frame repetition rate is 30 times per second, and one frame is generally represented by 525 horizontal scanning lines.

Furthermore, the start point of horizontal scanning is shifted by 1/2 of the horizontal scanning period (H), ie, 0.5H, between odd-numbered fields and even-numbered fields. FIG. 1 shows a typical example of a composite video signal (frame signal) representing a frame. In the figure, 1 and 2 are composite video signals (field signals) representing fields, where 1 is for an odd field and 2 is for an even field. 3 is a vertical blanking period, 4 is a front equalization pulse, 5 is a vertical synchronization signal, 6 is a cutting pulse, 7 is a back equalization pulse, 8 is a horizontal synchronization signal, and 9 is a video signal. Section A in FIG. 1 is enlarged and shown in FIG. 2. 10 is the horizontal blanking period;
11 is the front pouch, 12 is the back pouch, 1
3 is the pedestal level, and 14 is the sink chip level.

By the way, when recording video signals on magnetic tape, magnetic disk, or other various recording media, 1
It is common to allocate one field of signals to each track or one frame of signals to each track. Also, in 1 field/1 track recording, so-called 1 frame/2 in which odd numbered fields and even numbered fields are recorded one after another.
There are track recording and field recording in which only odd or even fields are recorded.

In the reproduction of field recording, a so-called field/frame conversion method is often used, which takes advantage of the strong vertical correlation of video signals and scans the same track twice to create a frame signal from one type of field signal. The main purpose of this is to improve the recording density, making it possible to record for a long time in the case of movies, and to increase the number of frames in the case of stills. However, when converting a field signal into a frame signal, interlaced scanning cannot be achieved by simply repeating and reproducing the same field signal twice. The reason for this is that for interlaced scanning, the vertical synchronizing signal 5
The time relationship between the horizontal synchronizing signal 8 and the video signal 9 of each line is odd field 1 and even field 2.
This is because, while a 0.5H time difference is required for , simply repeating the same field signal does not result in a 0.5H time difference.

Therefore, as shown in Fig. 3, the same field signal that is repeatedly reproduced is passed through a 0.5H delay line 15, and an analog switch 16 is used to connect the through field signal 17 and the 0.5H delay field signal 18 to one vertical line. Field signals are converted into frame signals by alternately selecting them every scanning period (1V). In addition, as it is, the interval between vertical synchronization signals will be from 1V to
Since the difference is 0.5H, it is considered that, for example, the contacts c and d of the analog switch 16 are selected as shown in FIG. That is, of the period in which the through field signal 17 is selected, the 0.5H delay field signal 18 is selected only in the portion 19 from the front equalization pulse section to the back equalization pulse section. In any case, to convert the field signal into a frame signal, a circuit is used that selects between a through signal and a 0.5H delay signal, as shown in FIG.

However, the delay line 15 not only delays the transmission time but also attenuates the signal to a small extent, and the offset voltage of the analog switch 16 is
d, the converted frame signal has a difference in signal level and pedestal level between even and odd fields, causing flicker on the screen. In order to prevent flicker, a circuit shown in FIG. 5 has conventionally been adopted. In FIG. 5, 20 is an amplifier, 21 and 22 are clamp circuits,
VR ₁ is a gain adjustment potentiometer, and VR ₂ is a clamp level adjustment potentiometer. In this anti-flicker circuit, the gain of the amplifier 20 is adjusted by VR ₂ so that the signal level is equal for each field in the converted frame signal, and the clamp level is adjusted by VR ₂ so that the pedestal level is equal for each field. Adjust. However, since the above-mentioned adjustment is performed manually, it is unsuitable for making severe adjustments of −40 dB or more to prevent flicker, and is not suitable for mass production.
Also, 0.5H delay line 15, analog switch 16, amplifier 20 and clamp circuits 21, 2
2 has temperature characteristics and also changes over time, so even if the flicker could be suppressed by adjusting VR ₁ or VR ₂ , it would not be possible to suppress the flicker caused by temperature characteristics or changes over time.

Therefore, the applicant has already developed a circuit that can automatically prevent flicker occurring in a field signal/frame signal conversion circuit without being affected by temperature characteristics or aging. This automatic flicker prevention circuit has already been filed as Japanese Patent Application No. 189202/1982, and its outline will be explained with reference to FIGS. 6 and 7. FIG. 6 is a circuit diagram, and FIG. 7 is an explanatory diagram of the operation of each part in FIG. In FIG. 6, 15 is a 0.5H delay line, 16 is an analog switch for field selection, 23 is an AGC loop, and 30 is a field back clamp loop. The AGC loop 23 operates to keep the sync chip level (14 in FIG. 2) constant, and includes an automatic gain controller 24, a field selection switch 16, and two input selection switches 25, 26, 2. It is composed of two peak detectors 27 and 28 and a differential amplifier 29. Here, the switch 16 outputs the frame signal shown in FIG. 7a, and the input selection switches 25 and 26 in FIG.
As shown in Fig. 7c and d, respectively, the
Turn off. As a result, each peak detector 27, 28
A frame signal is input every 1V as shown in FIG. 7e and FIG. 7f, respectively. That is, the peak value of, for example, an even field detected by one peak detector 27 and the peak value of, for example, an odd field detected by the other peak detector 28 are input to the differential amplifier 29, and the difference signal 29a is used for automatic gain control. Vessel 2
4, the peak values are matched between even and odd fields. If the peak value is constant, the sync level and signal level will be constant. Regarding the time constant, a time constant is selected that responds at least in field units so that the signal level of a subsequent field matches the signal level of a previous field.

On the other hand, the feedback clamp loop operates so that the pedestal level (numeral 13 in FIG. 2) is constant, and includes a field selection switch 16, a sampling switch 31, an integrating circuit 32, and two clamp circuits 33. , 34. FIG. 7g shows the sampling timing of the switch 31. That is, the pedestal level of each horizontal scanning period is sampled, the sample value is held in the integrating circuit 32, and the reference value is
Compared with Vref ₁ , the clamp circuits 33 and 34 whose outputs are designed to give the pedestal level are
By controlling with the difference signal 32a from the integrating circuit 32, the pedestal level is made to match in each horizontal scanning period. The time constant of this feedback clamp loop is set to be several H or less at most, and the clamp is stabilized between 1H and 2H when the field is switched. As a result, even if there are variations in the characteristics of the two clamp circuits 33 and 34, flicker is quickly eliminated. Incidentally, capacitors 37 and 38 in FIG. 6 are for DC cut.

As explained above, according to the anti-flicker circuit already developed by the applicant, the peak values (sync chip level) of even and odd fields
The signal level is kept constant between fields by detecting the difference and controlling the automatic gain controller with the difference signal, and the pedestal level is sampled every horizontal scanning period to find the difference with the reference value and clamped with the difference signal. Since the pedestal level is kept constant by controlling the level, even if the circuit that converts the field signal to the frame signal has temperature characteristics or changes over time, it is hardly affected by these, and flicker can be suppressed. In addition, the signal level and pedestal level are automatically adjusted, so
Highly mass-producible.

However, even with such anti-flicker circuits having many advantages, there is still room for improvement in response, and there is still room for improvement in anti-flicker effects based on temperature characteristics. That is, since signals are input to the peak detectors 27 and 28 only every 1V period, the hold time of the peak detectors is at least
A 1V period was required, which placed a limit on the responsiveness of the AGC loop. If the response is not fast enough, the AGC loop may not operate when the power is turned on and off or when the input signal is turned on and off.
On the other hand, separate peak detectors 27 and 2 are used to detect the peak values of the through and delayed field signals.
8 is used, so if there is a difference in temperature characteristics between the two peak detectors, this will cause a slight flicker.

<Object of the Invention> In view of the above-mentioned problems, the present invention provides a circuit that can automatically prevent flicker occurring in a field signal/frame signal conversion circuit without being affected by temperature characteristics or aging, and with good responsiveness. The purpose is to provide

<Structure of the Invention> The structure of the anti-flicker circuit of the present invention that achieves this object is to repeat the same field signal, and to switch between a field signal delayed by 1/2 horizontal scanning period and a through field signal. In a circuit that converts into a frame signal by alternately selecting one every vertical scanning period, (a) an automatic gain controller that amplifies the frame signal output from the above switch, and each horizontal retrace line of the amplified frame signal; and a gain control voltage generation circuit which, upon detecting the peak value of the period, compares the output signal of the peak detection circuit with a reference value and supplies a voltage signal proportional to the difference to the automatic gain controller, which is amplified. An AGC loop that keeps the sync chip level of the frame signal constant, and (b) a sample hold circuit that samples the pedestal level of the frame signal output from the above switch, and compares the output signal of this sample hold circuit with a reference value. a circuit that generates a clamp potential signal with a potential proportional to the difference between the two;
a feedback clamp loop having two clamp circuits connected to each of the through and delay lines and controlling the pedestal level of each of the through and delay field signals to a constant level by the output signal of the clamp potential generation circuit; It is characterized by:

<Effects of the Invention> In the present invention, a signal converted into a frame signal by a switch is amplified by an automatic gain controller, the peak value (sync chip level) of the amplified frame signal is detected, and the peak value is used as a reference. The automatic gain controller is controlled so as to have a constant peak value compared to the value. Therefore, only one peak detection circuit is required, and a signal is constantly input to the peak detection circuit. A signal is constantly input to the peak detection circuit. Since the signal is constantly input to the peak detection circuit, the hold time can be as short as about 1H period.
Therefore, the response of the AGC loop becomes extremely fast. Furthermore, since there is only one peak detection circuit, no flicker occurs even if there is a temperature characteristic.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 8 shows an embodiment of the present invention, and FIG. 9 shows operational waveform diagrams of each part thereof. Further, FIG. 10 shows another embodiment.

First, the embodiment shown in FIG. 8 will be explained. In Fig. 8, 15 is a 0.5H delay line, 16 is a field changeover switch, 17 is a through field signal, 18 is a delayed field signal, and 2
4 is an automatic gain controller, 33 and 34 are clamp circuits, 37 and 38 are DC cut capacitors, 39
43 is an emitter follower circuit for impedance conversion, 44 is an AGC loop, and 45 is a feedback clamp loop.

The AGC loop 44 of this embodiment is connected to the switch 16.
an automatic gain controller 24 that amplifies the frame signal 46 from the frame signal 47, a sample hold circuit 48 that samples the peak or sync chip level of the amplified frame signal 47, and a sample hold output 48.
a gain control voltage generation circuit 49 that compares a with a reference value Vref2 and outputs a voltage signal 49a proportional to the difference;
It consists of a synchronization signal separation circuit 50 that separates a synchronization signal from the frame signal 46, and a sampling pulse generation circuit 51 that generates a sampling pulse 51a from the separated synchronization signal 50a.

FIG. 9a shows the separated synchronization signal 50a,
The sampling pulse 51a is shown in FIG. The sampling pulse 51a is synchronized with the falling edge of the synchronization signal 50a, that is, the change point from the pedestal level to the sync chip level, and its pulse width is equal to the change from the sync chip level to the sync chip level during equalization periods 4 and 7 (see FIG. 1). The width of the incision or equalization pulse is equal to or narrower than that. As a result, the sample and hold circuit 48 detects the sync chip level during the period including the vertical blanking period 3 (see FIG. 1) of the amplified frame signal 47, and operates as a peak detection circuit. Gain control voltage generation circuit 4
9 is the output signal 48a of the sample hold circuit 48
is compared with the reference value Vref ₂ and a difference signal 49a is given to the automatic gain controller 24, which operates so that the sync chip level of the frame signal 47 becomes a constant value. Therefore, the voltage hold time of the sample and hold circuit 48 only needs to be about 1H period, and the responsiveness of the AGC loop 44 becomes extremely fast. Therefore, when the power is turned on/off or the switch 16 is turned on/off,
AGC operation is performed. Furthermore, since the detection of the peak value is performed by one circuit 48, no flicker occurs even if there are temperature characteristics.

On the other hand, the feedback clamp loop 45 of this embodiment receives the frame signal 46 from the switch 16.
Early synchronization signal separation circuit 5 that separates the synchronization signal from
0, sampling pulse generation circuit 5 that generates sample hold 52a from separated synchronization signal 50a
2. A sample and hold circuit 53 that samples the pedestal level of the frame signal 46 based on this sample and hold 52a, and a clamp voltage generator that compares the sample and hold output 53a with a reference value Vref ₁ and outputs a voltage signal 54a proportional to the difference. It consists of a circuit 54 and two clamp circuits 33 and 34 connected to each of the through and delay lines. FIG. 9c shows the sampling pulse 52a. This sampling pulse 52a is used as the synchronization signal 5.
It is synchronized with the rising edge of 0a, that is, the change point from the sink chip level to the pedestal level.
The pulse width is the cutting pulse 6 of the vertical synchronization period 5.
The width is the same as or narrower than (see Figure 1). As a result, the sample and hold circuit 53 detects the pedestal level during all periods of the frame signal 46 including the vertical blanking period 3 (see FIG. 1). The clamp potential generation circuit 54 uses the sampled pedestal level as a reference value.
A difference signal 54a compared with Vref ₁ is applied to each clamp circuit 33, 34, and operates so that the pedestal level of both through and delayed field signals 17, 18 becomes a constant value. Therefore, the feedback clamp loop 45 of this embodiment can clamp the pedestal level during all periods including the vertical blanking period. Also, since the sampling interval is 1H or less, the sample hold circuit 53
The voltage hold time of 1H is sufficient, and the responsiveness of the feedback clamp loop 45 becomes faster.

The embodiment shown in FIG.
It is the same as FIG. 8 except that 5 is slightly different. this
The AGC loop 55 includes an automatic gain controller 24, a peak detector 56, and a gain control voltage generation circuit 49, and does not require a sampling pulse generation circuit or the like.
The peak detector 49 detects the amplified frame signal 47
Since the peak value of , that is, the sync chip level is detected, by setting the voltage hold time to about 1H period, the AGC loop 5 is
5's responsiveness is extremely fast. Furthermore, since the peak value is detected by only one circuit 56, no flicker occurs even if there are temperature characteristics.

Note that the feedback clamp loop 30 shown in FIG. 6 can also be used for each of the feedback clamp loops shown in FIGS. 8 and 10. However, in this case, it is common to create a sampling pulse using an HD pulse from a synchronization signal generator (SSG) and apply it to the sampling switch 31. Therefore, normally, the pedestal level cannot be sampled during the vertical synchronization period, and it is necessary to increase the voltage hold time by the integrating circuit 32 to about 4H period. In this respect, the feedback clamp loop 45 in FIGS. 8 and 10 clamps even during the vertical synchronization period, so no sag occurs, and the response is fast, so it can be used to turn on/off the power supply or turn the switch 16 on/off. It has the advantage of being able to clamp immediately in some cases.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the frame signal, and Figure 2 is an explanatory diagram of the frame signal.
An enlarged explanatory diagram of part A in the figure, Fig. 3 is a principle circuit diagram of field signal/frame signal conversion, Fig. 4 is an explanatory diagram of switch operation, Fig. 5 is a circuit diagram showing a conventional flicker prevention circuit, FIG. 6 is a circuit diagram showing an embodiment of the previously applied application, and FIG. 7 is an explanatory diagram of the operation of each part in FIG. FIG. 8 is a circuit diagram showing one embodiment of the present invention, FIG. 9 is an explanatory diagram of the operation of each part in FIG.
FIG. 0 is a circuit diagram showing another embodiment. In the drawing, 15 is a 0.5H delay line, 16 is a field changeover switch, 17 is a through field signal, 18 is a delayed field signal,
24 is an automatic gain controller, 30 and 45 are feedback clamp loops, 31 is a sampling switch, 32 is an integration circuit, 33 and 34 are clamp circuits, 44 and 55 are AGC loops, 46 is a frame signal, and 47 is an amplification circuit. 48 is a sample and hold circuit, 49 is a gain control voltage generation circuit, 50 is a synchronous separation circuit, 51 is a sampling pulse generation circuit, 52 is a sampling pulse generation circuit, 53 is a sample and hold circuit, and 54 is a clamp voltage generation circuit. The circuit 56 is a peak detector.

Claims (1)

[Claims] 1. A frame is generated by repeating the same field signal and alternately selecting a field signal delayed by 1/2 horizontal scanning period and a through field signal every 1 vertical scanning period by switching a switch. The circuit for converting the signal into a signal includes: (a) an automatic gain controller that amplifies the frame signal output from the switch; a circuit that detects the peak value of the amplified frame signal in each horizontal blanking period; and a circuit that detects the peak value of the amplified frame signal. and a gain control voltage generation circuit that compares the output signal of the circuit with a reference value and supplies a voltage signal proportional to the difference to the automatic gain controller, and keeps the sync chip level of the amplified frame signal constant. (b) A sample-and-hold circuit that samples the pedestal level of the frame signal output from the above switch, and a clamp potential that compares the output signal of this sample-and-hold circuit with a reference value and is proportional to the difference between the two. A circuit that generates a signal,
a feedback clamp loop having two clamp circuits connected to each of the through and delay lines and controlling the pedestal level of each of the through and delay field signals to a constant level by the output signal of the clamp potential generation circuit; A flicker prevention circuit in field signal/frame signal conversion, characterized by: 2. The flicker prevention circuit in field signal/frame signal conversion according to claim 1, wherein the peak detection circuit is a peak detector having a voltage hold time of approximately 1H period. 3. In claim 1, the peak detection circuit is a sample-and-hold circuit having a voltage hold time of approximately 1H period, and as a sampling pulse generation circuit for this sample-and-hold circuit, a signal is generated from the frame signal output from the switch. It has a circuit that separates the synchronization signal, and a circuit that inputs the separated synchronization signal and outputs a pulse that is synchronized with the change point from the pedestal level to the sync chip level and whose width is equal to or smaller than the equalization pulse width. A flicker prevention circuit in field signal/frame signal conversion characterized by: 4. In claim 1, 2, or 3, the feedback clamp loop includes a circuit that separates a synchronization signal from a frame signal output from the switch, and a circuit that inputs the separated synchronization signal. The present invention is characterized in that it has a circuit that generates, as a sampling pulse for the sample and hold circuit, a pulse that is synchronized with the change point from the sync chip level to the pedestal level and has a width that is equal to or less than the width of the cutting pulse. Flicker prevention circuit in field signal/frame signal conversion.