JPH055236B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a circuit that uses peak AGC (automatic gain control) to prevent flicker that occurs when a field signal is converted into an interlaced scanning frame signal.

<Prior Art> In television scanning, so-called interlaced scanning is performed in which horizontal scanning lines are skipped every few lines in order to reduce flickering to the eyes. Generally, skip every other line [2:1]
Interlaced scanning is widely used.

[2:1] In the interlaced scanning method, one screen (frame) is created by overlapping two coarse screens (fields) created by one vertical scan. For example, in the NTSC system, the field repetition rate is 60 times per second, the frame repetition rate is 30 times per second, and one frame is generally represented by 525 horizontal scanning lines.
Also, between odd and even fields,
The starting point of horizontal scanning is 1/2 of the horizontal scanning period (H),
In other words, it is shifted by 0.5H.

By the way, when recording video signals on magnetic tape, magnetic disk, or other various recording media, 1
It is common to allocate one field of signals to each track or one frame of signals to each track. Also, in one field/one track recording, there are so-called one frame/two track recording in which an odd numbered field and an even numbered field are recorded one after another, and field recording in which only one of the even and odd fields is recorded.

In the reproduction of field recording, a so-called field/frame conversion method is often used, which takes advantage of the strong vertical correlation of video signals and scans the same track twice to create a frame signal from one type of field signal. This is mainly aimed at improving the recording density, making it possible to record for a long time in the case of movies, and increasing the number of frames in the case of stills. However, when converting a field signal into a frame signal, interlaced scanning cannot be achieved by simply repeating and reproducing the same field signal twice. The reason for this is that for interlaced scanning, the time relationship between the vertical synchronizing signal, the horizontal synchronizing signal of each line, and the video signal must be shifted by 0.5H between odd and even fields, whereas This is because a time lag of 0.5H does not occur simply by repeating the process.

Therefore, as shown in Fig. 6, the same field signal 1 that is repeatedly reproduced is passed through the 0.5H delay line 2, and the analog switch 3 is used to connect the through field signal 1 and the 0.5H delay field signal 4 to 1. Field signal 1 is converted into frame signal 5 by alternately selecting it every vertical scanning period (1V). In addition, as it is, the interval between vertical synchronization signals will be from 1V to
Since the difference is 0.5H, it has been considered to select contacts a and b of the analog switch 3 as shown in FIG. 7, for example. In other words, during the period in which the through field signal 1 is selected by the switch control signal 9, only the portion 10 from the front equalization pulse section to the back equalization pulse section is 0.5H.
Delay field signal 4 is selected. In any case, in order to convert the field signal to a frame signal, as shown in Figure 6, the through signal and
A circuit that selects a 0.5H delay signal is used.

However, the delay line 2 not only delays the transmission time but also attenuates the signal to a considerable extent, and the offset voltage of the analog switch 3
Therefore, in the converted frame signal 5, a difference occurs in the video signal level and the pedestal level between the even field and the odd field, and flicker occurs on the screen. In order to prevent flicker, a circuit shown in FIG. 6 has conventionally been adopted. In FIG. 6, 6 is an amplifier, 7 and 8 are pedestal level clamp circuits, VR ₁ is a gain adjustment potentiometer, and VR ₂ is a clamp level adjustment potentiometer. This anti-flicker circuit uses an amplifier 6 at VR ₁ to make the video signal level equal for each field in the converted frame signal.
Adjust the gain in a semi-fixed manner, and adjust the clamp level with VR ₂ so that the pedestal level is equal for each field. However, since the above-mentioned adjustment is done manually, it is difficult to prevent flickering.
It is unsuitable for making severe adjustments of 40 dB or more, and is not suitable for mass production. Also, the 0.5H delay line 2, analog switch 3, amplifier 6, and clamp circuits 7 and 8 have temperature characteristics and change over time, so even if you can suppress flicker by adjusting VR ₁ and VR _2, However, it has not been possible to suppress frizz caused by temperature characteristics or aging.

Therefore, the applicant has already developed a circuit that can automatically prevent flicker occurring in a field signal/frame signal conversion circuit without being affected by temperature characteristics or aging. This automatic anti-flicker circuit has already been filed as Application No. 189202/1985, and its outline will be explained with reference to FIGS. 8 and 9. FIG. 8 is a circuit diagram, and FIG. 9 is an explanatory diagram of the operation of each part in FIG. In Figure 8, 2 is a 0.5H delay line, 3 is an analog switch for field selection, 11 is an AGC loop,
18 is a field back clamp loop.
The AGC loop 11 operates so that the sync chip level (reference numeral 28 in FIG. 9) is constant, and includes an automatic gain controller 12, a field selection switch 3, and two input selection switches 13, 1.
4. Peak detector 1 for two sync chip levels
5, 16 and a differential amplifier 17. Here, the switch 3 outputs a frame signal 5 shown in FIG. 9a.
is output, and the input selection switch 13 in FIG.
14 is turned on/off as shown in FIGS. 9c and 9d, respectively, by the switch control pulse 23 and inverter 24 shown in FIG. 9b. As a result, a frame signal is input to each peak detector 15, 16 every 1V as shown in FIGS. 9e and 9f, respectively. That is, for example, the peak value of the sync chip 28 of an even field detected by one peak detector 15,
For example, the peak value of the sync chip 28 in an odd field detected by the other peak detector 16 is inputted to the differential amplifier 17, and by controlling the automatic gain controller 12 with the difference signal 17a, the peak value of the sync chip is divided into both even and odd fields. It is consistent between

On the other hand, the field back clamp loop 18 operates so that the pedestal level (reference numeral 29 in FIG. 9) is constant, and includes a field selection switch 3, a sampling switch 19, an integrating circuit 20, and two clamp circuits 21. , 22. 27 is a sampling pulse. FIG. 9g shows the sampling timing of the switch 19. That is, the pedestal level 29 of each horizontal scanning period is sampled, the sample value is held in the integrating circuit 20, and the reference value Vrefg
By controlling the clamp circuits 21 and 22 whose outputs give the pedestal level using the difference signal 20a from the integrating circuit 20, the pedestal level 29 is made to match each horizontal scanning period. . Note that capacitors 25 and 26 in FIG. 8 are for DC cut.

As explained above, the flicker prevention circuit already developed by the applicant detects the difference between the peak values of the sync chip levels in even and odd fields, and controls the automatic gain controller using the difference signal. The level is kept constant between fields, and the pedestal level is kept constant by sampling the pedestal level every horizontal scanning period, finding the difference from the reference value, and controlling the clamp level using the difference signal. Even if the circuit that converts it into a frame signal has temperature characteristics or changes over time, it is almost unaffected by these.
Fritzka can be suppressed. In addition, since the video signal level and pedestal level are automatically adjusted, it is highly suitable for mass production.

<Problems to be Solved by the Invention> Although the anti-flicker circuit shown in FIG. 8 has many advantages as described above, it still has the following problems.

In other words, flicker actually occurs when the level of the video signal appearing on the screen of a television receiver or the like does not match between the through field signal and the delayed field signal. Even if the levels of the video signals are made to match each other, since the control is indirect, the levels of the video signals will match to each other with a good approximation, but flicker cannot be completely prevented.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a circuit that can extremely effectively prevent flicker by directly controlling the level of a video signal.

<Means for Solving the Problems> The anti-flicker circuit of the present invention which achieves the above-mentioned object repeatedly reproduces a field signal recorded on a track of a recording medium, and reproduces a field signal delayed by 1/2 horizontal scanning period. By alternately selecting the signal and the other through field signal every vertical scanning period by switching the switch,
In the conversion circuit for obtaining a frame signal, a clamp circuit matches the pedestal level of the through field signal with the pedestal level of the delayed field signal, and a peak detection circuit detects the peak value of the clamped through field signal. , a peak detection circuit that detects the heak value of the delayed and clamped field signal, a differential amplifier that outputs a signal proportional to the difference between the detected values of both of the peak detection circuits, and an output of the differential amplifier. an automatic gain controller that is controlled by the signal to match the peak value of the through field signal with the peak value of the delayed field signal, and a head that reproduces the field signal from the recording medium and the recording medium traverse the track. The present invention is characterized by comprising a mute circuit which inputs a track feed signal indicating relative movement and stops the operation of the automatic gain controller for a predetermined period of time after input of the track feed signal.

<Function> The clamp circuit matches the pedestal level of the through field signal with the pedestal level of the delayed field signal, and the peak detection circuit matches the peak value of the through field signal with the peak value of the delayed field signal. By this detection, the video signal level in each field is directly detected. Therefore, when the difference in video signal level between fields is determined by a differential amplifier and the difference signal is input to an automatic gain controller, the automatic gain controller operates so that the difference signal becomes zero. As a result, the video signal level of each field is directly detected, and the gain is automatically controlled so that it matches between the fields, completely eliminating flicker.

What should be noted here is that the video signal level depends on the picture and can vary greatly, such as around 3 times, depending on the picture, so the loop gain of the automatic gain control should be set quite large, for example several hundred times. However, on the other hand, if the loop gain is large, it will take a long time to stabilize the control, that is, the pull-in time, and if the video signal level changes significantly, large flickers will occur for a while. Therefore, when the video signal level changes significantly, it is necessary to mute the automatic gain control for a while.

Here, the situations in which the video signal level changes significantly are as follows: (a) In so-called still recording, where a still image is recorded on each track of a recording medium, from playback of one track to playback of the next track. (b) When performing a high-speed search in still recording; (c) When performing a high-speed search in so-called movie recording in which moving images are recorded over multiple tracks on a recording medium. In either case, the head for reproducing field signals from the recording medium crosses the track, so either the head itself moves and a track feed signal indicating that it crosses the track, or the recording medium moves and the head crosses the track. When a track sending signal indicating that the track is crossed is input to the mute circuit, the mute circuit holds the gain of the automatic gain controller constant and stops the control operation for a while. As a result, even if the video signal level changes greatly when the head crosses the track, flickering does not occur, and the loop gain of the automatic gain control can be set as large as necessary.

Example 1 FIG. 1 shows an example of the present invention. This embodiment is an example in which the present invention is applied to field signal/frame signal conversion when still images are field-recorded to form concentric tracks on a magnetic disk 30. In FIG. 1, 31 is a motor that rotationally drives the magnetic disk 30, 32 is a magnetic head, 33 is a head feeding device that moves the magnetic head 31 in a direction across the track and positions it on a desired track, and 34 is a one-track magnetic head. A switch 35 is used to issue various head feed commands such as forward direction, reverse direction, high speed search, etc., and 35 is a circuit that performs signal processing such as amplification and demodulation on the output signal of the magnetic head. In addition, 1 is a regenerated field signal, 2 is a 0.5H delay circuit such as a delay line, and 3 is a 0.5H delay circuit such as a delay line.
is a changeover switch, 4 is a delayed field signal, 5 is a frame signal, 9 is a control signal for changeover switch 3, and 12 is an automatic gain controller. It is the same as the thing. Furthermore, 36 is a field signal passed through the automatic gain controller 12, 37 is a clamp circuit that matches the pedestal level of the through field signal and the pedestal level of the delayed field signal, 38 is a clamped through field signal, 39 is a delayed and clamped field signal; 40 and 41 are peak detection circuits that detect the peak value (video signal level) of each clamped field signal; 42 is a differential amplifier; 43
is a mute circuit, and 44 is a track feed signal output from the head feed device 33.

First, the anti-flicker operation will be explained with reference to FIGS. 2a to 2d. Now, the reproduction signal processing circuit 35
When the field signal 1 is repeatedly outputted from the delay circuit 2 as shown in FIG.
Field signal 4 delayed by 0.5H as shown in
is output. This field signal 4 is generally attenuated and the pedestal level is shifted compared to the through signal. In FIG. 2b, reference numeral 45 indicates the pedestal level of the through field signal 1.
Therefore, the through field signal and the delayed field signal are made to have the same pedestal level with each other by the clamp circuit 37.
FIG. 2c shows the clamped through field signal 38, and FIG. 2d shows the delayed and clamped field signal 39. However, it is sufficient that the pedestal levels match each other, and the absolute value does not matter. The two types of field signals 38 and 39 whose pedestal level has been clamped in this way are sent to a peak detection circuit 40 and a peak detection circuit 40, respectively.
41, and Vp 1 and Vp ₁ are shown in Figure 2c and d, respectively.
A peak value designated Vp ₂ is detected. The peak values Vp ₁ and Vp ₂ detected here are the video signal levels indicated by 38a and 39a in c and d of the same figure, respectively, since the pedestal levels match between the two types of field signals. Therefore, the differential amplifier 42
is _the difference signal ΔV ₌ K(Vp ₁ −
Vp ₂ ), and this difference signal is sent to automatic gain controller 1.
2 as a control signal 12a,
When ΔV>0, the delayed field signal is smaller than the through field signal, so the gain of the automatic gain controller 12 automatically increases in proportion to ΔV, and conversely, when ΔV<0, the gain increases. Automatic control is performed so that Vp ₁ =Vp ₂ . That is, the video level of the delayed field signal 36 output from the automatic gain controller 12 matches the video level of the through field signal.

Next, the mute operation will be explained with reference to FIGS. 3a and 3b. Now, suppose that a still image recorded on a certain track is being played back and viewed during a certain period indicated by reference numeral 46 in FIG. Therefore, assume that the track feed switch 34 is pressed as shown in FIG. 3b. Then, this switch 34
The head feeding device 33 feeds the head in the forward or reverse direction one track at a time depending on the meaning of the head, or in the forward or reverse direction for high-speed searching. When these heads are fed, the on signal of the switch 34 or the head feeding device 3 is used as the track feed signal 44.
A drive pulse signal of a stepping motor (not shown) for driving a head feed, etc. generated in the head feed drive unit 3 is input to a mute circuit 43. Then, the mute signal 12b is outputted from the mute circuit 43 to the automatic gain controller 12 only during the period indicated by reference numeral 47 in FIG.
During this time, the gain is kept constant for 47 minutes. Thereafter, the gain is automatically controlled again, and the still image recorded on the desired track can be viewed. The length of the mute period 47 is sufficient as long as it covers the time from when the head 32 starts to feed until it is positioned on the desired track, and for example, the length is 47 mm.
φ, track width 100μm, track pitch 100μm,
For example, in the case of a magnetic disk with 50 tracks, it only takes a few seconds.

<Specific example> A specific circuit example of the flicker prevention circuit shown in Fig. 1 is as follows.
It is shown in Figure 4. In FIG. 4, the automatic gain controller 12 has two control terminals A and B, and one control terminal A receives a control signal 12a from a differential amplifier 42.
(ΔV) is input, a reference voltage Vref ₂ is input to the other control terminal B, and the gain is controlled in proportion to ΔV+Vref ₂ . 48 is an amplifier, which is provided to increase the loop gain to about 400 times. The clamp circuit 37 at the pedestal level is basically the eighth
Any method using the fieldback clamp loop 18 shown in the figure may be used, but if the sampling pulse 27 in Figure 8 is synchronized with the HD pulse from a commercially available synchronous signal generator (SSG), vertical synchronization will be achieved. In between, it becomes impossible to sample the pedestal level. Therefore, sampling is not performed between vertical synchronous periods, and instead, it is necessary to lengthen the voltage hold time of the integrator circuit 20 by about 4H period, but this will cause a sag between vertical synchronous periods and the response of the fieldback clamp. The problem of poor sex remains. In this embodiment, the pedestal clamp circuit 37 is synchronized with the synchronization separation circuit 49 that separates the synchronization signal from the frame signal 5, and the timing of the change from the sync chip level to the pedestal level in the separated synchronization signal 49a, and the pulse width is A sampling pulse generation circuit 50 that generates a sampling pulse 50a having a width equal to or less than the width of the cutting pulse between vertical synchronous intervals, and this sampling pulse 50.
a sample hold circuit 51 that samples the pedestal level of the frame signal 5 by a;
Sampled pedestal level as reference value
A clamp voltage generation circuit 52 that compares it with Vref ₁ and outputs a difference signal 52a, two clamp circuits 21 that clamp the pedestal level of each field signal of through and delay according to this difference signal 52a,
It consists of 22. This makes it possible to clamp all the vedestal levels, including the vertical synchronization intervals. Also, the voltage hold time is only about 1H, so the response is faster. Next, the peak detection circuits 40 and 41 are positive peak hold circuits each consisting of a diode 53, a capacitor 54, and two resistors 55 and 56, and are coupled to the differential amplifier 42 via an emitter follower circuit 57 with high input impedance. has been done. Peak detection circuit 40, 4
1 voltage hold time is 1V or more, differential amplifier 4
The voltage hold time of 2 is also set to be 1V or more. The mute circuit 43 is a CR integral type delay circuit 5.
8, a discharge transistor switch 59, and a mute transistor switch 60. When the track sending signal 44 is input, the transistor switch 50 is turned on and the delay circuit 5 is turned on.
8's capacitor 61 is discharged, the transistor switch 60 is immediately turned on, and the automatic gain controller 1 is turned on.
Short-circuit between the two control terminals A and B of 2. Due to this short circuit, only a constant value of control voltage can be applied to the automatic gain controller 12, and the automatic gain controller 12 is muted. This mute continues even after the transistor switch 59 is turned off when the track send signal 44 disappears, until the capacitor 61 is charged to a constant voltage and the transistor switch 60 is turned off. Incidentally, even if the automatic gain controller 12 is placed in the through line, contrary to the embodiment, the same effect can be obtained.

Embodiment 2 FIG. 5 shows another embodiment of the present invention. The embodiment shown in FIG. 5 has an automatic gain controller 12 and a peak detection circuit 40, 41 compared to the embodiment shown in FIG.
The difference is that both are placed after the switch 3, and along with this, the peak detection circuits 40 and 41
A switch 62 is provided for switching the input signal for each field. Note that the peak detection circuits 40 and 41
A voltage hold time of 2V or more is required. The operation is the same as in FIG.

<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, the automatic gain controller can be operated by directly detecting the video signal levels of the through field signal and the delayed field signal, which are the causes of flicker. Since it is controlled, flicker can be almost completely removed. In this case, if there is a track feed, the video level changes greatly and it takes time for the control system to stabilize, which in turn increases flicker. Fritzka will also disappear.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a flicker prevention circuit according to an embodiment of the present invention, FIGS. 2 a to d are explanatory diagrams of flicker prevention operation, FIGS. 3 a and b are explanatory diagrams of mute operation, and FIG. 4 is a specific circuit diagram, FIG. 5 is a block diagram of another embodiment, FIG. 6 is a conventional flicker prevention circuit diagram, FIG. 7 is an explanatory diagram of the operation of a switch that switches between through and delayed field signals, and FIG. The figure is a diagram of an improved conventional flicker prevention circuit, and FIGS. 9a to 9g are diagrams illustrating its operation. In the drawing, 1 is the reproduced file signal, 2 is
0.5H delay circuit, 3 is a changeover switch, 4 is a delayed field signal, 5 is a frame signal, 12 is an automatic gain controller, 12a is a control signal, 12b is a mute signal, 30 is a magnetic disk, 32 is a magnetic head, 33 is a head feeder, 37 is a pedestal clamp circuit, 38 is a clamped through field signal, 39 is a delayed and clamped field signal, 40 and 41 are peak detection circuits, 42 is a differential amplifier, and 43 is a mute signal. circuit, 4
4 is a track sending signal.

Claims (1)

[Claims] 1. A field signal recorded on a track of a recording medium is repeatedly reproduced, and a field signal delayed by 1/2 horizontal scanning period and a through field signal are reproduced by switching a switch. A conversion circuit that obtains a frame signal by alternately selecting each vertical scanning period includes a clamp circuit that matches the pedestal level of the through field signal with the pedestal level of the delayed field signal; A peak detection circuit that detects the peak value of the through field signal, a peak detection circuit that detects the peak value of the delayed and clamped field signal, and a signal proportional to the difference between the detection values of both of the peak detection circuits. an automatic gain controller that is controlled by the output signal of the differential amplifier to match the peak value of the through field signal with the peak value of the delayed field signal; and an automatic gain controller that outputs the field signal from the recording medium. A mute circuit that inputs a track feed signal indicating that the head to be reproduced and the recording medium move relative to each other across the track, and stops the operation of the automatic gain controller for a predetermined period of time after inputting the track feed signal. An anti-flicker circuit comprising: and.