JPS6184181A - Flicker preventing circuit for field and frame signal conversion - Google Patents

Abstract

PURPOSE:To remove a flicker completely by detecting video signal levels of a through field signal which causes the flicker and a delayed field signal directly and controlling an automatic gain controller. CONSTITUTION:A pedestal clamping circuit 37 equalizes the pedestal level of the through field signal to that of the delayed field signal and peak detecting circuits 40 and 41 detect the peak value of the through field signal and the peak value of the delayed field signal to detect video signal levels of respective fields directly. For the purpose, a differential amplifier 42 finds a difference in video signal level between fields and inputs the difference signal to the automatic gain controller 12, which operates so that the difference signal becomes zero. Consequently, video signal levels of respective fields are detected directly and the gain is controlled automatically so that the levels are equal among the fields, thereby removing a flicker completely.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a circuit that uses beak AGC (automatic gain control) to prevent flicker that occurs when a field signal is converted into an interlaced scanning frame signal.

<Prior Art> In television scanning, so-called interlaced scanning is performed in which horizontal scanning lines are skipped every few lines in order to reduce flickering to the eyes. In general, [2:1] interlaced scanning in which every other line is skipped is widely used.

[2:1] In the interlaced scanning method, one screen (frame) is created by overlapping two coarse screens (fields) created by one vertical scan.The number of field repetitions is, for example, NT.
In the SC system, the rate is 60 times per second, the frame repetition rate is 30 times per second, and a frame is generally represented by 525 horizontal scanning lines. Furthermore, the start point of horizontal scanning is shifted by 7 of the horizontal scanning period (H), that is, 0.5H, between odd-numbered fields and even-numbered fields.

By the way, when recording video signals on magnetic tape, magnetic disks, or other various recording media, one field of signal is assigned to one track, or one field is assigned to one trunk.
It is common to allocate 7 frames of signals. Also, in 1-fee/'1-track recording, the so-called 1-frame L/- records an odd field and an even field one after another.
``There are two-track recording and field recording, which records only either the odd or even field.

For playback of field recording, the so-called fee ""/7 V-1 conversion method is often used, which takes advantage of the strong vertical correlation of video signals and scans the same track twice to create a frame signal from one type of field signal. has been done. This is mainly aimed at improving recording density.
For movies, it is possible to record for a long time, and for stills, it is possible to increase the number of frames. However, when converting a field signal into a frame signal, interlaced scanning cannot be achieved by simply repeating and reproducing the same field signal twice. The reason for this is that for interlaced scanning, the time relationship between the vertical synchronization signal, the horizontal synchronization signal of each line, and the video signal is 0.5 for odd and even fields.
This is because, while it is necessary to have a time shift of 0.5H, simply repeating the same field signal does not result in a time shift of 0.5H.

Therefore, the same field signal 1t that is repeatedly reproduced
- As shown in Figure 6, pass through the 0.5H delay line 2 and select the through field signal 1 and the sail 5H delay field signal 4 alternately every vertical scanning period (1■) using the analog switch 3. What is being done is converting the field signal 1 into a frame signal 5.

Note that if this continues, the interval between vertical synchronization signals will deviate from 1V to 5H, so for example, analog switch 3
It is considered that the selection of contacts a and b is performed as shown in FIG.

In other words, during the period in which the through field signal 1 is selected by the switch control signal 9, only the portion 10 from the front equalization pulse section to the back equalization pulse section is 0.5
H delay field signal 4 can be selected. In any case, to convert a field signal into a frame signal, a circuit is used that selects between a through signal and a 0.5 H delay signal, as shown in FIG.

However, because the delay line 2 not only delays the transmission time but also attenuates the signal to a considerable extent, and because the offset voltage of the analog switch 3 is different between contacts a and b, the converted frame signal 5 has a difference between even and odd fields. A difference occurs between the video signal level and the pedestal level, causing flicker on the screen. In order to prevent flicker, a circuit shown in FIG. 6 has conventionally been adopted. In FIG. 6, 6 is an amplifier, 7 and 8 ij petestal level clamp circuit, VR, i2 gain adjustment potentiometer,
In this 7-bit power prevention circuit, which is a VRzi clamp level adjustment potentiometer, the gain of the amplifier 6 is semi-fixedly adjusted using VRt so that the video signal level is equal for each field in the converted frame signal.
Further, the clamp level is adjusted using VRz so that the pedestal level is equal for each field. However, since the above-mentioned adjustment is performed manually, it is unsuitable for making severe adjustments of −40 dB or more for flicker prevention, and is not suitable for mass production. In addition, the 0.5H delay line 2, analog switch 3, amplifier 6, and clamp circuit 7.81C have temperature characteristics and change over time, so even if you can suppress the 7.81C by adjusting VRI and VRz, However, it was not possible to suppress flicker caused by temperature characteristics or aging.

Therefore, the applicant has already developed a circuit that can automatically prevent flicker occurring in the converter circuit for the ``E''/, L/- signals without being affected by temperature characteristics or changes over time. This automatic flicker prevention circuit has already been developed in a patent application filed in 1973.
8-189202, its outline will be explained with reference to FIGS. 8 and 9. FIG. 8 is a circuit diagram, and FIG. 9 is an explanatory diagram of the operation of the circuit section in FIG. In FIG. 8, 2 is a 0.5H delay line, 3 is an analog switch for field selection, 11 is an AGC loop, and 18 is a feedback crank group. AG
The C loop 11 is connected to the think tin prepel (numeral 28 in Fig. 9).
) is kept constant, and includes an automatic gain controller 12, a field selection switch 3, two input selection switches 13 and 14, two sync tip level peak detectors 15 and 16, and a differential It is composed of an amplifier 17. Here, the switch 3 outputs the 7-rem signal 5 shown in FIG. 9(a), and the input selection switch 13 in FIG.
14 is turned on/off as shown in FIG. 9(C) and FIG. 9(d) by the switch control pulse 23 and inverter 24 shown in FIG. 9(b), respectively. As a result, each peak detector 15
．． 16, frame signals are input every 1V as shown in FIG. 9(el) and FIG. , the other peak detector 16
For example, by inputting the peak value of the sync tip 28 of the odd field detected in the sync chip 28 to the fully differential amplifier 17 and controlling the automatic gain controller 12 with the difference signal 17a, the peak value of the sync tip lag is made to match between the even and odd cylinder fields. There is.

On the other hand, the feedback crank group 18 operates so that the pedestal level (numeral 29 in FIG. 9) is constant, and includes a field selection switch 3, a sampling switch 19, an integrating circuit 20, and two clamp circuits 21. It consists of 22. Reference numeral 27 denotes a sampling pulse. FIG. 9(g) shows the sampling timing of the switch 19. That is, the pedestal level 29 of each horizontal scanning period is sampled, the sampled value is held in the integrating circuit 20, and the reference value is The pedestal level 29 is determined by comparing the clamp circuits 21 and 22 whose outputs are designed to give the pedestal level with the difference signal 20a from the integrating circuit 20.
are set to 4 each and are made to match in the horizontal scanning period. Note that capacitors 25 and 26 in FIG. 8 are for DC cut.

As explained above, according to the anti-flicker circuit already developed by the applicant, the sync chip is detected by detecting the difference between the peak values of the sync chip levels of the even field and the full field and controlling the automatic gain controller with the difference signal. The field signal level is kept constant during all fields, and the pedestal level is sampled every horizontal scanning period to find the difference from the reference value and the clamp level is controlled by the difference signal. Even if the circuit that converts the 7-frame signal into a 7-frame signal has temperature characteristics or changes over time, flicker can be suppressed almost unaffected by these factors. In addition, since the video signal level and pedestal level are automatically adjusted, it is highly suitable for mass production.

<Problems to be Solved by the Invention> Although the 7-stroke force prevention circuit shown in FIG. 8 has many advantages as described above, it still has the following problems.

In other words, flicker actually occurs when the level of the video signal appearing on the screen of a television receiver or the like does not match between the through field signal and the delayed field signal. Even if the levels of the video signals are made to match each other, since the control is indirect, the levels of the video signals will match with a good approximation, but flicker cannot be completely prevented.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a circuit that can extremely effectively prevent 7-point errors by directly controlling the level of a video signal.

Means for Solving the Problems〉 To the anti-flicker circuit of the present invention that achieves the above-mentioned objects)
, a field signal recorded on a track of a recording medium is repeatedly reproduced, and a field signal delayed by an upper horizontal scanning period and a through field signal which is not delayed are alternately selected every vertical scanning period by switching a switch. By doing this, in the conversion circuit that obtains the frame signal, the pedestal level of the through field signal is delayed and 7' (a clamp circuit that matches the pedestal level of the field signal, and the peak value of the clamped through field signal is delayed. a peak detection circuit that detects the peak value of the delayed and clamped field signal, and a differential amplifier that outputs a full signal proportional to the difference between the detection values of both of the peak detection circuits;
an automatic gain controller that is controlled by the output signal of the differential amplifier to match the peak value of the through field signal with the peak value of the delayed field signal; a head that reproduces the field signal from the recording medium; and a recording medium. a mute circuit that inputs a track advance signal indicating that the automatic gain controller moves relatively across the track, and stops the operation of the automatic gain controller for a predetermined period of time after inputting the track advance signal. It is characterized by

The clamp circuit makes the pedestal level of the through field signal match the pedestal level of the delayed field signal, and the peak detection circuit makes the peak value of the through field signal match the peak value of the delayed field signal. By detecting this, the video signal level in each field is directly detected. Therefore, a differential amplifier is used to determine the difference in video signal level between fields, and when the difference signal is input to a fully automatic gain controller, the difference signal is operated to become zero. As a result, the video signal level of each field is directly detected, and the gain is automatically controlled so that it matches between fields, completely eliminating flicker.

What should be noted here is that the video signal level depends on the picture, so it varies considerably depending on the picture, such as around 3 times, so the loop gain of the automatic gain control should be set considerably large.
For example, it is necessary to set it several hundred times, but on the other hand, if the loop gain is large, it will take a long time to stabilize the control, that is, the pull-in time will be long, and if the video signal level changes significantly, it will return for a while and cause a large flicker. It is something that happens. Therefore, when the video signal level changes sharply, it is necessary to mute the automatic gain control for a while.

Here, the following are the cases in which the video signal level changes sharply: (a) In so-called steal recording, where a still image is recorded on each track of a recording medium, the playback of one track changes to the next track. When moving to playback, (b) When performing a high-speed search in the same methyl recording, (c) When performing a full high-speed search in so-called movie recording that records moving images across multiple trunks of a recording medium, etc. . In either case, the head for reproducing field signals from the recording medium crosses the track, so either the track feed signal indicates that the head itself moves and crosses the track, or the recording medium moves and the head tracks the track. When a track feed signal indicating that the track is crossed is input to the mute circuit, the mute circuit holds the gain of the automatic gain controller constant and stops the control operation for a while. As a result, the video signal level changes greatly when the head crosses the track, and the loop gain of the automatic gain control can be set as large as necessary.

<Example 1> FIG. 1 shows an example of the present invention. This embodiment is an example in which the present invention is applied to field signal/frame signal conversion when still images are field-recorded to form concentric tracks on the magnetic disk 30. In FIG. 1, 31 is a motor that rotates the magnetic disk 30t, 32 is a magnetic head, 33 is a head feeding device that moves the magnetic head 31 in a direction across the track and positions it on a desired track, and 34 is a one-track device. A switch 35 is used to command various head feeds such as forward direction, reverse direction, and high-speed search. Reference numeral 35 is a circuit that performs signal processing such as amplification and demodulation on the output signal of the magnetic head. In addition, 1 is a reproduced field signal, 2 is a 0.5H delay circuit such as a #-t delay line, 3 is a changeover switch, 4 is a delayed field signal, 5 is a frame signal, and 9 is a control signal for changeover switch 3. , 12 are automatic balance controllers, which are the same as those shown in FIGS. 6 and 8 with the same reference numerals. Furthermore, 36 is a field signal that has passed through the automatic gain controller 12, 37 is a clamp circuit that matches the pedestal level of the through field signal and the pedestal level of the delayed field signal, 38 is a clamped through field signal, 39 is a delayed and clamped field signal, 40 and 41 are peak detection circuits that detect the peak value (video signal level) of the clamped field signal, 42 is a differential amplifier, 43 is a mute circuit, and 44 is a head This is a track feed signal output from the feed device 33.

First, the 7-return force prevention operation will be explained with reference to FIG. 2 (al) to FIG. 2 (d). Then, the field signal 4 delayed by 0.5 H is outputted from the delay circuit 2 as shown in FIG.

This field signal 4 is generally attenuated and the pedestal level is shifted compared to the through signal 1, Fig. 2 (b
), reference numeral 45 indicates the pedestal level of the through field signal 1. Therefore, the through field signal and the delayed field signal are respectively sent to the clamp circuit 3.
7VC allows the pedestal levels to match each other. FIG. 2(c) shows a clamped through field signal 38, and FIG. 2(d) shows a delayed and clamped field signal 39. However, it is sufficient that the pedestal levels match each other, and the absolute value does not matter. The two types of field signals 38 and 39 whose pedestal levels have been clamped in this way are respectively input to peak detection circuits 40 and 41, as shown in FIG. 2(c),
(d) are Vpl and vp, respectively.

The peak value shown by can be detected. The peak value ept (Vl)2 detected here is the same as the pedestal level between the two types of field signals.
, (d) show the video signal levels indicated by 38a and 39a, respectively. Therefore, the differential amplifier 42 generates a difference signal ΔV=K(Vpx Vpz
)tl-output, and this difference signal is sent to the automatic gain controller 12.
), Δv〉0
When , the delayed field signal is smaller than the through field signal, so the gain of the automatic gain controller 12 automatically becomes dog in proportion to ΔV, and conversely, when ΔV<0, the gain becomes smaller. Automatic control is performed so that Vpl = Vpl. In other words, the automatic gain controller 12
The video level of the delayed field signal 36 output from the through field signal matches the video level of the through field signal.

Next, the mute operation will be explained with reference to FIG. 3(a) and FIG. 3(a). Now, assume that you are playing back and viewing still images recorded on a track during the period indicated by reference numeral 46 in FIG. 3(a), and after that, you are viewing still images recorded on other tracks. Assume that the track advance switch 34 is pressed as shown in FIG. 3(b). Then, depending on the meaning of this switch 34, the head feeding device 33 moves the head forward or backward one track at a time, or moves the head forward or backward for high-speed search. During these head feeds, an ON signal of the switch 34 or a pivot pulse signal of a stepping motor (not shown) generated in the head feed device 33 is inputted to the mute circuit 43 as a track feed signal 44. Then, the mute signal 12 is activated only during the period indicated by reference numeral 47 in FIG. 3(A).
b is output from the mute circuit 43 to the automatic gain controller 12, and the gain is kept constant for 47 during this period. Thereafter, automatic gain control is performed again, and all still images recorded on the desired track can be viewed. The length of the mute period 47 is sufficient as long as it covers the time from when the head 32 starts moving until it is positioned on a desired track. For example, if several 50 magnetic disks are used, it may take only a few seconds.

<Specific Example> A specific circuit example of the 7 stress prevention circuit shown in FIG. 1 is shown in FIG. In FIG. 4, the automatic gain controller 12 is A, B2
Looking down at two control terminals, one control terminal A is connected to a differential amplifier 4.
2, the reference voltage Wefg is input to the other control terminal B, and ΔV + V
Gain is controlled in proportion to refz. 48 is an amplifier, which is provided to increase the loop gain to about 400 times. Basically, the pedestal level clamp circuit 37 may be of any type, such as one using the feedback clamp loop 18 shown in FIG. 8, but the sampling pulse 27 of FIG. If the pedestal level is generated in synchronization with the HD pulse from the pedestal, it will not be possible to sample the pedestal level at vertical intervals.

Therefore, it is necessary not to perform sampling between vertical synchronous periods, and instead to increase the voltage hold time of the integrating circuit 20 to approximately 4H period, but this will cause a sag between vertical synchronous periods and the responsiveness of the feedback clamp. The problem remains that it gets worse. In this embodiment, the pedestal clamp circuit 37 is synchronized with the synchronization separation circuit 49 that separates the synchronization signal from the 7-frame signal 5, and at the time when the separated synchronization signal 49a changes from the sync chip level to the pedestal level. A sampling pulse generation circuit 50 that generates a sampling pulse 50a' whose pulse width is less than or equal to the width of a vertically synchronized cutting pulse, and this sampling pulse 50a.
A sample and hold circuit 51 that clamps the entire pedestal level of the frame signal 5, a clamp voltage generation circuit 52 that compares the sampled pedestal level with a reference value Vrefl and outputs a difference signal 52a, and a clamp voltage generation circuit 52 that outputs a difference signal 52a according to the difference signal 52a. and two clamp circuits 21 and 22 that clamp the entire pedestal level of each delayed field signal. As a result, all pedestal levels, including the vertical synchronization intervals, can be 1-clamped. Further, since the voltage hold time may be approximately IH, the response is quick. Next, the peak detection circuits 40.41 each have a diode 53.41. A positive peak hold circuit consisting of a capacitor 54 and two resistors 55°56,
It is coupled to the differential amplifier 42 via an emitter follower circuit 57 with high input impedance. Peak detection circuit 4
0.41 voltage hold voltage is 1v or more, differential amplifier 4
The voltage hold time of No. 2 is also 17 or more. The mute circuit 43 includes a CR integral type delay circuit 58, a discharge transistor switch 59, and a mute transistor switch 60. When the track transmission signal 44 is input, the transistor switch 59 is turned on and the capacitor 61 of the delay circuit 58 is discharged, and the transistor switch 60 is immediately turned on and the automatic gain controller 1
2, the two control terminals A and B are completely shorted. Due to this short circuit, only a constant value of control voltage is applied to the automatic gain controller 12, and the automatic gain controller 12 is muted. This mute is activated by the transistor switch 5 when the track feed signal 44 disappears.
Even after the transistor switch 9 is turned off, the capacitor 61 is charged to a constant voltage and continues until the transistor switch 60 is turned off. Note that even if the automatic gain controller 12 enters the through line contrary to the embodiment, the same effect can be obtained. The embodiment shown, when compared to the embodiment of FIG.
The difference is that both the peak detection circuit 2 and the peak detection circuit 40.degree. Note that the peak detection circuit 40
The voltage hold time of 41 is required to be 2V or more.O operation is the same as in the case of FIG.

<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, all video signal levels of the through field signal and the delayed field signal, which are the causes of 7-bit loss, are directly detected and the automatic gain controller control, it is possible to almost completely eliminate flicker. In this case, if there is a track advance, the video level changes significantly and it takes time for the control system to stabilize, which in turn increases flicker, but if there is a track shift, the automatic gain control is muted, so There will be no flicker.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a 7 flicker prevention circuit according to an embodiment of the present invention, Figs. 2 (a) to (d) are explanatory diagrams of flicker prevention operation, and Fig. 3 (al, (b) is an explanatory diagram of the mute operation, FIG. 4 is a specific circuit diagram, FIG. 5 is a block diagram of another embodiment, FIG. 6 is a conventional 7-bit power prevention circuit diagram, The figure is an explanatory diagram of the operation of a switch that switches all through and delayed field signals, Figure 8 is a diagram of an improved conventional flicker prevention circuit, and Figures 9 (a) to 9) are explanatory diagrams of its operation. 1 is a reproduced field signal, 2 is a 0.5H delay circuit, 3 is a selector switch, 4 is a delayed field signal, 5 is a frame signal, 12 is an automatic gain controller, 12a is a control signal, 12b is a mute 30 is a magnetic disk, 32 is a magnetic head, 33 is a head feeder, 37 is a pedestal clamp circuit, 38 is a clamped through field signal, and 39 is a delayed and clamped field signal. 40 and 41 are peak detection circuits, 42 is a differential amplifier, 43 is a mute circuit, and 44 is a track feed signal.

Claims (1)

[Claims] A field signal recorded on a track of a recording medium is repeatedly reproduced, and a field signal delayed by 1/2 horizontal scanning period and a through field signal which is not otherwise delayed are reproduced by switching a switch. A conversion circuit that obtains a frame signal by alternately selecting each vertical scanning period includes a clamp circuit that matches the pedestal level of the through field signal with the pedestal level of the delayed field signal; a peak detection circuit that detects the peak value of the field signal; a peak detection circuit that detects the peak value of the delayed and clamped field signal; and outputs a signal proportional to the difference between the detected values of both of the peak detection circuits. an automatic gain controller that is controlled by the output signal of the differential amplifier to match the peak value of the through field signal with the peak value of the delayed field signal, and reproduces the field signal from the recording medium. a mute circuit that inputs a track feed signal indicating relative movement of the recording head and the recording medium across the track, and stops the operation of the automatic gain controller for a predetermined period of time after inputting the track feed signal; An anti-flicker circuit comprising: .