JPS60126981A - Flicker preventing circuit for field signal/frame signal conversion - Google Patents

Abstract

PURPOSE:To prevent automatically the flicker with high response by comparing the output signal of a sample and hold circuit with the reference value to produce a clamping potential signal proportional to the difference of said comparison and also using this output signal to set the pedestal level at a fixed value for signals of both through and delay fields. CONSTITUTION:Peak detectors 40 and 41 detect the peak value of a field signal, i.e., the sink chip level every 1H and feed each detection value to a differential amplifier 29. The amplifier 29 applies a signal proportional to the difference between both input values to an automatic gain controller 24. The controller 24 controls the gain so as to obtain the coincidence between the sink chip levels of signals 17 and 18 of both through and delay fields. A feedback clamp loop 30 holds the pedestal level value of a frame signal 44 obtained by a sampling switch 31 at an integration circuit 32 and also compares it with the reference value Vref to obtain a clamping potential signal 32a proportional to the difference between both values. Both clamping circuits 33 and 34 are controlled with the signal 32a to keep the pedestal level at a fixed value.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a circuit for preventing flicker that occurs when converting a field signal into an interlaced scanning frame signal.
It has particularly good responsiveness, is unaffected by the temperature characteristics and aging of each part of the field/frame conversion circuit, and can prevent flicker without requiring severe adjustment.

<Background Art> In television scanning, so-called interlaced scanning, in which horizontal scanning lines are skipped every few lines, is used to reduce flickering to the eyes. In general, interlaced scanning (2:1) in which every other line is skipped is widely used.

[2:1] In the interlaced scanning method, two coarse screens (fields) created by one vertical scan overlap to form one screen (7 fields).
lem) is made. For example, the field repetition number is NT
In the SC system, the number of repetitions is 60 times per second, the frame repetition rate is 30 times per second, and one frame is generally represented by 525 horizontal scanning lines. Also, in odd and even fields, the starting point of horizontal scanning is the horizontal scanning period (LD 1
, that is, by 0.5H. FIG. 1 shows a typical example of a composite video signal (frame signal) representing a frame.

In the figure, 1 and 2 are composite video signals (field signals) representing fields, where 1 is for an odd field and 2 is for an even field. 3 is the vertical blanking period, 4 is the front equalization pulse, 5 is the vertical synchronization signal, 6 is the cutting pulse, 7 is the pack equalization pulse, 8
9 is a horizontal synchronizing signal, and 9 is a video signal. Section A in FIG. 1 is enlarged and shown in FIG. 2.

10 is the horizontal blanking period, 11 is the front porch, 12
is the pack pouch, 13 is the pedestal level, 1. l: sync tip level.

When recording video signals on magnetic tape, magnetic disks, or other various recording media, one field of signal is assigned to each track, or one field is assigned to each track.
It is common to allocate frame signals. Also, in 1-field/1-track recording, odd and even fields are recorded one after another, so-called 1 frame/track recording.
2 tons? There are two types of recording: field recording, which records only either the odd or even field.

For playback of field recording, the so-called field/frame conversion method is often used, which takes advantage of the strong vertical correlation of video signals and scans the same track twice to create a frame signal from one type of field signal. There is. This is mainly aimed at improving the recording density, making it possible to record for a long time in the case of 6C and movies, and increasing the number of frames in the case of stills. However, when converting a field signal into a frame signal, interlaced scanning cannot be achieved by simply repeating and reproducing the same field signal twice. The reason for this is that for interlaced scanning, as can be seen from FIG. 1, the time relationship between the vertical synchronizing signal 5, the horizontal synchronizing signal 8 of each line, and the video signal 9 is 0.000. While it is necessary to shift by 5H, simply repeating the same field signal requires a shift of 0.
This is because there is no time lag of 5H.

Therefore,! '7! As shown in FIG.
and the analog switch 16 connects the through field signal 17 and the 0.5H delay field signal 18 to 1.
By alternately selecting every vertical scanning period (1■),
Converting field signals to frame signals is performed. Note that if this continues, the interval between the vertical synchronizing signals will deviate from 1 to 0.5 H, so it is considered that, for example, the contacts c and d of the analog switch 16 should be selected as shown in Fig. 4. .

That is, of the period in which the through field signal 17 is selected, the 0.5H delay field signal 18 is selected only in the portion 19 from the front equalization pulse section to the bark equalization pulse section.

In any case, in order to convert the field signal to a frame signal, as shown in Figure 3, there is no circuit to select between the through signal and the 0.5H delay signal, and in order to attenuate the signal to a considerable extent, an analog switch is required. Since the offset voltage of 16 is different at the contact C9d, a difference occurs in the signal level and pedestal level between the even field and the odd field in the converted frame signal, causing flicker on the screen. In order to prevent flicker, a circuit shown in FIG. 5 has conventionally been adopted. In Fig. 5, 20 is an amplifier, 21 and 22 are clamp circuits, 1 is a gain adjustment potentiometer, and VR is a clamp level adjustment? It is a tension meter. In the flicker prevention circuit No. 2, the gain of the amplifier 20 is fully adjusted by VR so that the signal level is equal for each field in the converted frame signal,
Further, the clamp level is adjusted using VR so that the pedestal level is equal for each field. However, since the above-mentioned adjustment is performed manually, it is unsuitable for making severe adjustments of -40 dB or more for flicker prevention, and is not suitable for mass production. In addition, the 0.5H delay line 15, analog switch 16, amplifier 20, and clamp circuit 21.22 have temperature characteristics and change over time, so even if you try to suppress flicker by adjusting VR or VR, However, it was not possible to suppress flicker caused by temperature characteristics or aging.

Therefore, the applicant has already developed a circuit that can automatically prevent flicker occurring in a field signal/frame signal conversion circuit without being affected by temperature characteristics or aging. This automatic flicker prevention circuit has already been developed in a patent application filed in 1983.
The application has been filed as No. 189202, and its outline will be explained with reference to FIGS. 6 and 7. FIG. 6 is a circuit diagram, and FIG. 7 is an explanatory diagram of the operation of each part of the sixth embodiment. 6th
In the figure, 15 is a 0.5H delay line, 16 is an analog switch for field selection, 23 is an AGC loop, and 30 is a feedback clamp loop. AG
The C loop 23 is connected to the sync chip level (numeral 1 in FIG. 2).
4) is operated to be constant, and includes an automatic gain controller 24, a field selection switch 16, two input selection switches 25 and 26, and two peak detectors 27.
．． 28 and a differential amplifier 29.

As a result, the switch 16 outputs the frame signal shown in FIG. 7(a), and the input selection switch 2.5.2 in FIG.
6 is turned on/on as shown in FIG. 7(C) and FIG. 7(di) by the switch control pulse 35 and inverter 36 in FIG.
28 as shown in Fig. 7(e) and 7(f), respectively.
A frame signal is input every v. That is, the peak value of, for example, an even field detected by one peak detector 27 and the peak value of, for example, an odd field detected by the other peak detector 28 are input to the differential amplifier 29, and the difference signal 29a is used for automatic gain control. By controlling the device 24,
The peak values are matched between even and odd fields. If the peak value is constant, the sync level and signal level will be constant.

Regarding the time constant, a time constant is selected that responds at least in field units so that the signal level of the subsequent field F is set to the signal level ti of the previous field.

On the other hand, the feedback clamp loop operates so that the pedestal level (numeral 13 in FIG. 2) remains constant, and includes a field selection switch 16, a sampling switch 31, an integrating circuit 32, and two clamp circuits 33 and 34. It consists of The sampling timing of the switch 31 is shown in the fs7 diagram (b). That is, the pedestal level in each horizontal scanning period is sampled, the sample value is held in the integrating circuit 32, and the reference value V
The pedestal level can be made equal in each horizontal scanning period by comparing the pedestal level with the difference signal 32a from the integrating circuit 32 and controlling the Cla/de circuits 33 and 34, whose outputs are designed to give the pedestal level. I'm letting you do it. The time constant of this feedback clamp loop should be at most several H or less.
The transition between H and Nde is now stable. As a result, even if there are variations in the characteristics of the two clamp circuits 33 and 34, flicker is quickly eliminated. In addition,
Capacitors 37 and 38 in FIG. 6 are for DC' cut.

As explained above, according to the flicker prevention circuit that the applicant has already developed, it detects the difference between the peak values (sync chip level) of even and odd fields and controls the automatic gain controller using the difference signal. The multi-signal level is kept constant between fields, and the pedestal level is kept constant by sampling the pedestal level every horizontal scanning period and controlling the clamp level using a difference signal based on the difference from the reference value. Even if the circuit that converts the field signal to the frame signal has temperature characteristics or changes over time, flicker can be suppressed without being affected by these factors. In addition, the signal level and pedestal level are automatically adjusted, making it highly suitable for mass production.

However, even with such a seven-point force prevention circuit with many advantages, there was still room for improvement in response. That is, since a signal is input to each peak detector 27, 28 only every IV, a hold time of at least 1V is required, which limits the responsiveness of the AGC/RAD.

<Object of the Invention> In view of the above-mentioned problems, the present invention provides a circuit that can automatically prevent flicker occurring in a field signal/frame signal conversion circuit without being affected by temperature characteristics or aging, and with good responsiveness. The purpose is to provide

<Configuration of the Invention> The configuration of the anti-flicker circuit of the present invention that achieves this object is to repeat the same field signal, and to switch between the field signal delayed by two horizontal scanning periods and the through field signal by changing the vertical scanning period. In a circuit that converts into a frame signal by alternately selecting each scan period, (a) a circuit that detects the peak value of the through field signal in each horizontal retrace period at a stage before the above switch; A circuit that detects the peak value of each horizontal retrace period of the delayed field signal, a differential amplifier that outputs the difference between the detection values of both peak detection circuits, and a peak value difference signal that is inserted into the delay or through line. an AGC loop having an automatic gain controller that is controlled by and keeps the sync tip level constant; A circuit that compares the signal with a reference value and generates a clamp potential signal with a potential proportional to the difference between the two, and a circuit that is connected to each through and delay line and generates through and delayed field signals by the output signal of the clamp potential generation circuit. and a feedback clamp loop having two clamp circuits that control the pedestal level of Detecting the peak values of each delayed field signal. Therefore, a signal is constantly input to each peak detection circuit, and the hold time may be approximately IH. This makes the response speed of the AGC operation extremely fast. Of course, since the automatic gain controller is controlled by the difference signal between the peak values of both the through and delayed field signals, the signal levels of the converted frame signals automatically match between the field signals and the delayed field signals. In addition, the pedestal level of the signal after frame conversion is sampled every horizontal scanning period, and the clamp level of both the through and delayed field signals before frame conversion is controlled by the sample value, so the pedestal level of the frame signal is automatically becomes constant. As a result, even if the circuit that converts the field signal into the frame signal has temperature characteristics or changes over time, flicker can be suppressed without being affected by these factors.

Additionally, the signal level and pedestal level are automatically adjusted, eliminating the need for manual adjustment during manufacturing, making it highly suitable for mass production.

<Example> The present invention will be explained below with reference to the drawings. First, an embodiment of the flicker prevention circuit of the present invention shown in FIG. 8 will be described.

The anti-flicker circuit shown in FIG. 8 is an improved version of the circuit shown in FIG.
This is the same as the case shown in FIG. 6, except that the AGO loop 39 is configured by directly applying a signal to each of the switches 1 and 1 from the stage before the field selection switch 16. Follow? 6 in Figure 8.
Components that are the same as those in the figures are given the same reference numerals to avoid redundant explanation.

It should be noted that the emitter four-wire circuits 42 and 43 are used for 1-impedance conversion.The operation of the circuit shown in FIG. 8 will be explained. One peak detector 4
When the field signal 18 passing through the 0.5H delay line 15 is input to 0, the through field signal 17 is simultaneously input to the other peak detector 41. Both peak detectors 40 and 41 detect the peak value of the field signal, that is, the sync tip level, for each IH, and input the detected values to the differential amplifier 29.

The differential amplifier 29 supplies a signal proportional to the difference between the two input values to the automatic gain controller 24, and controls the gain so that the sync tip levels of both the through and delayed field signals 17 and 18 match each other. In this case, both peak detectors 40
．． Since a signal is input to 41 in a sequence different from that in the case of FIG. 6, the voltage hold time may be as short as the IH period. Therefore, the responsiveness of the AGC loop 39 becomes extremely fast.

The feedback clamp loop is shown in Figure 6.
It is exactly the same as 0, and the value of the pedestal level of the frame signal 44 obtained by the sampling switch 31 is transferred to the integrating circuit 3.
The pedestal level is kept constant by controlling the clamp circuits 33 and 34 with the clamp potential signal 32a, which is held at 2 and is compared with the reference value Vref, and whose potential is proportional to the difference between the two. There is.

Note that in FIG. 8, either a peak detector or a sample and hold circuit may be used as the peak detectors 40 and 41, but the detection timing is such that the sync tip level of each field signal is detected as shown in FIG. Must be set.

Next, another example of the feedback clamp loop will be explained as follows.
This will be explained with reference to Figure 0. In FIG. 10, the AGC loop 39 is the same as in FIG. The feedback clamp loop 45 in FIG. 10 has improved response than the feedback clamp loop 30 in FIGS. 6 and 8' and has reduced sag in the vertical synchronization period 5 (see FIG. 1). be. That is, in the case of FIGS. 6 and 8, it is common to operate the sampling switch 31 using an HD pulse from a synchronization signal generator (SSG). Therefore, normally, the pedestal level cannot be sampled during the vertical synchronization period 5, and it is necessary to increase the voltage hold time of the integrating circuit 32 to about 4H period.

The feedback clamp loop 45 in FIG. 10 includes a synchronization signal separation circuit 46 that separates a synchronization signal from the frame signal 44 from the switch 16, a sampling pulse generation circuit 47 that generates a sampling pulse 47a from the separated synchronization signal 46a, and a sampling pulse generation circuit 47 that generates a sampling pulse 47a from the separated synchronization signal 46a. A sample and hold circuit 48 samples the pedestal level of the frame signal 44 based on the pulse 47a, and a clamp voltage generation circuit 4 compares the sample and hold output 48a with a reference value Vr e f and outputs a voltage signal 49a proportional to the difference.
9, and two clamp circuits 33 and 34 connected to each of the through and delay lines. FIG. 11 5] shows the separated synchronization signal 46a. Further, FIG. 11(b) shows the Sanzoringtsu 4rus 47a. This sampling pulse 47a is synchronized with the rising edge of the synchronization signal 46a, that is, the point of change from the sync tip level to the deskle level, and its pulse width is equal to the depth of the vertical synchronization period 5.
The width is the same as that of Yarus 6 (see Figure 1), and it is narrower than the curve.

As a result, the sample and hold circuit 50 detects the pedestal level during all periods including the vertical blanking period 3 (see FIG. 1) of the frame signal 44. The clamp potential generation circuit 49 compares the sampled pedestal level with the reference value Vref and generates a difference signal 49.
A is applied to each clamp circuit 33 and 34 to operate so that the pedestal level of both the through field signal 17 and the delayed field signal 17 and 18 becomes a constant value. Therefore, the feedback clamp loop 45 of this embodiment can clamp the pedestal level during all periods including the vertical blanking period. Also, since the sampling interval is less than IH, the voltage hold time of the sample and hold circuit 48 is IH.
If the period is sufficient, it becomes -, and the response of the feedback clamp loop 45 becomes faster.

In the embodiment described above, the automatic gain controller 24 is 0.5
Although it is placed on the same line as H delay line 15, it may be placed on the through side line.

In this case, as shown in FIG.
It is preferable to reverse the connection between the input terminal of the differential amplifier 29 and the input terminal of the differential amplifier 29.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of a frame signal, Fig. 2 is an enlarged explanatory diagram of part A in Fig. 1, Fig. 3 is a principle circuit diagram of field signal/frame signal conversion, and Fig. 4 is an explanatory diagram of switch operation. , Fig. 5 is a circuit diagram showing a conventional flicker prevention circuit, and Fig. 6 is a circuit diagram showing a conventional flicker prevention circuit.
The figure is a circuit diagram showing an embodiment of the previously applied application, and FIG. 7 is an explanatory diagram of the operation of each part in FIG. Fig. 8 is a circuit diagram showing one embodiment of the present invention, Fig. 9 is an explanatory diagram of the operation of the reporting unit in Fig. 8, Fig. 10 is a circuit diagram of another embodiment, and Fig. 11 is the operation of Fig. 10. The explanatory diagram, FIG. 12, is a circuit diagram of a main part of still another embodiment. In the drawing, 15 is a 0.5H delay line, 16 is a field changeover switch, 17 is a through field No. 43, 18 is a delayed field signal, 24 is an automatic gain controller, 30.45 is a feedback clamp loop, 33.3
4 is a clamp circuit, 39 is an AGC loop, 40.41 is a peak detector, 44 is a frame signal, 46 is a synchronization separation circuit, 47 is a sampling pulse generation circuit, 48 is a sample hold circuit, and 49 is a clamp voltage generation circuit. . Patent Applicant Fuji Photo Film Co., Ltd. Representative Patent Attorney Shibu Mitsuishi (and 1 other person) Figure 2d Figure 35 Figure 4 Figure 5 Figure 5

Claims (1)

[Claims] (1) By repeating the same field signal and alternately selecting a field signal delayed by a horizontal scanning period and a through field signal every vertical scanning period by switching a switch, a frame is generated. In the circuit for converting into a signal, (a) a circuit that detects the peak value of the through field signal in each horizontal retrace period at the stage before the switch, and a circuit for detecting the peak value of the field signal delayed at the stage before the switch; A circuit that detects the peak value of each horizontal retrace period, a differential amplifier that outputs the difference between the detection values of both peak detection circuits, and a differential amplifier that is inserted into the delay or through line and controlled by the peak value difference signal. an AGC loop having an automatic gain controller that keeps the sync tip level constant, and (b) 4 of the frame signals output from the above switch.
A sample-and-hold circuit that samples the death level, a circuit that compares the output signal of this sample-and-hold circuit with a reference value and generates a clamp potential signal with a potential proportional to the difference between the two, and 4 are connected to the through and delay lines. and a feedback clamp loop having two clamp circuits that control the pedestal level of each through and delayed field signal to be constant by the output signal of the clamp potential generation circuit. anti-flicker circuit. (2. In claim 1, the flicker prevention circuit in field signal/frame signal conversion is characterized in that the peak detection circuit is a peak detector having a voltage hold time of approximately an IH period. (3) The flicker prevention circuit in field signal/frame signal conversion according to claim 1, wherein the peak detection circuit is a sample and hold circuit having a voltage hold time of approximately an IH period. (4) Claims In the range 1st term, 2nd term, or 3rd term, the feedback clamp loop inputs the separated sync signal output from the switch and uses it as a sampling pulse for the sample hold circuit from the sync tip level. 7. A power prevention circuit for field signal/frame signal conversion, characterized by having a through circuit that generates a pulse that is synchronized with the point of change to the pedestal level and has a width equal to or less than the width of the cutting pulse. .