JPS60126982A - Flicker preventing circuit for field signal/frame signal conversion - Google Patents

Abstract

PURPOSE:To prevent the flicker automatically and with high response by amplifying the signal converted into a frame signal by a switch through an automatic gain controller and then controlling the gain controller to set the peak value (sink chip level) of the amplified signal at a fixed level after comparing it with the reference value. CONSTITUTION:A sample and hold circuit 48 detects the sink chip level in a period including a vertical blanking period of an amplified frame signal 47 and therefore functions as a peak detecting circuit. A gain control voltage generating circuit 49 compares the output signal 48a of the circuit 48 with the reference value Vref2 and applies a difference signal 49a to an automatic gain controller 24 to control the sink chip level of the signal 47 to be a fixed value. Therefore it is enough to set the voltage holding time of the circuit 48 at about 1H. This accelerate greatly the response speed of an automatic gain control AGC loop 44. As a result, an AGC action is immediately possible in an ON/OFF mode of a power supply or a switch 16. In addition, the peak value is detected by a single circuit 48. This prevents the generation of flicker despite the presence of the temperature characteristics.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a circuit for preventing flicker that occurs when converting a field signal into an interlaced scanning frame signal.
It has particularly good responsiveness, is unaffected by the temperature characteristics and aging of each part of the field/7 frame conversion circuit, and can prevent 7 losses without requiring severe adjustment.

BACKGROUND TECHNOLOGY In television scanning, in order to reduce flickering to the eyes, a so-called cross-over scan is performed in which horizontal scanning lines are skipped every few lines. In general, interlaced scanning in which every other line is skipped (2:1) is widely used. In the (2:1) interlaced scanning method, one screen (frame) is created by overlapping two coarse screens (fields) created by one vertical scan. For example, in the NTSC system, the number of field repetitions is 60 times per second, the number of frame repetitions is 30 times per second, and one frame is generally represented by 525 horizontal scanning lines.

In addition, in odd fields and even fields, the starting point of horizontal scanning is equal to 1 horizontal scanning period, that is, 0.5
H is shifted. FIG. 1 shows a typical example of a composite video signal (frame signal) representing a frame. In the figure, 1 and 2 are composite video signals (field signals) each representing a field, where 1 is an odd field and 2 is an even field. 3 is the vertical blanking period, 4
5 is a front equalization pulse, 5 is a vertical synchronization signal, 6 is a cutting pulse, 7 is a puncture equalization pulse, 8 is a horizontal synchronization signal, and 9 is a video signal. Section A in FIG. 1 is enlarged and shown in FIG. 2. lO is the horizontal blanking period, 11 is the front porch,
12 is the crossbow, 13 is the pedestal level, and 14 is the sink tip level.

By the way, when recording video signals on magnetic tape, magnetic disks, or other various recording media, it is common to allocate one field of signals to each track, and one frame of signals to each track. be. Also 1
Fee k) '7□ Even in track recording, the so-called 17' records odd and even fields one after another.
"/2)", "Tsuku recording", and "Field recording" which records only one field (even or odd).

Playback of field recording takes advantage of the strong vertical correlation of video signals and scans the same track twice.
So-called 7 that creates a frame signal from one type of field signal
f-k)'/ conversion frame method is often used. This is mainly aimed at improving the recording density, making it possible to record for a long time in the case of movies, and increasing the number of frames in the case of stills. However, when converting a field signal into a frame signal, interlaced scanning cannot be achieved by simply repeating and reproducing the same field signal twice. The reason is,
For interlaced scanning, as shown in Figure 1, the time relationship between the vertical synchronizing signal 5, the horizontal synchronizing signal 8 of each line, and the video signal 9 is 0 in odd field 1 and even field 2.
．． This is because, while it is necessary to deviate by 5H, simply repeating the same field signal does not cause a time lag in sail 5H.

Therefore, as shown in FIG.
The field signal is converted into a frame signal by alternately selecting the field signal 18 with a delay of 7 and 0.5H every one vertical scanning period (IV). In addition, as it is, the interval between vertical synchronization signals is 1
Since it deviates from v by 0.5H, it is considered that, for example, the contacts c and d of the analog switch 16 are selected as shown in FIG.

That is, of the period in which the through field signal 17 is selected, the 0.5H delay field signal 18 is selected only in the portion 19 from the front equalization pulse section to the nox and equalization pulse sections.

In any case, in order to convert the field signal to a frame signal, as shown in Figure 3, there is no circuit to select between the through signal and the 0.5H delay signal, and in order to attenuate the signal to a considerable extent, an analog switch is required. Since the offset voltage of 16 is different at the contact C2d, a difference occurs in the signal level and pedestal level between the even field and the odd field in the converted frame signal, causing flicker on the screen. In order to prevent flicker, a circuit shown in FIG. 5 has conventionally been adopted. In FIG. 5, 20 is an amplifier, 21 and 22 are clamp circuits, VR is a gain adjustment potentiometer, and VR2 is a clamp level adjustment potentiometer. In this flicker prevention circuit, the gain of the amplifier 20 is adjusted by VR2 so that the signal level is equal for each field in the converted frame signal, and the gain of the amplifier 20 is adjusted by VR2 so that the pedestal level is equal for each field. Adjust the level. However, since the above-mentioned adjustment is performed manually, it is unsuitable for making severe adjustments of 140^B or more to prevent flicker, and is not suitable for mass production. In addition, the 0.5H delay line 15, analog switch 16, amplifier 20, and clamp circuit 21.22 have temperature characteristics and change over time, so even if you try to suppress flicker by adjusting VR or VR, However, it was not possible to suppress the damage caused by temperature characteristics and aging.

Therefore, the applicant has already developed a circuit that can automatically prevent flicker occurring in a frame signal conversion circuit without being affected by temperature characteristics or aging. This automatic flicker prevention circuit has already been filed as Japanese Patent Application No. 189202/1989, and its outline will be explained with reference to FIGS. 6 and 7.
The figure is a circuit diagram, and FIG. 7 is an explanatory diagram of the operation of each part of the sixth embodiment. In Fig. 6, 15 is a 0.5H delay line, 16 is an analog switch for field selection, and 2
3 is an AGC loop, and 30 is a feedback clamp loop. The AGC loop 23 operates so that the sync tip level (numeral 14 in FIG. 2) is constant, and includes an automatic gain controller 24 and a field selection switch 1.
6. Consists of two input selection switches 25, 26, two peak detectors 27, 28, and a differential amplifier 29.

Here, the switch 16 outputs the frame signal shown in FIG. 7(a), and the input selection switches 25 and 26 in FIG.
is turned on/on by the switch control pulse 35 and inverter 36 in FIG. 7(b) as shown in FIG. 7(C) and FIG. 7(d), respectively. This allows each peak detector 27.2
8 is 1v as shown in Fig. 7(e) and Fig. 7(f), respectively.
A frame signal is input every other time. For example, the peak value of an even field detected by one peak detector 27 and the peak value of an odd field detected by the other peak detector 28 are input to the differential amplifier 29, and the difference signal 29a is used to generate an automatic gain. By controlling the controller 24, the peak values are matched between even and odd fields. If the peak value is constant, the sync level and signal level will be constant. As for the time constant, a time constant is selected that responds at least in field units so that the signal level of the subsequent field matches the signal level of the previous field.

On the other hand, the feedback clamp loop operates so that the pedestal level (numeral 13 in FIG. 2) remains constant. It consists of 34. FIG. 7(g) shows the sampling timing of the switch 31. At the same time, the vedestal level of each horizontal scanning period is sampled, and the sample value is held in the integrating circuit 32, and the reference value Vr is
efl, the clamp circuits 33 and 34 whose outputs are designed to give the pedestal level are connected to the integrator circuit 32.
The pedestal level is made to match in each horizontal scanning period by controlling with the difference signal 32 & from the . The time constant of this feedback clamp looseness is set to be several H or less at most, so that the clamp is stabilized between IH and 2H when the field is switched. For this, 2
Even if there are variations in the characteristics of the two clamp circuits 33 and 34, flicker disappears quickly. Note that capacitors 37 and 38 in FIG. 6 are for DC cut.

As explained above, according to the 7-bit power prevention circuit already developed by the applicant, it is possible to detect the difference between the peak values (sync tip level) of even and odd fields and control the automatic gain controller with the difference signal. The signal level is kept constant between fields, and the pedestal level is kept constant by sampling the pedestal level every horizontal scanning period and controlling the clamp level using the difference signal from the reference value. Even if the circuit that converts the field signal to the frame signal has temperature characteristics or changes over time, it is hardly affected by these factors, and the loss can be suppressed. In addition, since the signal level and pedestal level are automatically adjusted, it is highly suitable for mass production.

However, even with such flicker prevention circuits having many advantages, there is still room for improvement in response.

There was still room for improvement in the flicker prevention effect based on temperature characteristics. That is, the peak detectors 27 and 28 each have 1
Since a signal is input only every v periods, the hold time of the peak detector must be at least IV periods, which limits the responsiveness of the AGC loose. If the response is not fast enough, there is a risk that the AGC loop will not operate when the power is turned on/l-7 or when the input signal is turned on. On the other hand, separate peak voice detectors 27 and 28 are used to detect the peak values of the through and delayed field signals.
Because it is using .

If there is a difference in temperature characteristics between the two peak detectors, this will cause a slight flicker.

<Object of the invention> In view of the above-mentioned problems, the present invention has been made to solve the problems described above.
An object of the present invention is to provide a circuit that can automatically prevent flicker occurring in a conversion circuit for , -E signals without being affected by temperature characteristics or changes over time and with good responsiveness.

<Configuration of the Invention> The configuration of the anti-flicker circuit of the present invention that achieves this object is to repeat the same field signal and to switch between the field signal delayed by one horizontal scanning period and the through field signal. l In a circuit that converts into a frame signal by alternately selecting each vertical scanning period, (a) an automatic gain controller that amplifies the frame signal output from the switch, and each horizontal return of the amplified frame signal; It has a circuit for detecting the peak value of the line period, and a gain control voltage generation circuit that compares the output signal of the peak detection circuit with a reference value and supplies a voltage signal proportional to the difference to the automatic gain controller, (b) A sample hold circuit that samples the pedestal level of the frame signal output from the above switch, and an output signal of this sample hold circuit that keeps the sync tip level of the amplified frame signal constant. A circuit that generates a clamp potential signal with a potential proportional to the difference between the two, and a circuit that is connected to each of the through and delay lines, and the pedestal level of each through and delay field signal is determined by the output signal of the clamp potential generation circuit. A feedback clamp loop having two clamp circuits for constant control.

<Effects of the Invention> In the present invention, a signal converted into a frame signal by a switch is amplified by an automatic gain controller, the peak value (sync chip level) of the amplified frame signal is detected, and the peak value is used as a reference value. The automatic gain controller is controlled so that the comparison results in a constant peak value. Therefore, the peak detection circuit is 1
Moreover, a signal is constantly input to the peak detection circuit. Since the signal is constantly input to the peak detection circuit, the hold time can be as short as the IH period.
As a result, the response of the AGC loop becomes extremely fast. Furthermore, since there is only one peak detection circuit, flicker does not occur even if it has temperature characteristics.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 8 shows an embodiment of the present invention, and FIG. 9 shows operational waveform diagrams of each part thereof. Further, FIG. 10 shows another embodiment.

First, the embodiment shown in FIG. 8 will be explained. In Figure 8,
15 is a 0.5H delay line, 16 is a field changeover switch, 17 is a through field signal, 18 is a delayed field signal, 24 is an automatic gain controller, 3
3 and 34 are clamp circuits, 37 and 38 are DC cut capacitors, 39 to 43 are emitter follower circuits for impedance conversion, 44 is AGC#-7', and 45 is a feedback clamp loop.

The AGC loop 44 in this embodiment includes an automatic gain controller 24 . A sample and hold circuit 48 for sampling the peak or sync tip level of the amplified frame signal 47. A gain control voltage generation circuit 49 that compares the sample hold output 48a with a reference value Vref2 and outputs a voltage signal 49a proportional to the difference. The synchronizing signal separating circuit 501 separates the synchronizing signal from the frame signal 46-, and the sampling pulse generating circuit 51 generates the sampling pulse 51a from the separated synchronizing signal 50a.

FIG. 9(a) shows the separated synchronous signal 450a, and FIG. 9(b) shows the sampling pulse 51a. The sampling pulse 51a is synchronized with the falling query of the synchronization signal 50a, that is, the change point from the digital level to the sync tip level), and its pulse width is the same as the sync level in the melting periods 4 and 7 (see Figure 1). The width of the cut or equalization pulse is equal to or narrower. As a result, the sampling T-Lehonhild circuit 48 operates as a peak detection circuit without detecting the sync tip level during the period including the vertical blanking period 3 (see FIG. 1) of the amplified frame signal 47. do. The gain control voltage generation circuit 49 compares the output signal 48a of the sample and hold circuit 48 with a reference value Vrefz and provides a difference signal 49a to the automatic gain controller 24.

It operates so that the sync tip level of the frame signal 47 is kept at a constant value. Therefore, the voltage hold time of the sample-and-hold circuit 48 may be approximately the IH period.
The responsiveness of the AGC loop 44 becomes extremely fast. Therefore,
AGC operation is performed immediately when the power is turned on/off or when the switch 16 is turned on/off. Also, the detection of the beam value is 1
Unless the circuit 48 is used, the temperature difference will not occur even if there is a temperature characteristic.

On the other hand, the feedback crank group 45 of this embodiment includes the synchronization signal separation circuit 502 that separates the synchronization signal from the frame signal 46 from the switch 16, and the sampling pulse generation circuit that generates the sample pulse 52a from the separated synchronization signal 50a. 52. A sample and hold circuit 53 samples the pedestal level of the frame signal 46 based on this sampling pulse 52a.A clamp voltage generation circuit 54 compares the sample and hold output 53a with a reference value Vrefl and outputs a voltage signal 54a proportional to the difference. and two clamp circuits 33 and 34 connected to each of the through and delay lines. Figure 9 (
C) shows the sampling pulse 52a. This sampling pulse 52a is synchronized with the rising edge of the synchronizing signal 50g, that is, the point of change from the sync tip level to the pedestal level, and its pulse width is equal to that of the cutting pulse 6 of the vertical synchronization period 5 (see FIG. 1). It's the same width or even narrower.

As a result, the sample and hold circuit 53 detects the pedestal level during all periods including the vertical blanking period 3 (see FIG. 1) of the frame signal 46. The clamp potential generation circuit 54 compares the sampled pedestal level with the reference value Vrefx and generates a difference signal 54.
A is applied to each clamp circuit 33 and 34 to operate so that the pedestal level of both the through field signal 17 and the delayed field signal 17 and 18 becomes a constant value. Therefore, the feedback clamp loop 45 of this embodiment can clamp the pedestal level during all periods including the vertical blanking period. Furthermore, since the sampling interval is less than IH, the voltage hold time of the sample and hold circuit 53 is IH.
The good news is that the feedback clamp loop 45 has a faster response time than the H period.

The embodiment shown in FIG. 10 is the same as FIG. 8, except that the AGC loop 55 is slightly different.

This AGC loop 55 consists of an automatic gain controller 24° peak detector 56 and a gain control voltage generating circuit 49, and does not require a sampling pulse generating circuit or the like. Since the peak detector 49 detects the peak value of the amplified frame signal 47, that is, the sync tip level, by setting the voltage hold time to about the IH period, the response of the AGC loop 55 can be reduced as in the case of FIG. Sexuality becomes extremely rapid.

Furthermore, since the peak value is detected by only one circuit 56, flicker is not likely to occur even if there is a temperature characteristic.

Note that the feedback clamp loop 30 shown in FIG. 6 can also be used for each of the feedback clamp loops shown in FIGS. 8 and 10. However, in this case, it is common to generate a sampling pulse 9 using an HD pulse from a synchronization signal generator (SSG) and apply it to the sampling switch 31.

Therefore, normally, the pedestal level cannot be sampled during the vertical synchronization period, and the voltage hold time by the integrating circuit 32 must be made as long as about 4H period. In this regard, the feedback clamp loop 45 in Figs. 8 and 10 clamps even during the vertical synchronization period, so no sag occurs, and the response is fast, so it can be used even when the power is turned on/off or when the switch 160 is turned on/at 17:00. It has the advantage of immediate clamping operation.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of a frame signal, Fig. 2 is an enlarged explanatory diagram of part A in Fig. 1, and Fig. 3 is an explanatory diagram of a frame signal.
-Biy number conversion principle circuit diagram, Figure 4 is an explanatory diagram of switch operation, Figure 5 is a circuit diagram showing a conventional 7-resistance prevention circuit, Figure 6 is a circuit diagram showing an embodiment of a previously applied application. , FIG. 7 is an explanatory diagram of the operation of the reporting unit shown in FIG. 6. FIG. 8 is a circuit diagram showing one embodiment of the present invention, FIG. 9 is an explanatory diagram of the operation of the reporting unit in FIG. 8, and FIG. 1θ is a circuit diagram showing another embodiment. In the drawing, 15 is a 0.5H delay line, 16 is a field changeover switch, 17 is a through field signal, 18 is a delayed field signal, 24 is an automatic gain controller, 30.45 is a feedback clamp loop, 31 is a sampling switch, 32 is an integration circuit, 33 and 34 are clamp circuits, 44 and 55 are AGC loops, and 46 is a frame signal. 47 is an amplified frame signal, 48 is a sample and hold circuit, 49 is a gain control voltage generation circuit, 50 is a synchronization separation circuit, 51 is a sampling pulse generation circuit, 52 is a sampling pulse generation circuit, and 53 is a sample and hold circuit. 54 is a clamp voltage generation circuit, and 56 is a peak detector. Patent Applicant Fuji Photo Film Co., Ltd. Representative Patent Attorney Shibu Mitsuishi (and 1 other person) Figure 2d Figure 3 Figure 4 Figure 5 Figure 5

Claims (1)

[Claims] (1) The same field signal is repeated, and a field signal delayed by one horizontal scanning period and a through field signal are alternately selected every one vertical scanning period by switching a switch. (a) an automatic gain controller that amplifies the frame signal output from the switch, and detects the peak value of the amplified frame signal in each horizontal retrace period; and a gain control voltage generation circuit table for comparing the output signal of the peak detection circuit with a reference value and supplying a voltage signal proportional to the difference to the automatic gain controller, and a sync chip for the amplified frame signal. An AGC loop that keeps the level constant, and (b) a sample hold circuit that samples the pedestal level of the frame signal output from the above switch, and compares the output signal of this sample hold circuit with a reference value and calculates the difference between the two. A circuit that generates a clamp potential signal with a proportional potential, and two clamp channels that are connected to the through and delay lines and control the pedestal level of each through and delay field signal to a constant level by the output signal of the clamp potential generation circuit. What is claimed is: 1. A flicker prevention circuit in field signal/frame signal conversion, comprising: a feedback clamp loop having the following features: (2. In claim 1, the flicker prevention circuit in field signal/frame signal conversion is characterized in that the peak detection circuit is a peak detector having a voltage hold time of approximately an IH period. (3) In claim 1, the peak detection circuit is a sample-and-hold circuit having a voltage hold time of approximately an IH period, and a sampling pulse is output from the switch as a sampling pulse generation circuit for this sample r-over-and-hold circuit. A circuit that separates the synchronization signal from the frame signal, and a circuit that inputs the separated synchronization signal and outputs a pulse that is synchronized with the change point from the pedestal level to the sync tip level and whose width is equal to or smaller than the equalization pulse width. A flicker prevention circuit for field signal/frame signal conversion, characterized in that it has a flicker prevention circuit for field signal/frame signal conversion. A circuit that separates the synchronization signal from the frame signal, and inputs the separated synchronization signal and uses it as a sampling pulse to the sample blue-hold circuit, which is synchronized with the change point from the sync tip level to the pedestal level and is synchronized with the cutting pulse. 1. A flicker prevention circuit in field signal/frame signal conversion, comprising a circuit that generates a pulse having a width equal to or less than the width of the flicker.