JP3230693B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. BACKGROUND OF THE INVENTION Means for Solving the Problems (FIGS. 1 to 5) Operation (FIGS. 1 to 5) Example (1) Overall Configuration (FIG. 1) (2) ) Digital signal processing circuit (FIG. 2) (3) Gate signal generation circuit (FIG. 3) (4) Level detection circuit (FIG. 4) (5) Central processing unit (FIGS. 5 and 6) (6) Effects of the embodiment (7) Other embodiments Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus and can be applied to, for example, a television camera.

[0003]

2. Description of the Related Art Conventionally, in this type of image pickup apparatus, the black level does not fluctuate even when the amplification rate of the image pickup signal is switched by adjusting the black set.

That is, in this type of image pickup apparatus, an image pickup signal output from a solid-state image pickup device is converted into a color signal and amplified to a predetermined level. The amplification factor can be switched.

At this time, the image pickup apparatus converts the correction data previously stored in the memory circuit into an analog signal and adds / subtracts the color signal, thereby correcting the signal level so that the black level becomes equal between the color signals. Further, by switching the correction data in response to the operation of the gain switching operator, the black level does not fluctuate.

[0006]

In an image pickup apparatus, the black level of each color signal is detected at the time of assembly, and correction data is set based on the detection result. If this adjustment work can be automated, the assembly work of the imaging device can be simplified, which is considered to be convenient.

The present invention has been made in view of the above points, and has as its object to propose an image pickup apparatus capable of automating this kind of adjustment work.

[0008]

According to the present invention, there is provided an image pickup means for picking up an image of a desired subject, and an analog / digital conversion circuit for converting an output of the image pickup means into a digital signal and outputting the digital signal. 18, digital signal processing circuits 24 and 26 for performing digital signal processing on the digital signal, a signal level detection circuit 90 for detecting a black level of the digital signal, and a black level detection result of the signal level detection circuit 90 And a control circuit 10 that outputs correction data to the digital signal processing circuits 24 and 26 based on the digital signal processing circuit 24 and 26. The control circuit 10 adds the flare correction signal DF to the digital signal via the digital signal processing circuits 24 and 26. With respect to the obtained flare correction result, the digital signal black level detection result becomes a predetermined value. By adding to generate correction data DP, the pedestal level and black level of the digital signal so as to automatically adjust.

[0009]

[0010]

The control unit adds the flare correction signal to the digital signal of the imaging result, and corrects the flare correction result so that the black level detection result of the digital signal becomes a predetermined value. By generating and adding the DP, the pedestal level and the black level of the digital signal can be automatically adjusted, and the adjustment work of the black set can be automated with a simple configuration.

[0011]

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) Overall Configuration In FIG. 1, reference numeral 1 denotes an imaging apparatus as a whole, which drives a solid-state imaging device (CCD) 2 to image a desired subject.

That is, the image pickup apparatus 1 generates a reference signal with the timing generator (TG) 4 and drives the solid-state image pickup device 2 with the reference signal. The imaging apparatus 1 arranges a stop 6 and a zoom lens 8 in front of the solid-state imaging device 2, thereby forming an image of a subject on the imaging surface of the solid-state imaging device 2 at a desired magnification and brightness.

At this time, the central processing unit (CPU) 10
Detects the magnification of the captured image with the zoom position detection circuit 12, and switches the control of the aperture 6 based on the detection result.
Thereby, even when the magnification changes, the subject can be imaged with the brightness desired by the user.

Further, the image pickup apparatus 1 samples and holds the output signal of the solid-state image pickup element 2 by a sample / hold circuit (S / H) 14 by applying a correlated double sampling technique.
The resulting imaging signal S1 is converted to a VA block circuit 16
Output to

The VA block circuit 16 generates each color signal from the image pickup signal S1, amplifies it at a predetermined amplification factor, and corrects the signal level of each color signal at this time to perform shading correction and the like. Further, by switching the amplification rate, white balance adjustment and gain up adjustment can be performed.

Analog digital conversion circuit (A / D) 1
8 is a color signal SR output from the VA block circuit 16.
To SB are converted into digital signals and output.

The digital signal processing circuit 20 detects a signal level of each of the color signals SR to SB by a predetermined detection circuit, thereby adjusting the black set, adjusting the black balance, adjusting the white balance, adjusting the aperture, and correcting the flare. And outputs the detection result to the central processing unit 10 as necessary. Thus, in the image pickup apparatus 1, by controlling each signal processing circuit in the central processing unit 10 based on the data detection result, white balance adjustment and the like can be performed.

Further, the digital signal processing circuit 20 corrects the signal level of each color signal based on the data detection result, thereby performing flare correction and also generates a correction signal SH for shading correction, and generates the correction signal SH. V via a digital / analog conversion circuit (D / A) 22
Output to the A block circuit 16. Thereby, the imaging device 1
In, shading correction is performed using the correction signal SH generated by the digital signal processing circuit 20.

The video processing circuit 24 receives the color signal processed by the digital signal processing circuit 20, performs gamma processing and knee processing, and sets a pedestal level. The following encoder circuit 26 converts each color signal into a luminance signal and a color difference signal, and then converts it into a video signal and outputs it.

Thus, the image pickup apparatus 1 can pick up an image of a desired subject and output the video signal SV.

(2) Digital Signal Processing Circuit As shown in FIG. 2, the digital signal processing circuit 20 generates various test signals TS by the test signal generation circuit 30 and selects the selectors 32R, 32G, 32B and 34R, 34.
G, 34B. At this time, the test signal is switched based on the output signal of the central processing unit 10. Thus, the digital signal processing circuit 20
In the adjustment mode, various test signals T
S can be used to adjust the VA block circuit 16 and the like, so that the entire operation can be confirmed in the self-diagnosis mode.

Further, the digital signal processing circuit 20 supplies the respective color signals SR to SB, which are digital signals, to the clamp level detection circuit 36, and detects the signal levels of the respective color signals SR to SB at a predetermined timing. Further, the digital signal processing circuit 20 outputs this signal level detection result to a clamp circuit (not shown), thereby setting the clamp level of each of the color signals SR to SB.

The selectors 32R to 32B select the respective color signals SR to SB in the normal operation mode and output the signals to the defect correction circuit 38. In the self-diagnosis mode, the selectors switch the contacts at a predetermined timing. , The color signal SR during one horizontal scanning period of the vertical blanking period.
And selectively outputs a test signal instead of SB. On the other hand, in the adjustment mode, the selectors 32R to 32B are controlled by the central processing unit 10 to switch the contacts at a predetermined timing according to each adjustment item. Various test signals are output in place of .about.SB so that various items can be easily adjusted.

The automatic defect detection circuit 40 detects a defective pixel of the solid-state imaging device 2 by continuously monitoring the signal level of each color signal, and stores the position of the defective pixel in a predetermined memory circuit. The defect correction circuit 38 performs an interpolation operation at the position of the defective pixel according to the contents of the memory circuit. Thereby, the defect correction circuit 38 generates a color signal for correction from the surrounding pixels for the defective pixel, and replaces the color signal of the defective pixel with the generated color signal. Thereby, the defect correction circuit 38 is designed so that the image quality is not significantly deteriorated even when a defect occurs in the solid-state imaging device 2.

The addition circuits 42R to 42B add the flare correction signal output from the flare correction circuit 44 to each color signal, thereby correcting the flare of the captured image. The flare correction circuit 44 generates a flare correction signal based on the calculation result of the central processing unit 10, so that the image pickup apparatus 1 can perform flare correction by a simple adjustment operation.

The selectors 46R-46B are provided with an adder circuit 42.
The output signals of R to 42B are output to the subsequent video processing circuit 24. At this time, when the signal level of the selection signal SEL1 switches, the signal level of the output signal falls to 0 level by switching the contacts. Thereby, the imaging device 1
In, the input level of the video processing circuit 24 is lowered to 0 level as needed in the adjustment mode or the like, so that the circuit blocks after the video processing circuit 24 can be easily adjusted.

The low-pass filter circuit (LPF) 48
The color signal output from the defect correction circuit 38 is output after suppressing noise components by suppressing high frequency components. The shading correction circuits 50 and 52 generate the shading correction signals SH1 and SH2 based on the output signal of the low-pass filter circuit 48. In this embodiment, the shading correction signals SH1 and SH2 control the shading of the black level and the white level with the shading correction signals SH1 and SH2, respectively. to correct.

At this time, the shading correction circuit 52
Based on the operation result D1 of the central processing unit 10, a correction signal SH2 for shading correction is created from each color signal. Thus, the digital signal processing circuit 20 feeds back the shading correction signals SH1 and SH2 to the VA block circuit 16 to perform shading correction.

At this time, the shading correction circuit 50
The correction signal SH1 is output via the selectors 34R to 34B. When the selection signal SEL2 rises, the selectors 34R to 34B selectively output a test signal instead of the correction signal SH1. As a result, in the image pickup apparatus 1, the shading correction signal SH1 and the test signal are selectively output as required, and the adjustment work of the VA block circuit 16 can be simplified.

The data detection circuit 54 detects data for flare correction and white balance adjustment by detecting the signal level and the like of the output signal of the low-pass filter circuit 48. The data detection circuit 54 stores the data of the detection result in the memory circuit of the defect correction circuit 38 for the data for the aperture adjustment. The contents of this memory circuit are accessed from the central processing unit 10 and easily. The aperture can be adjusted.

(3) Gate Signal Generation Circuit Further, the data detection circuit 54 generates a gate signal for data detection by the gate signal generation circuit 68 shown in FIG. Accordingly, in the white balance adjustment mode, the gate signal generation circuit 68 sets the white balance adjustment region by outputting the gate signal GT1 with reference to the signal level of the luminance signal ADY, whereas the self-diagnosis mode and the In the adjustment mode, the timing of test signal detection can be set.

That is, the gate signal generation circuit 68 supplies the luminance signal ADY to the comparison circuits 70 and 72, and outputs a comparison result based on predetermined comparison references PK and LOW. Here, the comparison standards PK and LOW can be set by the central processing unit 10 according to the operation mode. In the white balance adjustment mode, the peak level detected by the peak level detection circuit (not shown) is used. While the first comparison reference PK is set as a reference, a level lower than the first comparison reference PK by a predetermined level is set as the second comparison reference LOW.

As a result, the comparison circuits 70 and 72 detect an area of the luminance level within the range from the first to the second comparison reference, and output the detection result as the level gate LVGT. Thus, in the gate signal generation circuit 68, the first and second comparison references PK
And LOW, various gate signals LVGT can be generated based on the signal level of the luminance signal ADY.

Further, in the gate signal generating circuit 68, a vertical synchronizing signal VD is supplied to the V counter 74, and a horizontal synchronizing signal HD is supplied to the V counter 74 and the H counter 76. After resetting the count value with the vertical synchronizing signal VD, the V counter 74 sequentially counts the horizontal synchronizing signal HD, thereby outputting a count value representing a raster scanning position in the vertical scanning direction. On the other hand, after resetting the count value by the horizontal synchronizing signal HD, the H counter 76 sequentially counts predetermined clock signals, and thereby outputs a count value representing a raster scanning position in the horizontal scanning direction.

The comparison circuit 78 raises the signal level of the output signal when the count value of the V counter 74 falls within the range of the two comparison references UP and DWN based on the two comparison references UP and DWN. Generates a gate signal whose signal level rises at a predetermined raster scanning position in the vertical scanning direction. Similarly, the comparison circuit 80 sets the count value of the H counter 76 based on the two comparison references LFT and RGT,
When entering the range of T, the signal level of the output signal rises, thereby generating a gate signal whose signal level rises at a predetermined raster scanning position in the horizontal scanning direction.

Thus, the gate signal generation circuit 68 can generate various gate signals WHGT whose signal level rises in a predetermined area of the captured image.

Here, the comparison reference U of the comparison circuits 78 and 80
P, DWN and LFT, RGT are the central processing unit 1.
The gate signal generation circuit 68 can switch the timing of the gate signal WHGT according to the operation mode.

The selector 82 switches its operation based on the control signals ARE0 to ARE2 output from the central processing unit 10, and in a self-diagnosis mode or the like, the gate signal WHGT or the blanking signal output from the comparison circuits 78 and 80. While the BLK is selectively output, in the white balance adjustment mode, the level gate LVG is output.
Selectively output T.

Thus, the gate signal generation circuit 68 can select the comparison output of, for example, the comparison circuits 78 and 80 and output the gate signal GT1 whose signal level rises in a desired one horizontal scanning period during the vertical blanking period. Against
The comparison output of the comparison circuit 78 is selected to output a gate signal GT1 whose signal level rises during the video period.

In this embodiment, the gate signal generation circuit 68 outputs the selected output of the selector 82 to the gate circuit 86.
In response to the mode switching signals MSL0 to MSL2 output from the central processing unit 10, first and second gate signals CLR and LC are output from the selected output.
H is generated. As a result, the gate signal generation circuit 68 can selectively use the gate signals CLR and LCH according to the operation mode, simplify the adjustment work, and check the operation mode and the like.

(4) Level Detection Circuit As shown in FIG.
Various signals are detected on the basis of T1. In the white balance adjustment mode, a signal level difference between a red signal and a blue signal with respect to a green signal is detected. That is, the level detection circuit 90 outputs the color signals SR
To SB to the selector 92, and outputs the selection signal via the latch circuit 94.

Here, in the selector 92, the contacts are switched based on a control signal output from the central processing unit 10, whereby the selector 9 is switched in this embodiment.
By switching the two contacts, the signal levels of the respective color signals SR to SB can be detected. Thus, in the white balance adjustment mode, the selector 92 switches the contacts in units of fields, and alternately selects and outputs the red signal SR and the blue signal SB in units of fields. In contrast, in the adjustment mode and the self-diagnosis mode, the contacts are sequentially switched in units of fields,
Thus, the respective color signals SR to SB are sequentially and cyclically output.

The selector 92 receives the output signal of the counter circuit 96 in addition to the color signals SR to SB, thereby selecting a reference signal which rises every three fields in place of the color signals SR to SB. It is made to be able to output. The gate circuit 96 outputs the selected output of the selector 92 to the latch circuit 98 during the period when the signal level of the gate signal GT1 rises, thereby selecting the color signals SR and SB in the white balance adjustment area in the white balance adjustment mode. Output.

On the other hand, in the self-diagnosis mode and the adjustment mode, the gate circuit 96 similarly controls the gate signal GT1.
During the period when the signal level rises, the output signal of the latch circuit 94 is sent out, thereby selectively outputting one horizontal scanning period during the vertical blanking period, a video period, etc., for each of the color signals SR to SB. It has been made like that.

The gate circuit 100 receives the green signal SG via the latch circuit 102 and selectively outputs the green signal SG to the latch circuit 104 during a period in which the signal level of the gate signal GT1 rises.

The subtraction circuit 106 is connected to the selector 10
The output signals of the latch circuits 98 and 104 are received via the output circuits 8 and 110, and the subtraction output is output to the addition circuit 112. As a result, in the white balance adjustment mode,
The level detection circuit 90 alternately outputs a first subtraction signal obtained by subtracting a green signal from a red signal and a second subtraction signal obtained by subtracting a green signal from a blue signal in a field cycle. It has been made to be.

On the other hand, in the adjustment mode and the self-selection mode, the selector 110 lowers the signal level of the output signal to the 0 level, thereby stopping the subtraction processing of the subtraction circuit 106, for example, for adjusting the black level. It is designed to detect data. In the level detection circuit 90, a predetermined subtraction output is input to the selector 108 in addition to the output signal of the latch circuit 98, whereby the contacts of the selector 108 are switched.
The signal level of the subtraction output can be detected.

The adder circuit 112 outputs an output signal to the latch circuit 116 via the AND circuit 114, and feeds back the output signal of the latch circuit 116 as an addition input. Here, in the AND circuit 114, in the white balance adjustment mode, the clear signal C is synchronized with the vertical synchronization signal.
LR is inputted, whereby the addition circuit 1
At 12, the output signals of the selector 108 are cumulatively added in the field cycle. Thereby, the level detection circuit 90
In, a signal level difference between a red signal and a blue signal with respect to a green signal in a white balance adjustment region is cumulatively added at a field cycle via a latch circuit.

On the other hand, in the self-diagnosis mode and the adjustment mode, the subtraction processing of the subtraction circuit 106 is stopped and controlled, so that the signal level of each of the color signals SR to SB in the period during which the gate signal GT1 rises is determined in units of fields. The result of the cumulative addition is obtained.

The selectors 118 and 120 switch the contacts at the field cycle, respectively, and latch the cumulative addition result of the latch circuit 116 at the subsequent latch circuits 122 and 124 at the field cycle. As a result, in the level detection circuit 90, in the white balance adjustment mode, the signal level difference cumulative addition results of the red and blue color signals with respect to the green color signal in the white balance adjustment area are latched by latch circuits 122 and 124, respectively.
To the central processing unit 10
Output to Thus, in the imaging apparatus 1, the white balance is adjusted so that the result of the cumulative addition becomes the zero level.

On the other hand, in the adjustment mode, the level detection circuit 90 sequentially and cyclically accumulates the accumulation results of the signal levels of the respective color signals during the period in which the gate signal GT1 rises in the latch circuits 122 and 124. In this embodiment, in the image pickup apparatus 1, each circuit block is adjusted based on the result of the cumulative addition.

In the self-diagnosis mode, the clear signal CLR input to the AND circuit 114 is generated when the rising edge of the test signal TS inserted during the vertical blanking period
In response to this, the latch circuits 122 and 124 respectively accumulate the cumulative addition results of the signal levels based on the rising timing of each clear signal CLR. . Thus, in the imaging device 1, the test signal inserted during the vertical blanking period is monitored based on the cumulative addition result stored in the latch circuit 122, and based on the cumulative addition result stored in the latch circuit 124, The signal level in the video period is detected, whereby the abnormality of the circuit block can be detected while controlling the aperture 6, for example.

Further, in this embodiment, the level detection circuit 90 supplies the output signal of the latch circuit 98 to the flip-flop circuit (FF) 126, whereby the white balance adjustment is performed via the flip-flop circuit 126, for example, in the white balance adjustment mode. Within the area,
A detection output in which a signal level rises in pixel units of the solid-state imaging device 2 is generated.

The counter 130 receives the signal of the flip-flop circuit 126 via the selector 128 and counts this output signal in the field cycle to detect the number of pixels during the period when the gate signal GT1 rises. Thus, in the imaging device 1, the latch circuit 12
By dividing the cumulative addition result of 2 and 124 by the count value of the counter 130, the signal level of each pixel can be easily detected.

In this embodiment, the selector 128
Switches the contacts based on a predetermined control signal CSL, whereby the level detection circuit 90 can output various count results as needed in operation modes other than the white balance adjustment mode.

With the switching of the operation of the selector 128, the output signal of the latch circuit 98 is input to the selector 128 via the comparison circuit 132.
In the comparison circuit 132, the central processing unit 10
Latch circuit 9 based on comparison reference PRK set by
The comparison result is output for the output signal of No. 8. Thus, in the level detection circuit 90, various reference levels are set as necessary, and the number of pixels of each color signal exceeding the reference level can be detected.

(5) Central processing unit Here, the central processing unit 10 switches the operation based on the serial data input through a predetermined jig when assembling and maintaining the image pickup apparatus 1, thereby switching to the adjustment mode. Switch.

In this state, the central processing unit 10 executes a processing program corresponding to each adjustment item based on the subsequently input control data, thereby automatically adjusting each adjustment item.

Here, as shown in FIG. 5, in the black set adjustment, the central processing unit 10 executes step SP1.
To step SP2, close the aperture 6,
Move to step SP3.

Here, the central processing unit 10 outputs a control signal to the gate signal generation circuit 68, thereby setting the comparison reference LFT, RGT, UP, DWN and switching the contact of the selector 82. Accordingly, the central processing unit 10 generates the gate signal GT1 whose signal level rises in the effective area of the captured image, and then generates the gate signal GT1 in step SP.
Move to 4.

Here, the central processing unit 10 fetches the accumulated addition results latched by the latch circuits 122 and 124, and then stores the accumulated addition results in the counter 130.
Divide by the count value of. That is, in the image pickup apparatus 1, since the aperture 6 is completely closed,
By dividing the cumulative addition result of the latch circuit 122 or 124 by the count value of the counter 130, the black level of each pixel can be detected.

At this time, the central processing unit 10 causes the latch circuits 122 and 124 to latch the accumulated addition results on a field basis, thereby detecting the black level of the color signal for the even field and the odd field. That is, in the output signal of the solid-state imaging device, the black level may fluctuate between fields, and in this case, it is necessary to switch and adjust the black level for each field. Therefore, the central processing unit 10 detects the black level for the even field and the odd field,
The black level is corrected based on this detection result.

When the detection result is obtained, the central processing unit 10 proceeds to the subsequent step SP5, where the central processing unit 10 generates correction data DP so that the black level of the color signal output to the encoder 26 becomes 20H. This correction data DP is output to an addition circuit 140 for setting the pedestal level.
Here, as shown in FIG. 6, the respective color signals SR to SB are added to the shading correction signal SH1 of the black level by the addition circuit 132 in the VA block circuit 16, and then amplified by the gain amplifier 134. The white level shading correction signal SH2 is multiplied.

Further, the color signals SR to SB are converted into digital signals by the following analog digital conversion circuit 18, and then the flare correction signal DF is added by the addition circuits 42R to 42B to correct the flare.
The pedestal level is set by the adder 140 of No. 4. Here, in the central processing unit 10, correction data DP is generated by correcting the set-up level based on the black level detection result, and the correction data DP is added to the color signal by the addition circuit 140, thereby obtaining a pedestal. The black level is set together with the level, whereby the black level is automatically adjusted with a simple configuration.

At this time, the central processing unit 10 switches the correction data DP between the even field and the odd field based on the black level detection result, thereby correcting the change in the black level generated between the fields.

That is, since this fluctuation is repeated in the field cycle, for example, in the state of an analog signal, the fluctuation cannot be completely corrected. However, if the correction data DP is switched to prevent the fluctuation as in this embodiment, the fluctuation of the black level between the fields can be surely prevented.

Subsequently, the central processing unit 10 stores the contents of the correction data DP in the memory circuit, and then proceeds to step SP6, where it determines whether or not the black level has been set for all the color signals. In this case, since a negative result is obtained, the central processing unit 10 proceeds to step SP.
Then, the process proceeds to step 7 and the channel is switched to return to step SP4. This causes the central processing unit 10 to execute step SP.
By repeating the processing loop of 4-SP5-SP6-SP7-SP4 and correcting the black level for all the color signals,
When a positive result is obtained in step SP6, the process proceeds to step SP8.

Here, the central processing unit 10 judges whether or not the black level has been set for all the gains. In this case, if a negative result is obtained, the process proceeds to step SP9 to switch the gain of the gain amplifier 134. That is, in this embodiment, the imaging device 1 can switch the amplification ratio of the color signal to two stages in units of 6 [dB] as compared with the normal operation state by operating a predetermined operation element. Thus, the brightness of the entire screen can be increased. Therefore, when there is an offset voltage in the adder circuit 132 or the like, the black level fluctuates with the switching of the gain.

Therefore, in this embodiment, the central processing unit 10 adjusts the black level for each gain, accumulates the contents of the correction data DP in the memory circuit, and then proceeds to step S
The process moves to P10, and this processing procedure ends. Thus, the central processing unit 10 switches the correction data DP for each gain in the operating state based on the contents of the correction data DP stored in the memory circuit, thereby correcting the black level of each color signal and adjusting the black set. .

At this time, in the central processing unit 10, by setting the black level of each color signal to a predetermined reference level, the black balance is also adjusted.

(6) Effects of Embodiment According to the above configuration, the correction data for pedestal level setting is corrected based on the black level detection result, and the black level is set to a predetermined value. The work of adjusting the black set can be simplified, and assembling work and maintenance work can be simplified accordingly.

(7) Other Embodiments In the above-described embodiment, the case where the black level is set by switching the correction data DP for setting the pedestal level has been described. However, the present invention is not limited to this, and the flare correction is not limited to this. The black level may be set by switching the data DF. That is, in the flare correction data, the value of the correction data DF changes according to the amount of incident light.
Is offset to set the black level to a predetermined level. Even in this case, the black level can be automatically set with a simple configuration.

Further, in the above-described embodiment, the case where the black level is detected in the effective area of the imaging screen and the adjustment is automatically performed has been described. The present invention can be widely applied, for example, in the case where the adjustment is performed by adjusting the predetermined area in the effective area and the black level is detected in this area.

Further, in the above-described embodiment, the case where the black level of each color signal is adjusted to a predetermined reference level has been described. However, the present invention is not limited to this. For example, the black level is adjusted based on a green color signal. The black balance may be adjusted by setting the black levels of the red and blue signals.

Further, in the above-described embodiment, the case where the fluctuation of the black level between the fields is also corrected has been described. However, the present invention is not limited to this, and the correction between the fields may be omitted as necessary. It may be.

[0078]

As described above, according to the present invention, the flare correction signal is added to the digital signal of the imaging result, and the black signal detection result of the digital signal is set to a predetermined value with respect to the resulting flare correction result. By generating and adding correction data such that the following equation is satisfied, the pedestal level and the black level of the digital signal can be automatically adjusted, thus realizing an imaging apparatus capable of automating the work of adjusting the black set with a simple configuration. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an imaging apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the digital signal processing circuit.

FIG. 3 is a block diagram showing a gate signal generation circuit.

FIG. 4 is a block diagram showing a level detection circuit.

FIG. 5 is a flowchart for explaining adjustment of a black level.

FIG. 6 is a block diagram provided for explanation thereof.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Imaging device, 2 ... Solid-state image sensor, 10 ... Central processing unit, 16 ... VA block circuit, 20 ... Digital signal processing circuit, 54 ... Data detection circuit, 68 ...
... Gate signal generation circuit 90... Level detection circuit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 9/44-9/78 H04N 5/14-5/217

Claims (2)

(57) [Claims] An image pickup means for picking up an image of a desired subject, an analog-to-digital conversion circuit for converting an output of the image pickup means into a digital signal and outputting the digital signal, and a digital signal processing circuit for performing digital signal processing on the digital signal If, comprising a signal level detecting circuit for detecting the black level of said digital signal, on the basis of the black level detection result of said signal level detecting circuit, and a control circuit for outputting the corrected data to the digital signal processing circuit, said control The circuit is connected via the above digital signal processing circuit.
Adding the flare correction signal to the digital signal
The flare correction result obtained from the digital signal
So that the black level detection result of the signal becomes a predetermined value.
By generating and adding positive data, the digital
Automatically adjusts the pedestal level of the video signal and the above black level
An imaging device, comprising: (2)The signal level detection circuit is provided with the digital
The black level of the video signal to the even and odd fields
Detected every time, The control circuit is configured to control the even field and the odd field.
Generate and add the correction data according to the
Change of the black level between the fields
Prevent movement Characterized byClaim 1Imaging equipment
Place.