JPS6080226A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6080226A
JPS6080226A JP18824383A JP18824383A JPS6080226A JP S6080226 A JPS6080226 A JP S6080226A JP 18824383 A JP18824383 A JP 18824383A JP 18824383 A JP18824383 A JP 18824383A JP S6080226 A JPS6080226 A JP S6080226A
Authority
JP
Japan
Prior art keywords
thickness
etching
film
deposition
wiring film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18824383A
Other languages
Japanese (ja)
Other versions
JPH0365657B2 (en
Inventor
Michiari Kono
通有 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18824383A priority Critical patent/JPS6080226A/en
Publication of JPS6080226A publication Critical patent/JPS6080226A/en
Publication of JPH0365657B2 publication Critical patent/JPH0365657B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To contrive improvement in covering of level differences and protection of a wiring film when performing deposition and etching alternately by performing only deposition to the predetermined film thickness and then etching after the thickness exceeds said predetermined value. CONSTITUTION:When SiO2 is vapor-deposited by bias spattering, a substrate bias is not applied while a film thickness is 500-1,000Angstrom (in such thickness, etching has virtually no influence on a base wiring film) and it is applied after the thickness exceeds this thickness. Next, deposition and etching are performed by spattering and ion milling respectively. At this time, while the film thickness is 50-1,000Angstrom , only deposition is done and when the thickness exceeds that thickness, etching is done. Consequently, covering of level differences is improved and damages in a wiring film can be prevented.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は半導体基板上に被着された配線膜を覆って絶縁
膜を被着する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of depositing an insulating film over a wiring film deposited on a semiconductor substrate.

(2)技術の背景 一般に眉間絶縁あるいはパッシベーション用絶縁物を堆
積する方法として熱酸化法、化学的な気相成長(CVD
)法、プラズマ中でのCVD法等があるがいづれも半導
体基板が高温度にさらされるため現状では主として物理
的なスパッタ法が用いられている。特に絶縁物のスパッ
タは帯電防止のため高周波(rf)を用い我国では13
.56M11zが使用されている。絶縁物のスパッタ法
としてrf−ダイオード・スパッタ法、さらに磁界をか
けてイオン濃度を上げ被着レートを高くしたrf−マグ
ネトロン・スパッタ法が汎用されている。
(2) Background of the technology Generally, thermal oxidation method, chemical vapor deposition (CVD)
) method, CVD method in plasma, etc., but in both cases, the semiconductor substrate is exposed to high temperatures, so currently physical sputtering methods are mainly used. In particular, sputtering of insulators uses radio frequency (RF) to prevent static electricity, and in Japan, 13
.. 56M11z is used. As sputtering methods for insulators, RF-diode sputtering and RF-magnetron sputtering, in which a magnetic field is applied to increase the ion concentration to increase the deposition rate, are widely used.

スパッタ法により段差のある半導体基板上に被膜を覆う
場合段差部には被膜がなだらかに着かないで深いヒダを
生ずる。第1図fa)において1は半導体基板、2は配
線膜としてのアルミニウム(A1)膜を示し、図はスパ
ッタ法を用いた場合AI膜によって生じた段差を覆って
被着された絶縁膜3に段差部で深い亀裂が生じているこ
とを示す。
When a film is applied to a semiconductor substrate having a step by sputtering, the film does not adhere smoothly to the step, and deep folds are formed. In Fig. 1 fa), 1 is a semiconductor substrate, 2 is an aluminum (A1) film as a wiring film, and the figure shows an insulating film 3 that is deposited to cover the step caused by the AI film when sputtering is used. This indicates that deep cracks have formed at the step.

スパッタ法で第1図fblのようになだらかな被覆にす
るためにつぎのような方法がとられている。
In order to obtain a smooth coating as shown in FIG. 1 fbl using the sputtering method, the following method is used.

(alrf−ダイオード・スパッタ法により半導体基板
にバイアスを印加し絶1i膜の堆積とエツチングを同時
に行って目的を達することができる。第2図+a)ば装
置の要部を示し、21.22は極板、23.24はrf
電源、25は半導体基板、26は25の上に堆積しよう
とする絶縁物をあられす。
(By applying a bias to the semiconductor substrate using the ALRF-diode sputtering method, the deposition and etching of the 1i film can be performed simultaneously to achieve the purpose. Figure 2+a) shows the main parts of the device, and 21.22 shows the main parts of the device. Pole plate, 23.24 is rf
A power source, 25 is a semiconductor substrate, and 26 is an insulator to be deposited on 25.

電源24の電圧を電#23より大きくすると絶縁物26
はアルゴン・イオン(Ar”)にたたかれて飛出し半導
体基板上に堆積する。一方半導体基板25はバイアス電
源23によりΔr+にたたかれてエツチングされる。こ
のようにして同時に半導体基板上へ絶縁物の堆積とエツ
チングを行う。
When the voltage of the power supply 24 is made higher than the voltage of the power supply #23, the insulator 26
is struck by argon ions (Ar) and deposited on the semiconductor substrate. Meanwhile, the semiconductor substrate 25 is struck by Δr+ by the bias power supply 23 and etched. Perform insulator deposition and etching.

(bl 第2図(blに示されるように半導体基板にバ
イアスを印加しないrf−スパッタ装置にイオン・ミリ
ング装置27を同一装置内に41加し、基板を移動して
交互に堆積とエツチングを加える。図において第2図1
8)と同一番号は同一対象を示す。またはイオン・ミリ
ング装置のイオン・ガンをスパッタ装置内の半導体基板
に向けて付加し同時に堆積とエツチングを行う。
(bl) As shown in Figure 2 (bl), an ion milling device 27 is added to an RF-sputtering device in which no bias is applied to the semiconductor substrate in the same device, and the substrate is moved and deposition and etching are applied alternately. .In Figure 2 Figure 1
The same numbers as 8) indicate the same objects. Alternatively, an ion gun of an ion milling device is added toward the semiconductor substrate in a sputtering device to simultaneously perform deposition and etching.

スパッタ法によると加速されたAr イオ/によりたた
き出された絶縁物の粒子は直線的に飛行して堆積される
ため、被着物に段差があると段差部の上向に堆積された
被膜に少しでもオーバ・ハング(第1図(a)の4)が
できると堆積の進行に伴ヮてまずまずオーバ・ハングを
助長してゆきその結果段差部に亀裂を生じる。そのため
オーバ・ハングをエツチングにより削り取りながら堆積
を行うことにより段差被覆の改善ができる。
According to the sputtering method, insulating particles ejected by accelerated Ar ions fly in a straight line and are deposited, so if there is a step in the deposited material, the film deposited above the step may be slightly affected. However, if an overhang (4 in FIG. 1(a)) is formed, the overhang will be promoted as the deposition progresses, and as a result, cracks will occur at the stepped portion. Therefore, step coverage can be improved by performing deposition while removing overhangs by etching.

しかしながら段差被覆を改良するため上記の方法を実行
するとAIの酸化をm+止しているA1表面に自然に生
成した20人程度の厚さの機械的に強固なアルミナ(Δ
1zO,)膜をエツチング過程で損傷し、次式に示され
るように絶縁膜とAIが反応してAIの損耗を来し設計
上の電落容量がとれないばかりか信頼性の面でも極めて
危険である。
However, when the above method is carried out to improve the step coverage, a mechanically strong alumina (Δ
1zO,) film is damaged during the etching process, and the insulating film and AI react as shown in the following equation, causing wear on the AI, which not only fails to meet the designed capacitance, but is also extremely dangerous in terms of reliability. It is.

3StOz+4Al →2A1203 +3S 1(3
)従来技術と問題点 上述のように段差被覆の改良と配線膜の損耗防止ば利害
相反する条件によって制約をうけるためAIの損耗分を
見込んで当初より厚くする等の方法が考えられるが、損
耗量が一定せず、また一旦損傷を受けたAtは信頼性の
面でもIJ1題がある。
3StOz+4Al →2A1203 +3S 1(3
) Conventional technology and problems As mentioned above, improving the step covering and preventing wear on the wiring film is constrained by conflicting conditions, so methods such as making it thicker than the original in consideration of the wear on the AI can be considered. The amount is not constant, and once At is damaged, there is a problem in terms of reliability.

従って上記2つの要求を充ずような簡便で完全な製造方
法の提供がめられる。
Therefore, it is desirable to provide a simple and complete manufacturing method that satisfies the above two requirements.

(4)発明の目的 本発明は上記従来の欠点を除くため段差被覆を改良し、
しかも配線膜の損耗を防止できる製造方法を提供するこ
とを目的とするものである。
(4) Purpose of the invention The present invention improves the step covering in order to eliminate the above-mentioned conventional drawbacks,
Moreover, it is an object of the present invention to provide a manufacturing method that can prevent wear and tear on the wiring film.

(5)発明の構成 スパッタ法により絶縁膜を少くとも配線膜上に被着する
に際し、最初は該配線膜が以下のエツチングにより実質
的に損傷されない厚さ迄堆積のみを行って被着し、その
後堆積とエツチングを同時にまたは交互に繰返して被着
することを特徴とするものである。
(5) Constitution of the Invention When depositing an insulating film on at least a wiring film by sputtering, the wiring film is initially deposited only to a thickness that will not be substantially damaged by the following etching, It is characterized in that deposition and etching are then repeated simultaneously or alternately.

本発明は絶縁膜被着の際、エツチングにより下地の配線
膜に実質的に影響を与えないような被着厚さ迄エツチン
グを行わないで堆積のみにして配線膜を保護し、この厚
さを過ぎると仕息に堆積とエツチングを同時または交互
に行い所望の段差被覆が得られるようにするものである
In the present invention, when depositing an insulating film, the wiring film is protected by only being deposited without etching to a thickness that does not substantially affect the underlying wiring film. After that, deposition and etching are performed simultaneously or alternately to obtain the desired step coverage.

(6)発明の実施例 本発明の実施例を3の(2)技術の背景で述べた(a)
(6) Embodiments of the invention Embodiments of the invention are described in 3.(2) Technical background (a)
.

(b)2つの方法について絶縁膜として酸化シリコン(
S102)、配線膜としてAIを用いた場合につい゛ζ
説明する。
(b) Regarding the two methods, silicon oxide (
S102), when using AI as the wiring film ゛ζ
explain.

(al バイアス・スパッタ法によりS i Oz ヲ
被着するときはまづ膜厚が500〜1000人迄は基板
バイアスを印加しないで、この厚さを超えてから印加す
る。
(When depositing SiOz by the bias sputtering method, first do not apply a substrate bias until the film thickness is 500 to 1000 mm, and then apply it after this thickness is exceeded.

(bl 堆積をスパッタ法でエツチングをイオン・ミリ
ングで同時または交互に行うときも膜厚が500〜10
00人迄は堆積のみを行い、この厚さを超えてからエツ
チングを加える。
(bl) Even when deposition is performed by sputtering and etching is performed simultaneously or alternately by ion milling, the film thickness is 500 to 100 nm.
00, only deposition is performed, and etching is added after this thickness is exceeded.

以上の方法により下地のAll!tIは保護される。Using the above method, the base layer is all! tI is protected.

本発明においては絶縁膜としてSiO2,配線膜として
AIを用いたがこれら材料を変更しても発明の要旨を変
更するものではない。
In the present invention, SiO2 is used as the insulating film and AI is used as the wiring film, but changing these materials does not change the gist of the invention.

(7)発明の詳細 な説明したように配線膜上に絶縁膜を被着する際、筒車
に段差被覆の改良と配線膜の保護ができるようになり、
確実な生産性が得られ信頼性の向上に極め°C有効であ
る。
(7) As described in the detailed description of the invention, when an insulating film is deposited on a wiring film, it is possible to improve step coverage on the hour wheel and protect the wiring film;
It is extremely effective in achieving reliable productivity and improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は段差被覆を説明する半導体基板の断面図を示し
、第2図(alはバイアス式rf−ダイオ−1′・)、
バッタ装置、第2図(l))はバイアスなしのrf−ダ
イオ−1゛・スパッタ装置にイオン−ミリング装置をイ
」加した場合の概略図を示す。 1.25−−−半導体基板、2−−−一配線映、3−−
絶縁膜、21.22・−一−−極板、23.24 ・−
r「電源、26−絶縁物、27−− −イオン・ガン。 第1 目 茅2″1
FIG. 1 shows a cross-sectional view of a semiconductor substrate to explain step coverage, and FIG. 2 (al is bias type RF-diode-1'),
Batter Apparatus, FIG. 2(l)) shows a schematic diagram of an unbiased RF-diode-1 sputter apparatus with an ion-milling apparatus added. 1.25---semiconductor substrate, 2---one wire reflection, 3---
Insulating film, 21.22・--Polar plate, 23.24・-
r"Power supply, 26-Insulator, 27-- -Ion gun. 1st eye 2"1

Claims (1)

【特許請求の範囲】[Claims] スパッタ法により絶縁膜を少くとも配線膜上に被着する
に際し、最初は該配線膜が以下のエツチングにより実質
的に損傷されない厚さ迄堆積のみを行って被着し、その
後堆積と工・7チングを同時にまたは交互に繰返して被
着することを特徴とする半導体装置の製造方法。
When depositing an insulating film on at least a wiring film by a sputtering method, the wiring film is first deposited to a thickness that will not be substantially damaged by the following etching, and then deposited and etched. 1. A method for manufacturing a semiconductor device, characterized in that coating is repeatedly deposited simultaneously or alternately.
JP18824383A 1983-10-07 1983-10-07 Manufacture of semiconductor device Granted JPS6080226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18824383A JPS6080226A (en) 1983-10-07 1983-10-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18824383A JPS6080226A (en) 1983-10-07 1983-10-07 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6080226A true JPS6080226A (en) 1985-05-08
JPH0365657B2 JPH0365657B2 (en) 1991-10-14

Family

ID=16220286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18824383A Granted JPS6080226A (en) 1983-10-07 1983-10-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6080226A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214123A (en) * 1988-02-23 1989-08-28 Tel Sagami Ltd Plasma processing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01214123A (en) * 1988-02-23 1989-08-28 Tel Sagami Ltd Plasma processing device

Also Published As

Publication number Publication date
JPH0365657B2 (en) 1991-10-14

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