JPH0365657B2 - - Google Patents
Info
- Publication number
- JPH0365657B2 JPH0365657B2 JP18824383A JP18824383A JPH0365657B2 JP H0365657 B2 JPH0365657 B2 JP H0365657B2 JP 18824383 A JP18824383 A JP 18824383A JP 18824383 A JP18824383 A JP 18824383A JP H0365657 B2 JPH0365657 B2 JP H0365657B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- deposition
- etching
- semiconductor substrate
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000151 deposition Methods 0.000 claims description 17
- 238000004544 sputter deposition Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 230000008021 deposition Effects 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 15
- 239000012212 insulator Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- -1 argon ions Chemical class 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体基板上に被着された配線膜を覆
つて絶縁膜を被着する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method of depositing an insulating film over a wiring film deposited on a semiconductor substrate.
(2) 技術の背景
一般に層間絶縁あるいはパツシベーシヨン用絶
縁物を堆積する方法として熱酸化法、化学的な気
相成長（CVD）法、プラズマ中でのCVD法等が
あるがいづれも半導体基板が高温度にさらされる
ため現状では主として物理的なスパツタ法が用い
られている。特に絶縁物のスパツタは帯電防止の
ため高周波（rf）を用い我国では13.56MHzが使
用されている。絶縁物のスパツタ法としてrf―ダ
イオード・スパツタ法、さらに磁界をかけてイオ
ン濃度を上げ被着レートを高くしたrf―マグネト
ロン・スパツタ法が汎用されている。(2) Background of the technology Generally, there are thermal oxidation methods, chemical vapor deposition (CVD) methods, CVD methods in plasma, etc. as methods for depositing interlayer insulation or passivation insulators, but all of these methods require that semiconductor substrates are At present, the physical sputtering method is mainly used because it is exposed to temperature. In particular, spatter of insulating materials uses radio frequency (RF) to prevent static electricity, and in Japan, 13.56MHz is used. The RF-diode sputtering method and the RF-magnetron sputtering method, which increases the deposition rate by applying a magnetic field, are commonly used as sputtering methods for insulators.
スパツタ法により段差のある半導体基板上に被
膜を覆う場合段差部には被膜がなだらかに着かな
いで深いヒダを生ずる。第１図ａにおいて１は半
導体基板、２は配線膜としてのアルミニウム
（A1）膜を示し、図はスパツタ法を用いた場合
A1膜によつて生じた段差を覆つて被着された絶
縁膜３に段差部で深い亀裂が生じていることを示
す。スパツタ法で第１図ｂのようになだらかな被
覆にするためにつぎのような方法がとられてい
る。 When a film is applied to a semiconductor substrate having steps by the sputtering method, the film does not adhere smoothly to the steps, and deep folds are formed. In Figure 1a, 1 shows a semiconductor substrate, 2 shows an aluminum (A1) film as a wiring film, and the figure shows a case using the sputtering method.
It is shown that deep cracks have formed in the insulating film 3, which is deposited to cover the step caused by the A1 film, at the step. In order to obtain a smooth coating as shown in FIG. 1b using the sputtering method, the following method is used.
(a) rf―ダイオード・スパツタ法により半導体基
板にバイアスを印加し絶縁膜の堆積とエツチン
グを同時に行つて目的を達することができる。
第２図ａは装置の要部を示し、２１，２２は極
板、２３，２４はrf電源、２５は半導体基板、
２６は２５の上に堆積しようとする絶縁物をあ
らわす。電源２４の電圧を電源２３より大きく
すると絶縁物２６はアルゴン・イオン（Ar+）
にたたかれて飛出し半導体基板上に堆積する。
一方半導体基板２５はバイアス電源２３により
Ar+にたたかれてエツチングされる。このよう
にして同時に半導体基板上へ絶縁物の堆積とエ
ツチングを行う。(a) By applying a bias to the semiconductor substrate using the RF-diode sputtering method, the purpose can be achieved by simultaneously depositing and etching an insulating film.
Figure 2a shows the main parts of the device, 21 and 22 are electrode plates, 23 and 24 are RF power supplies, 25 is a semiconductor substrate,
26 represents the insulator to be deposited on 25. When the voltage of the power source 24 is made larger than the voltage of the power source 23, the insulator 26 becomes argon ions (Ar + ).
It flies out and is deposited on the semiconductor substrate.
On the other hand, the semiconductor substrate 25 is powered by the bias power supply 23.
Etched by being hit by Ar + . In this way, the insulator is simultaneously deposited and etched onto the semiconductor substrate.
(b) 第２図ｂに示されるように半導体基板にバイ
アスを印加しないrf―スパツタ装置にイオン・
ミリング装置２７を同一装置内に付加し、基板
を移動して交互に堆積とエツチングを加える。
図において第２図ａと同一番号は同一対象を示
す。またはイオン・ミリング装置のイオン・ガ
ンをスパツタ装置内の半導体基板に向けて付加
し同時に堆積とエツチングを行う。(b) As shown in Figure 2b, the RF sputtering device does not apply bias to the semiconductor substrate.
A milling device 27 is added in the same device and the substrate is moved to alternately deposit and etch.
In the figure, the same numbers as in FIG. 2a indicate the same objects. Alternatively, an ion gun of an ion milling device is added toward the semiconductor substrate in a sputtering device to simultaneously perform deposition and etching.
スパツタ法によると加速されたAr+イオンによ
りたたき出された絶縁物の粒子は直線的に飛行し
て堆積されるため、被着物に段差があると段差部
の上向に堆積された被膜に少しでもオーバ・ハン
グ（第１図ａの４）ができると堆積の推進に伴つ
てますますオーバ・ハングを助長してゆきその結
果段差部に亀裂を生じる。そのためオーバ・ハン
グをエツチングにより削り取りながら堆積を行う
ことにより段差被覆の改善ができる。 According to the sputtering method, insulating particles ejected by accelerated Ar + ions fly in a straight line and are deposited, so if there is a step on the deposit, the film deposited above the step will be slightly affected. However, if an overhang (4 in Fig. 1a) is formed, the overhang will be further promoted as the deposition progresses, and as a result, cracks will occur at the stepped portion. Therefore, step coverage can be improved by performing deposition while removing overhangs by etching.
しかしながら段差被覆を改良するため上記の方
法を実行するとA1の酸化を阻止しているA1表面
に自然に生成した20〓程度の厚さの機械的に強固
なアルナミ（A12O3）膜をエツチング過程で損傷
し、次式に示されるように絶縁膜とA1が反応し
てA1の損耗を来し設計上の電流容量がとれない
ばかりか信頼性の面でも極めて危険である。 However, when the above method is carried out to improve the step coverage, the mechanically strong alumina (A1 2 O 3 ) film naturally formed on the A1 surface with a thickness of about 20 mm, which prevents the oxidation of A1, is etched. It is damaged in the process, and the insulating film and A1 react as shown in the following equation, causing wear and tear on A1, which not only prevents the designed current capacity but also poses an extremely dangerous problem in terms of reliability.
3SiO2＋4A1→2A12O3＋3Si
(3) 従来技術と問題点
上述のように段差被覆の改良と配線膜の損耗防
止は利害相反する条件によつて制約をうけるため
A1の損耗分を見込んで当初より厚くする等の方
法が考えられるが、損耗量が一定せず、また一旦
損傷を受けたA1は信頼性の面でも問題がある。
従つて上記２つの要求を充すような簡便で完全な
製造方法の提供が求められる。 3SiO 2 +4A1→2A1 2 O 3 +3Si (3) Conventional technology and problems As mentioned above, improvement of step coverage and prevention of wiring film wear are limited by conditions that conflict with interest.
One possible method would be to make the thickness of A1 thicker to account for wear and tear, but the amount of wear and tear is not constant, and once A1 is damaged, there are problems in terms of reliability.
Therefore, there is a need to provide a simple and complete manufacturing method that satisfies the above two requirements.
(4) 発明の目的
本発明は上記従来の欠点を除くため段差被覆を
改良し、しかも配線膜の損耗を防止できる製造方
法を提供することを目的とするものである。(4) Object of the Invention The object of the present invention is to provide a manufacturing method that improves the step covering in order to eliminate the above-mentioned conventional drawbacks and prevents wear and tear on the wiring film.
(5) 発明の構成
スパツタ法により絶縁膜を少くとも配線配上に
被着するに際し、最初は該配線膜が以下のエツチ
ングにより実質的に損傷されない厚さ迄堆積のみ
を行つて被着し、その後堆積とエツチングを同時
にまたは交互に繰返して被着することを特徴とす
るものである。(5) Structure of the Invention When depositing an insulating film on at least a wiring layer by a sputtering method, the wiring film is initially deposited only to a thickness that will not be substantially damaged by the following etching, It is characterized in that deposition and etching are then repeated simultaneously or alternately.
本発明は絶縁膜被着の際、エツチングにより下
地の配線膜に実質的に影響を与えないような被着
厚さ迄エツチングを行わないで堆積のみにして配
線膜を保護し、この厚さを過ぎると任意に堆積と
エツチングを同時または交互に行い所望の段差被
覆が得られるようにするものである。 In the present invention, when depositing an insulating film, the wiring film is protected by only being deposited without etching to a thickness that does not substantially affect the underlying wiring film. After that, deposition and etching may optionally be performed simultaneously or alternately to obtain the desired step coverage.
(6) 発明の実施例
本発明の実施例を３の(2)技術の背景で述べた
(a)、(b)２つの方法について絶縁膜として酸化シリ
コン（SiO2）、配線膜としてA1を用いた場合につ
いて説明する。(6) Embodiments of the invention Examples of the invention are described in 3.(2) Technical background.
The following describes two methods (a) and (b) in which silicon oxide (SiO 2 ) is used as the insulating film and A1 is used as the wiring film.
(a) バイアス・スパツタ法によりSiO2を被着す
るときはまづ膜厚が500〜1000Å迄は基板バイ
アスを印加しないで、この厚さを超えてから印
加する。(a) When depositing SiO 2 by the bias sputtering method, first do not apply a substrate bias until the film thickness is 500 to 1000 Å, and then apply it after this thickness is exceeded.
(b) 堆積をスパツタ法でエツチングをイオン・ミ
リングで同時または交互に行うときも膜厚が
500〜1000Å迄は堆積のみを行い、この厚さを
超えてからエツチングを加える。(b) Film thickness also increases when deposition is performed by sputtering and etching is performed simultaneously or alternately by ion milling.
Only deposition is performed up to a thickness of 500 to 1000 Å, and etching is added after this thickness is exceeded.
以上の方法により下地のA1膜は保護される。
本発明においては絶縁膜としてSiO2、配線膜と
してA1を用いたがこれら材料を変更しても発明
の要旨を変更するものではない
(7) 発明の効果
以上説明したように配線膜上に絶縁膜を被着す
る際、簡単に段差被覆の改良と配線膜の保護がで
きるようになり、確実な生産性が得られ信頼性の
向上に極めて有効である。 The underlying A1 film is protected by the above method.
In the present invention, SiO 2 is used as the insulating film and A1 is used as the wiring film, but even if these materials are changed, the gist of the invention will not be changed. When applying a film, it becomes possible to easily improve step coverage and protect the wiring film, which is extremely effective in achieving reliable productivity and improving reliability.
第１図は段差被覆を説明する半導体基板の断面
図を示し、第２図ａはバイアス式rf−ダイオー
ド・スパツタ装置、第２図ｂはバイアスなしのrf
−ダイオード・スパツタ装置にイオン・ミリング
装置を付加した場合の概略図を示す。
１，２５……半導体基板、２……配線膜、３…
…絶縁膜、２１，２２……極板、２３，２４……
rf電源、２６……絶縁物、２７……イオン・ガ
ン。
Fig. 1 shows a cross-sectional view of a semiconductor substrate to explain step coverage, Fig. 2a shows a biased RF-diode sputtering device, and Fig. 2b shows a non-biased RF
- Shows a schematic diagram of an ion milling device added to a diode sputtering device. 1, 25...Semiconductor substrate, 2...Wiring film, 3...
...Insulating film, 21, 22... Pole plate, 23, 24...
RF power supply, 26...Insulator, 27...Ion gun.
Claims (1)
に被着するに際し、最初は該配線膜が以下のエツ
チングにより実質的に損傷されない厚さ迄堆積の
みを行つて被着し、その後堆積とエツチングを同
時にまたは交互に繰返して被着することを特徴と
する半導体装置の製造方法。1. When depositing an insulating film on at least a wiring film by sputtering, the wiring film is first deposited to a thickness that will not be substantially damaged by the following etching, and then the deposition and etching are performed. A method for manufacturing a semiconductor device, characterized in that deposition is performed repeatedly at the same time or alternately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18824383A JPS6080226A (en) | 1983-10-07 | 1983-10-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18824383A JPS6080226A (en) | 1983-10-07 | 1983-10-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6080226A JPS6080226A (en) | 1985-05-08 |
| JPH0365657B2 true JPH0365657B2 (en) | 1991-10-14 |
Family
ID=16220286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18824383A Granted JPS6080226A (en) | 1983-10-07 | 1983-10-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6080226A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2652547B2 (en) * | 1988-02-23 | 1997-09-10 | 東京エレクトロン株式会社 | Plasma processing method |
-
1983
- 1983-10-07 JP JP18824383A patent/JPS6080226A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6080226A (en) | 1985-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5801098A (en) | Method of decreasing resistivity in an electrically conductive layer | |
| US4818334A (en) | Method of etching a layer including polysilicon | |
| JP3954667B2 (en) | Method for manufacturing ferroelectric capacitor | |
| KR930011054B1 (en) | Method of forming electrical contact between interconnection layers located at different layer levels | |
| JP2000323436A5 (en) | ||
| JPS63152146A (en) | Method and apparatus for applying and levelling layer forming material | |
| JPS63155671A (en) | Manufacture of semiconductor device | |
| GB1514664A (en) | Method of forming an electrically insulative coating | |
| EP0747502B1 (en) | Improved adhesion layer for tungsten deposition | |
| JPS5871665A (en) | Method of forming thin film transistor | |
| US5028982A (en) | Semiconductor device | |
| GB2267291A (en) | Integrated circuits; depositing silicon compounds using excess hydrogen | |
| JPH0365657B2 (en) | ||
| JPS63117423A (en) | Method of etching silicon dioxide | |
| JPH0214784B2 (en) | ||
| JPH08293487A (en) | Method of etching | |
| JPS5987834A (en) | Forming method of thin-film | |
| US5466495A (en) | Method of manufacturing a magnetic head | |
| JP3288010B2 (en) | Method for forming metal wiring of semiconductor device | |
| JP3120513B2 (en) | Dry etching method | |
| JP2699611B2 (en) | Thin film formation method | |
| JPH06275617A (en) | Oxidation resistant copper thin film, its manufacture, and semiconductor device using the same | |
| JPH10112461A (en) | Manufacture of semiconductor | |
| EP0597526A2 (en) | Method of manufacturing a magnetic head, and magnetic head manufactured by means of said method | |
| EP0620585A1 (en) | Apparatus and method for flattening an insulating layer by etching in a semiconductor device |