JPH0284727A - Thin film formation - Google Patents

Thin film formation

Info

Publication number
JPH0284727A
JPH0284727A JP23686788A JP23686788A JPH0284727A JP H0284727 A JPH0284727 A JP H0284727A JP 23686788 A JP23686788 A JP 23686788A JP 23686788 A JP23686788 A JP 23686788A JP H0284727 A JPH0284727 A JP H0284727A
Authority
JP
Japan
Prior art keywords
thin film
substrate
whose
target
stress
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23686788A
Other languages
Japanese (ja)
Inventor
Keiji Kobayashi
啓二 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23686788A priority Critical patent/JPH0284727A/en
Publication of JPH0284727A publication Critical patent/JPH0284727A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To realize a thin film forming method wherein leak current between wirings can be reduced, stress generating between the wirings and a thin film can be decreased, and the generation of cracks and the disconnection of wirings can be prevented, by sputtering a specified target, and forming, on a substrate, an inorganic thin film whose stress is smaller than or equal to a specified value. CONSTITUTION:A target 14 is used, whose bond gap Eg is 3.5eV<=Eg<=10.0eV and whose resistivity rho is 1 1X10<13>OMEGAcm<=rho<=10<16>OMEGAcm. Material of the target 14 is spread on a substrate 13 by sputtering method, and an inorganic thin film, whose stress is smaller than or equal to 1500kg/cm<2>, is formed. For example, an Al wiring layer 22 is formed on an Si substrate 21; the sample substrate is mounted on an electrode 11 of a sputtering equipment as shown by figure; thereby depositing an insulating layer 23. Concerning to the target 14, material composed of 0.5SiO2-0.1ZrO2-0.4B2O3 is used, whose Eg is 7.4eV and whose rhois 1X10<15>OMEGAcm. After that, an Al wiring layer 24 is again formed on the insulating film 23, and, in this case, the stress in the insulating film 23 becomes 820kg/cm<2>.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体デバイスの層間絶縁膜、保護膜等とし
て用いられる薄膜の形成方法に係わり、特にスパッタ法
により良質の薄膜を形成する薄膜形成方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for forming thin films used as interlayer insulating films, protective films, etc. of semiconductor devices, and in particular, relates to a method for forming thin films used as interlayer insulating films, protective films, etc. The present invention relates to a method for forming a thin film.

(従来の技術) 従来、各種半導体デバイスの層間絶縁膜には、燐酸シリ
カガラス、酸化珪素、窒化珪素等の絶縁膜が用いられて
いる。これらの絶縁膜は配線と接触しているが、絶縁膜
と配線との熱膨脹係数は一般に20倍程度もある。この
ため、温度変化により層間絶縁膜と配線との間に大きな
応力が加わり、配線が切断する等の欠点があった。さら
に、従来の層間絶縁膜は配線間のリーク電流を抑える点
で十分とは言えず、さらにクラック発生の問題も有して
いる。
(Prior Art) Conventionally, insulating films of phosphoric acid silica glass, silicon oxide, silicon nitride, etc. have been used as interlayer insulating films of various semiconductor devices. These insulating films are in contact with the wiring, and the coefficient of thermal expansion of the insulating film and the wiring is generally about 20 times greater. For this reason, a large stress is applied between the interlayer insulating film and the wiring due to temperature change, resulting in a disadvantage that the wiring may be cut. Furthermore, conventional interlayer insulating films are not sufficient in suppressing leakage current between wirings, and also have the problem of cracking.

なお、上記の問題は、LSIの微細化が進んで配線幅が
1μm以下になると、より顕著に現れてくる。また、層
間絶縁膜に限らず半導体デバイスの保護膜にも同様な問
題がある。
It should be noted that the above problem becomes more noticeable as the miniaturization of LSI progresses and the wiring width becomes 1 μm or less. Further, similar problems exist not only in interlayer insulating films but also in protective films of semiconductor devices.

(発明が解決しようとする課題) このように従来、層間絶縁膜や保護膜として用いられる
絶縁膜は、配線材料との熱膨張係数の差により大きな応
力が生じ、クラックの発生や配線の断線を招く問題があ
った。さらに、この種の絶縁膜は、配線間のリーク電流
の点でも十分に満足できるものではなかった。
(Problems to be Solved by the Invention) As described above, insulating films conventionally used as interlayer insulating films or protective films are subject to large stress due to the difference in coefficient of thermal expansion with wiring materials, which can lead to cracks and disconnection of wiring. There was a problem. Furthermore, this type of insulating film is not fully satisfactory in terms of leakage current between wirings.

本発明は、上記事情を考慮してなされたもので、その目
的とするところは、配線間のリーク電流を少なくするこ
とができ、且つ配線等との間に生じる応力を小さくする
ことができ、クラック発生の防止及び配線の断線防止等
をはかり得る薄膜形成方法を提供することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to be able to reduce leakage current between wirings, reduce stress generated between wirings, etc. It is an object of the present invention to provide a thin film forming method that can prevent the occurrence of cracks and disconnection of wiring.

[発明の構成] (課題を解決するための手段) 上記目的を達成するために本発明では、次のようにして
薄膜を形成している。
[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, in the present invention, a thin film is formed in the following manner.

即ち本発明は、バンドギャップEgが3.5eV≦Eg
≦lO,OcV、比抵抗ρが1×1013ΩC≦ρ≦1
×1016Ωcmのターゲットを用い、該ターゲットを
スパッタリングし、このスパッタリングにより叩き出さ
れた材料を基板上に披若し、応力が1500kg/ a
II2以下の無機質薄膜を形成するようにした方法であ
る。
That is, in the present invention, the band gap Eg is 3.5eV≦Eg
≦lO, OcV, specific resistance ρ is 1×1013ΩC≦ρ≦1
Using a target of ×1016 Ωcm, the target was sputtered, and the material ejected by this sputtering was spread on a substrate, and the stress was 1500 kg/a.
This method is designed to form an inorganic thin film of II2 or less.

また本発明は、ターゲットを複数個用い、スパッタ法に
より基板上に被着する薄膜を複数層とし、少なくとも1
層を非晶質、少なくとも他の1層を結晶質とした方法で
あり、さらにスパッタ法により基板上に被着された薄膜
を、アニール又はジッターするようにした方法である。
Further, the present invention uses a plurality of targets and has a plurality of thin films deposited on a substrate by sputtering, and at least one
This is a method in which one layer is amorphous and at least one other layer is crystalline, and the thin film deposited on the substrate by sputtering is further annealed or jittered.

ここで、上記限定理由としては、バンドギャップEgが
3.5cV以下では配線間の絶縁性が悪く、漏洩電流が
大きくなってしまい、Egがl OcV以上ではガラス
或いは無機質の膜を形成することとが困難となるためで
ある。内部応力が1500kg/ c+a2を越えると
、配線の切断やガラスのクラックが著しく増大するから
である。また、比抵抗ρがI×1013Ωcm以下では
保護膜の機能が果たせないばかりか、リーク電流の増大
、素子の電気特性に悪い影響を与えるからである。さら
に、ρが1×1016Ωcl1以上では、無機質の膜形
成ができないばからか、絶縁材料の熱膨張係数が配線材
料よりも著しく小さくなり、絶縁膜のクラックが生じる
からである。
Here, the reason for the above limitation is that if the band gap Eg is less than 3.5 cV, the insulation between wirings will be poor and the leakage current will increase, and if Eg is more than lOcV, a glass or inorganic film may be formed. This is because it becomes difficult. This is because if the internal stress exceeds 1,500 kg/c+a2, the occurrence of wiring breaks and glass cracks will increase significantly. Furthermore, if the specific resistance ρ is less than I×10 13 Ωcm, not only will the protective film fail to function, but it will also increase leakage current and adversely affect the electrical characteristics of the device. Furthermore, if ρ is 1×10 16 Ωcl1 or more, it is not only impossible to form an inorganic film, but also because the coefficient of thermal expansion of the insulating material becomes significantly smaller than that of the wiring material, causing cracks in the insulating film.

また、絶縁膜を2層以上にし、一方は非晶質。Also, the insulating film has two or more layers, one of which is amorphous.

他方は結晶質とした理由は、バンドギャップを大きくす
ることができるばかりではなく、不純物のブロッキング
効果、不働態体化等、絶縁膜の機能をより大きくするか
らである。さらに、アニールやジッターを施すのは、欠
陥の除去、界面での応力低減等に効果があるからである
The reason why the other material is crystalline is that it not only increases the band gap but also enhances the functions of the insulating film, such as impurity blocking effect and passivation. Furthermore, annealing and jitter are performed because they are effective in removing defects, reducing stress at interfaces, and the like.

(作 用) 本発明によれば、多層配線の層間絶縁膜や素子の保護膜
の形成に適用すると、リーク電流、応力の小さい高信頼
性の絶縁膜を形成することができる。例えば、多層配線
の層間絶縁膜を形成した場合、50V印加電圧に対し、
配線間の漏洩電流はlXl0−”A程度と極めて小さく
なり、さらに配線の切断、絶縁膜のクラック等も確実に
なくすことができる。また、絶縁膜を2層に一方を非晶
質他方を結晶質にすることにより、不純物の対ブロック
性、不働態化等に極めて好結果をもたらすことが判った
(Function) According to the present invention, when applied to the formation of an interlayer insulating film of multilayer wiring or a protective film of an element, a highly reliable insulating film with low leakage current and stress can be formed. For example, when forming an interlayer insulating film for multilayer wiring, for an applied voltage of 50V,
The leakage current between the wiring becomes extremely small at about 1X10-''A, and furthermore, it is possible to reliably eliminate disconnection of the wiring and cracks in the insulating film.Also, the insulating film is made of two layers, one of which is amorphous and the other of which is crystalline. It has been found that by improving the quality, very good results can be obtained in blocking impurities, passivation, etc.

(実施例) 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

第1図は本発明の一実施例方法に使用したスパッタ装置
を示す概略構成図である。図中10は真空容器であり、
この容器10内には電極11,12が対向配置されてい
る。下部電極11は接地されており、この電極11上に
は試料基板13が載置されている。上部電極12にはマ
ツチング回路15を介して高周波電源16から高周波電
力が印加されており、この電極12にはターゲット14
が固定されている。また、容器10内にはガス導入口1
7からA「等の不活性ガスが供給され、容器10内のガ
スはガス排気口18から排気されるものとなっている。
FIG. 1 is a schematic diagram showing a sputtering apparatus used in a method according to an embodiment of the present invention. 10 in the figure is a vacuum container,
Inside this container 10, electrodes 11 and 12 are arranged facing each other. The lower electrode 11 is grounded, and a sample substrate 13 is placed on this electrode 11. High frequency power is applied to the upper electrode 12 from a high frequency power source 16 via a matching circuit 15, and a target 14 is applied to the upper electrode 12.
is fixed. In addition, a gas inlet 1 is provided in the container 10.
An inert gas such as A is supplied from 7 to 7, and the gas in the container 10 is exhausted from a gas exhaust port 18.

次に、この装置を用いて多層配線の層間絶縁膜を製造し
た例について説明する。まず、第2図(a)に示す如く
、St基板21上にAl配線層22を形成した。この試
料基板を前記第1図に示す装置の電極11上に載置し、
第2図(b)に示す如く絶縁膜23の堆積を行った。こ
のとき、ターゲット14としては後述する材料を用いた
。その後、絶縁膜23の上に再度/i配線層24を形成
した。
Next, an example in which an interlayer insulating film of a multilayer interconnection is manufactured using this apparatus will be described. First, as shown in FIG. 2(a), an Al wiring layer 22 was formed on an St substrate 21. This sample substrate is placed on the electrode 11 of the apparatus shown in FIG.
An insulating film 23 was deposited as shown in FIG. 2(b). At this time, a material described later was used as the target 14. Thereafter, the /i wiring layer 24 was formed again on the insulating film 23.

また、第2図(b)の変形例として同図(e)に示す如
く、2Bのターゲットを用いて絶縁膜23を2層とした
。このとき、一方の絶縁膜23+を非晶質とし、他方の
絶縁llI23□を結晶質とした。
Further, as a modification of FIG. 2(b), as shown in FIG. 2(e), the insulating film 23 was formed into two layers using a 2B target. At this time, one insulating film 23+ was made amorphous, and the other insulating film llI23□ was made crystalline.

第3図は絶縁体のバンドギャップを示す図であり、半導
体に比べてEgができる限り大きいことが望ましい。単
層ではEgを大きくできないときは複数層にしてEgを
大きくしてもよい。また、配線内と絶縁膜内の応力をで
きる限り小さくするために、両者の材料の熱膨張係数差
を小さくすることが必要である。本実施例で用いたター
ゲット材料及び形成される絶縁膜は以下の通りであり、
また夫々の材料による諸特性を表に示す。なお、各実施
例の材料は 実施例1は0.82 n  0.4S i 02、実施
例2は0.5S f O2o、tz r O20,4t
hOi、実施例3は 1層目が0.9S i 02 0.lA S 20s 
+2層目がSiN+バイアススパッタSiO□、実施例
4は 1層目がARN。
FIG. 3 is a diagram showing the band gap of an insulator, and it is desirable that Eg be as large as possible compared to a semiconductor. If Eg cannot be increased with a single layer, multiple layers may be used to increase Eg. Furthermore, in order to reduce the stress within the wiring and the insulating film as much as possible, it is necessary to reduce the difference in coefficient of thermal expansion between the two materials. The target materials used in this example and the insulating film to be formed are as follows.
The table also shows the characteristics of each material. The materials for each example are 0.82 n 0.4S i 02 for Example 1 and 0.5S f O2o, tz r O20,4t for Example 2.
hOi, in Example 3, the first layer is 0.9S i 02 0. lA S 20s
+2nd layer is SiN+bias sputtered SiO□, and in Example 4, 1st layer is ARN.

2層目が0.8S t 02 0.1B2030.1P
205、実施例5は 1層目がSi、N4゜ 2層目が0.9B 203 0.1B a Oで350
℃のアニールしたもの、 実施例6は 1層目がバイアススパッタによる石英ガラス。
The second layer is 0.8S t 02 0.1B2030.1P
205, in Example 5, the first layer is Si and N4, the second layer is 0.9B 203 0.1B a O and 350
In Example 6, the first layer was quartz glass by bias sputtering.

2層目がクリストバライト結晶、 実施例7は 1層目がバイアススパッタ5in2ガラス。The second layer is cristobalite crystal, Example 7 is The first layer is bias sputtered 5in2 glass.

2層目がプラズマSiO結晶である。The second layer is plasma SiO crystal.

このようなターゲットを用い、スパッタ法により表に示
すような薄膜を形成することにより、バンドギャップ及
び比抵抗が十分大きくミ応力が十分小さい層間絶縁膜を
形成することができる。このため、配線間のリーク電流
が少なく、且つ耐ブロック性、不働態化も良好な半導体
デバイスを実現、することができる。
By forming a thin film as shown in the table by sputtering using such a target, it is possible to form an interlayer insulating film having a sufficiently large band gap and resistivity and a sufficiently small mis-stress. Therefore, it is possible to realize a semiconductor device with less leakage current between wirings and with good block resistance and passivation.

なお、本発明は上述した実施例に限定されるものではな
く、その要旨を逸脱しない範囲で、種々変形して実施す
ることができる。例えば、スパッタ装置は第1図に同等
限定されるものではなく、仕様に応じて適宜変更可能で
ある。具体的には、スパッタ方式として高周波スパッタ
に限らず、直流スパッタ、バイアススパッタ、或いはマ
グネトロンスパッタ等を用いてもよい。
Note that the present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the gist thereof. For example, the sputtering apparatus is not limited to the same as shown in FIG. 1, and can be modified as appropriate according to specifications. Specifically, the sputtering method is not limited to high-frequency sputtering, and direct current sputtering, bias sputtering, magnetron sputtering, or the like may be used.

[発明の効果] 以上詳述したように本発明によれば、スパッタにより薄
膜を堆積する際の材料を選択することにより、配線間の
リーク電流が少なく、配線及び絶縁膜内の応力が少なく
、且つクラック、断線のない高信頼性の絶縁膜を形成す
ることができる。
[Effects of the Invention] As detailed above, according to the present invention, by selecting the material when depositing a thin film by sputtering, leakage current between wirings is small, stress in the wirings and insulating film is small, and Moreover, a highly reliable insulating film without cracks or disconnections can be formed.

従って、各種半導体デバイスの製造に適用して絶大なる
効果を発揮する。
Therefore, it can be applied to the manufacture of various semiconductor devices with great effects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例方法に使用したスパッタ装置
を示す概略構成図、第2図は同実施例により層間絶縁膜
を形成する工程を示す断面図、第3図は良好な絶縁膜の
バンドギャップを示す特性図である。 10・・・真空容器、11.12・・・電極、13・・
・試料、14・・・ターゲット、15・・・マツチング
回路、16・・・高周波電源、17・・・ガス導入口、
18・・・ガス排気口、21・・・Si基板、22.2
4・・・AN配線層、23.23+ 、232・・・層
間絶縁膜。 出願人代理人 弁理士 鈴江武彦
FIG. 1 is a schematic configuration diagram showing a sputtering apparatus used in a method according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the process of forming an interlayer insulating film according to the same embodiment, and FIG. 3 is a diagram showing a good insulating film. FIG. 3 is a characteristic diagram showing the bandgap of 10... Vacuum container, 11.12... Electrode, 13...
- Sample, 14... Target, 15... Matching circuit, 16... High frequency power supply, 17... Gas inlet,
18... Gas exhaust port, 21... Si substrate, 22.2
4...AN wiring layer, 23.23+, 232... interlayer insulating film. Applicant's agent Patent attorney Takehiko Suzue

Claims (3)

【特許請求の範囲】[Claims] (1)バンドギャップEgが3.5eV≦Eg≦10.
0eV、比抵抗ρが1×10^1^3Ωcm≦ρ≦1×
10^1^6Ωcmのターゲットを用い、スパッタ法に
より該ターゲット材料を基板上に被着し、応力が150
0kg/cm^2以下の無機質薄膜を形成することを特
徴とする薄膜形成方法。
(1) Band gap Eg is 3.5eV≦Eg≦10.
0eV, specific resistance ρ is 1×10^1^3Ωcm≦ρ≦1×
Using a target of 10^1^6 Ωcm, the target material was deposited on the substrate by sputtering, and the stress was 150Ω.
A thin film forming method characterized by forming an inorganic thin film of 0 kg/cm^2 or less.
(2)前記ターゲットを複数個用い、前記スパッタ法に
より基板上に被着する薄膜を複数層とし、少なくとも1
層が非晶質、少なくとも他の1層が結晶質であることを
特徴とする請求項1記載の薄膜形成方法。
(2) A plurality of the targets are used, and a plurality of thin films are deposited on the substrate by the sputtering method, and at least one
2. The thin film forming method according to claim 1, wherein the layer is amorphous and at least one other layer is crystalline.
(3)前記スパッタ法により基板上に被着された薄膜を
、アニール又はジッターすることを特徴とする請求項1
又は2記載の薄膜形成方法。
(3) Claim 1 characterized in that the thin film deposited on the substrate by the sputtering method is annealed or jittered.
Or the thin film forming method described in 2.
JP23686788A 1988-09-21 1988-09-21 Thin film formation Pending JPH0284727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23686788A JPH0284727A (en) 1988-09-21 1988-09-21 Thin film formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23686788A JPH0284727A (en) 1988-09-21 1988-09-21 Thin film formation

Publications (1)

Publication Number Publication Date
JPH0284727A true JPH0284727A (en) 1990-03-26

Family

ID=17006974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23686788A Pending JPH0284727A (en) 1988-09-21 1988-09-21 Thin film formation

Country Status (1)

Country Link
JP (1) JPH0284727A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007091020A (en) * 2005-09-28 2007-04-12 Iseki & Co Ltd Traveling vehicle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007091020A (en) * 2005-09-28 2007-04-12 Iseki & Co Ltd Traveling vehicle

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