JPS607773A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate short-circuiting between a base region and an electrode which is provided on an emitter region by a method wherein an SiO2 film and an Si3N4 film which is so thin as impurity ions easily penetrate therethrough are laminatedly deposited on a semiconductor substrate where the base region has been formed, and an Si3N4 film in the proximity of an emitter-contact window is projected. CONSTITUTION:A P type base region 2 is diffusion-grown on the surface layer portion of an N type semiconductor substrate 1. An SiO2 film 3 and a thin Si3N4 film 4 are laminatedly deposited on the entire surface including the region 2. A photoresist film 5, which has an emitter-contact window 6 and a base-contact window 7, is then provided on the film 4. Windows 6 and 7 are formed in the film 4 by etching and at the same time a film 3 exposed inside the window 6 is side-etched by means of a separately provided mask, thereby making the film 4 projected. Thereafter, As<+> ions are implanted and an N type region 9 is formed inside the window 6. An electrode 10 is provided at the central portion of the region 9, whereby short-circuiting between the electrode 10 and the region 2 is prevented due to a space formed below the projected film 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a half-core device which is an improved method for forming an emitter of a bipolar transistor.

[Technical background of the invention and its problems]

In general, the high frequency of the microphone negative wave transistor is 4'! In order to improve the performance, it is necessary to shorten the emitter-base distance by -1 and the emitter width, and to make the emitter-paste junction depth shallower. To shorten the emitter-pace distance, the relative positions of the emitter-contact window and the pace-contact window, which were conventionally formed using mask alignment technology, can now be formed using a self-alignment method. Furthermore, in order to uniformly form a shallow emitter-paste junction, it has recently become common practice to form the emitter region and the paste region by ion implantation.

The conventional manufacturing method for L transistors is shown below from Figure 1 to Figure 3.
This will be explained using the process cross-sectional diagrams shown in FIG.

1 to 3 are cross-sectional views showing the manufacturing process of a conventional microwave NPN bipolar transistor,
FIG. 1 is a cross-sectional view of an N-type semiconductor substrate from which the silicon nitride film (5t3N4) of the emitter contact window and the space contact window has been removed after forming a P-type base region by ion implantation. FIG. 2 is a cross-sectional view of the step of removing the silicon oxide 1 (sto2) of the emitter contact window and implanting arsenic ions. FIG. 3 is a cross-sectional view after removing the silicon oxide film (Sin2) of the space contact window and forming an emitter electrode and a space electrode.

First, in FIG. 1, a silicon oxide film (S102) 3 is grown to a thickness of 1000× on an N-type semiconductor substrate 1 by thermal oxidation. Thereafter, although not shown, a photoresist film is deposited on the silicon oxide film (bio2) J, and the photoresist film is formed in a predetermined pattern by photolithography.

Thereafter, using the turned photoresist film as a mask, ions such as boron (B+), which will become P ions, are implanted into the N-type semiconductor substrate 1, and the P-type base region 2 is implanted into the N-type semiconductor substrate 1.
form. The P i'J base region 2 is activated by annealing.

Next, a silicon nitride film (813N4) 4 is deposited on the silicon oxide film (5102) 3 to a thickness of, for example, 1000 by vapor phase growth.
Grow to a thickness of X. Thereafter, as shown in FIG. 1, holes are simultaneously formed in the photoresist film 5 at positions that will become the emitter contact window 6 and the base contact window 7 for the self-line method by photolithography. Thereafter, the patterned photoresist film 5 is etched using a mask and a silicon nitride film (813N4) is etched using a well-known plasma etching method.
Etch 4. Thereafter, although not shown, a photoresist film is deposited, and only the emitter contact window 6 is opened by drilling or turning. Thereafter, as shown in FIG. 2, the silicon oxide film (51
02) Etch J using a hydrofluoric acid etching solution such as ammonium fluoride (NH,F). After that, a silicon oxide film (8102) 3 and a silicon nitride film (5i3) are formed.
Using N4) 4 as a mask, for example, arsenic ions (As") 8, which become N ions, are applied to the P-type base region 2 at an acceleration energy of 50 keV and a dose of 3 x 1015 cr.
Ion implantation is performed under the conditions of n-2 to form a Vh, NfJJJ emitter region 9. This N type emitter region 9 is 1
Activation is performed by annealing at 000°C for several minutes. Next, although not shown, the base contact window 7 is formed by photolithography.
Drill only the hole. Next, for example, platinum is deposited on the N-type semiconductor substrate 1 to a thickness of, for example, 300× by a well-known vacuum evaporation method. Thereafter, an ohmic contact layer of platinum silicide is annealed at 500° C. and then formed on the N-type semiconductor substrate 1 in the emitter contact window 6 and the base contact window 7.

Thereafter, as shown in FIG. 3, titanium, platinum, and gold are sequentially deposited on the N-type semiconductor substrate 1 by vacuum evaporation, and an emitter electrode 10 and a pace electrode 1 are formed by photolithography.

Now, focusing on the N, H2 emitter region 9 in FIG. 3, when forming the emitter region by diffusion from a diffusion source opposite to the base region, the lateral diffusion distance is Depending on the concentration of the diffusion distance, it is 70% to 80%. On the other hand, when the emitter region is formed by ion implantation, the lateral impurity density spread 9 is smaller than that described above.

For this purpose, silicon nitride #4 emitter contact window 6
The width of the lateral impurity concentration distribution in the emitter region 9 is only slightly wider than the opening width of the emitter region 9.
This is a cause of unstable device characteristics or a significant decrease in device yield υ in microphone four-wave output transistors with a large number of emitter contact windows. In the end, the conventional method TEHA, silicon nitride ([(
In order to increase the passivation effect of 813N4), the thickness of the silicon nitride film (Si2H4) is increased, and in order to accurately control the base width, the depth of the S/S junction is decreased, that is, the arsenic ion implantation energy is decreased. It was a trend. For this reason, silicon nitride film (813N4)
was used as a mask for arsenic ion implantation.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and suppresses the occurrence of emitter-pace short circuit points, stabilizes element characteristics,
An object of the present invention is to provide a method for manufacturing a semiconductor device that improves yield.

[Summary of the invention]

The present invention involves sequentially depositing a silicon oxide film as a first insulating film and a silicon nitride film as a second insulating film on the surface of a semiconductor substrate having a space region, and forming the silicon nitride film thinly. Then, an emitter region is formed so that arsenic ions as impurity ions to be ion-implanted pass through the silicon nitride film, and the paste region under the eaves-like portion of the silicon nitride film of the emitter contact window becomes an opposite conductive window. A method of manufacturing a semiconductor device is characterized in that:

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

4 to 6 show microwave N according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of a PN-type bipolar transistor. FIG. 4 shows an emitter layer after forming a P-type base region by ion implantation.

FIG. 3 is a cross-sectional view of an N-type semiconductor substrate from which the silicon nitride film (813N4) of the spacer contact window and the spacer contact window has been removed. FIG. 5 is a cross-sectional view of the step of removing the silicon oxide k (s! 02 ) of the emitter contact window and implanting arsenic ions. FIG. 6 is a cross-sectional view after removing the silicon oxide film of the space contact window and forming an emitter electrode and a space electrode.

In FIG. 4, a silicon oxide film (SiO□) 3 is deposited on an N-type semiconductor substrate 1 by a thermal oxidation method, for example, at 1500×
Grow to a thickness of . This thickness will be described later. For example, when arsenic ions (As+) are
V and a dose of 3×10 cm to provide a sufficient mask for ion implantation conditions. After that, although not shown, silicon oxidation 1 is applied! A photoresist film is deposited on (bx02)s, and the photoresist film is formed into predetermined grooves and turns by photolithography. Next, using the patterned photorenoids (Ill) as a mask, a boron ion (B
+), for example, by ion implantation under the conditions of acceleration energy 60 keV and dose group 1.5 x 10z,
A mold base region 2 is formed. The P-type base region 2b,
Activation is performed by annealing at 900° C. for 30 minutes. Next, a silicon nitride film (S13N4) 4 is deposited on the silicon oxide film (S102) 3 by a vapor phase growth method, e.g.
Grow to a thickness of . This thickness is set so that arsenic ions (As+) can sufficiently pass through the ion implantation conditions for arsenic ions (As+), which will be described later.

Thereafter, as shown in FIG. 4, holes are simultaneously formed in the photoresist film 5 at positions that will become the emitter contact window 6 and the space contact window 7 for the self-line method by photolithography. Thereafter, using the patterned photoresist film 5 as a mask, the silicon nitride film (bxsN4) 4 is etched by a well-known plasma etching method.

Thereafter, although not shown, a photoresist film is applied, and only the emitter contact window 6 is opened in the photoresist film. The opening at this time is silicon nitride BX (5i3N4
) 4 is the emitter mask to serve as an etching mask.
It may be somewhat wider than the contact window 6. After that, convert the emitter contact window 6 to silicon a (5102)
, 9 are etched by a hydrofluoric acid etching method, for example, ammonium fluoride (NH4F). At this time, i<1 As shown in FIG. 5, the opening of the silicon nitride film (5t3N4) 4 forms an eaves-like structure relative to the opening of the emitter contact window 6 of the silicon oxide film (8102) 3. over etching. Thereafter, arsenic ions (As+) 8, which become N-type ions, are added to the P-type base region 2.
For example, ion implantation is performed at an acceleration energy of 100 keV and a dose of Q 3 x 10'''cm-20 to form an N-type emitter region 9. After that, although not shown, a hole is opened in the resist film only for the pace contact window 7. At this time, the hole is
It may be somewhat wider than pace contact window 7 for the reasons discussed above. After that, use a hydrofluoric acid etching solution, for example,
Etching is performed using ammonium fluoride (NI (4F)). Then, by a well-known vacuum evaporation method, for example, platinum is deposited on the N-type semiconductor substrate 1 to a thickness of, for example, 300×,
500℃.

After 15 minutes of annealing, the platinum silicide ohmic
The contact layer is connected to the emitter contact window 6 and the paste layer.
A contact window 7 is formed on the ON type semiconductor substrate 1. Thereafter, as shown in FIG. 6, titanium, platinum, and gold are sequentially formed on the N-type semiconductor substrate 1 by vacuum evaporation, and the emitter electrode 1
0 and a pace electrode 1 are formed.

Conventionally, an emitter was placed around the emitter contact window 6.
The emitter-pace short-circuit point 12 shown in FIG. 3 was generated when the paste bonding area was exposed during the electrode forming process, but in the present invention (as shown in FIG. 6), the emitter-pace short circuit point 12 was generated.
An emitter region is formed directly under the O-shaped silicon nitride film 4, and even if metal is deposited directly under the canopy-shaped silicon nitride film 4 during the electrode formation process, emitter-base shorting will not occur. No spots occur, and device characteristics can be stabilized and device yields can be improved.

In addition, the examples are not limited to those described above, and the types of impurity ions for forming the pace region and the emitter region, the acceleration energy of ion implantation, the outsideness of the dose, and the first insulating film on the substrate surface and the first insulating film on the substrate surface. 2. The IM size and thickness of the insulating film and the electrode material are selected within the scope of the claims, and it goes without saying that the present invention can also be applied to integrated circuits and the like.

〔Effect of the invention〕

As described above, according to the present invention, the second insulating film on the first insulating film formed on the semi-2n substrate is formed thin, and impurity ions pass through the second insulating film. Then, by forming the emitter region so as to make the space region under the eave-like portion of the second insulating film of the emitter contact window conductive in the opposite manner, the second eave-like insulating film of the emitter contact window The emitter region is formed directly under the film, and even if metal is applied directly under the eave-shaped second insulating film during the electrode formation process, no emitter-base short circuit occurs, and the device characteristics are stabilized. Accordingly, it is possible to provide a method for manufacturing a semiconductor device that can improve the device yield υ.

[Brief explanation of drawings]

1 to 3 are cross-sectional views showing a conventional method of manufacturing a semiconductor device, and FIGS. 4 to 6 are cross-sectional views showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Nu half-core substrate, 2... P-type base region, 3
...Silicon oxide film (S102), 4...Silicon nitride film (81, N4), s...Photoresist film, 6
...Emi, contact window, 7...Pace contact window, 8...Arsenic ion (As''), 9...
N-type emitter region, 10... emitter electrode, 11...
・Pace electrode, 12... Emitter pace furnace m points.

Claims (1)

[Claims] A step of forming a first insulating film on a surface of a semiconductor substrate having a space region, a step of forming a second insulating film on this first insulating film, and a step of forming an opening window of this second insulating film. an emitter region having a structure in which the first insulating film is etched to the extent of side-etching using a mask, so that an end portion of the opening window of the second insulating film forms an eave-like shape with respect to the first insulating film; a step of opening a formation window on the pace region, and a step in which the first insulating film alone serves as a sufficient mask, but the second insulating film alone does not serve as a mask, and the pace region becomes of the opposite conductivity type. a step of implanting impurity ions into the semiconductor substrate to form an emitter region so that the space region directly under the eave-shaped portion of the second insulating film has an opposite conductivity type; The process of drilling a pace contact window in the semiconductor:! l
! : A method for manufacturing a semiconductor device, comprising the step of forming an emitter electrode and a pace electrode on a plate.