JPS6075167A - Synchronizing clock generator - Google Patents

Abstract

PURPOSE:To obtain a device attaining the accuracy of synchronism the same degree as the case with a higher clock frequency and realizing it inexpensively by using a clock having a same frequency but different phase. CONSTITUTION:Four kinds of clocks 22a-22d having the identical frequency and different phase shifted by 1/4 period each are fed to the output of a reference oscillator 23 generating a clock 22a having the same frequency as that of a picture signal rate clock through delay lines 24b-24d, the added result is inputted to D flip-flops 25a-25d and signals 29a-29d synchronously with an external signal 28 are fed to a clock selection circuit 26. Then the circuit 26 selects a clock (22a-22d) for a signal rising to the first among the synchronizing signals 29a- 29d and outputs it as the picture signal rate clock 31. Thus, the accuracy of synchronism improved to four times is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronized clock generation device that generates a clock synchronized with an external signal.

Conventional Structure and Problems Therein FIG. 1 is a perspective view showing a schematic structure of a scanning section of a laser printer or the like. In this figure, 1 is a semiconductor laser light source;
2 is a rotating polygon mirror that rotates at a constant speed, 3 is an imaging lens,
4 is a photosensitive drum. The semiconductor laser light source 1 outputs a laser beam 5 that is modulated according to both signals, which is swung in the axial direction of the photosensitive tram 4 by the rotating polygon mirror 2, and is directed onto the photosensitive drum 4 via the imaging lens 3. Even after the image is formed, an unmodulated laser beam is output from the semiconductor laser light source 1, and this is transmitted between the semiconductor laser light source 1 and the rotating polygon mirror 2.
In some cases, the light is modulated by an optical modulator provided between the two and then input to the rotating polygon mirror 2.

Now, the photosensitive drum 4 is scanned by the laser beam 6 that has passed through the imaging lens 3, and a latent image corresponding to the image 1t is recorded on its surface. To do this, it is necessary to synchronize the route of the photosensitive tram 4 with the image signal rate clock. It detects the routers 1 and 6 and outputs a position detection signal.Then, this position detection signal is converted into an image signal (ray) and clock to the same j, jlJ.

FIG. 2 is a block diagram of a conventional synchronized clock generation device that generates such a synchronized image signal rate clock. In this figure, a reference oscillator 11 generates a master clock 12 having a frequency that is an integral multiple of the image signal rate clock. The synchronization circuit 13 samples the position detection signal 14 using the master clock 12 as a sampling clock, and outputs a signal 16 for synchronizing the position detection signal 14 synchronized with the master clock 12. The frequency dividing circuit 16 outputs the image signal rate clock 17 by frequency dividing the master clock 12, or is reset by the synchronization signal 16 for each line. Therefore, the image signal rate clock 17 is synchronized with the position detection number Ia 14.

Now, in order to reduce the recording position deviation, it is necessary to improve the synchronization accuracy of the image (rate clock No. 6). However, in order to increase the frequency of the master clock 12, the reference oscillator 11, synchronization circuit 13, and frequency divider circuit 16 must be made faster, and these circuits There was a problem that it was expensive.
Reference oscillator 11, synchronization circuit 13 and frequency dividing circuit 1el
d: Using an ECL device etc., the speed can be considerably increased, but the frequency of the master clock 12 is restricted due to wiring between circuits, etc., so it is difficult to use a laser printer where the frequency of the image signal rate clock 17 is originally high. However, it is extremely difficult to improve the synchronization accuracy of the image signal rate clock 17 by further increasing the frequency of the master clock 120.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned problems of the conventional art, and is capable of achieving more synchronization J'l'1 degrees than ever before, and at a lower cost. 1. To provide a J1 clock creation device.
-1 target.

Structure of the Invention In the conventional device described above, (1, 1υ1 conversion I11.+1
The degree of external communication (position detection signal) is increased.
There is no other way than to increase the frequency of the lean-pulling clock, which may lead to the problems described above. The present invention focuses on this point, and by using a plurality of sampling clocks with the same frequency and different positions 1, it is possible to obtain the same effect as when the frequency of the sampling clock is increased. This is what we aim to achieve.

That is, the synchronized clock generation device according to the present invention includes means for generating a plurality of clocks having the same frequency and different phases, and a plurality of signal detection means for detecting a common external signal at the timing of the corresponding one of the clocks. and,
Characteristic 1.4 includes means for selecting and outputting the clock corresponding to the one signal detecting means that first detected the external signal among these signal detecting means.

Description of examples Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of a synchronized clock generation device according to an embodiment of the present invention. Although the apparatus of this embodiment will be described as a device for creating an image signal rate clock in the laser printer described above, it goes without saying that the application of the apparatus of this embodiment is not limited to this only.

In FIG. 3, reference numeral 21 denotes four types of clocks 22a with the same frequency and phases shifted by 1A period.

22b, 220.22d, this is a clock 221 with the same frequency as both signal rate clocks.
Base lf/′ that generates L; oscillator 23 and clock 22
Delay line 24.1L obtains clocks 22b-22d by delaying 1L. It is composed of b to 24d. Each of the clocks 22a to 22d is a D-flip clock 25.
It is an input terminal for the 027t''1 position detection signal 28 (external signal) applied to the clock input GK of the D flip-flops 262L to 26 (i) and input to the clock selection circuit 26. From the D flip-flop 25+L~2sd,
Synchronization signals 291-29d of the external signal 28 synchronized with the rising timing of the clocks 222L-22d
These signals are input manually to the clock selection circuit 26. This is an external output terminal for the image rate clock (synchronized chronograph) 31 output from the clock selection circuit 26. The clock selection circuit 26 selects the clock (one of 22a to 22d) corresponding to the one that rises first among the synchronization signals 29a to 29d, and outputs it as the image signal rate clock 31. FIG. 4 is a timing chart for explaining the operation of the device of this embodiment. When the external signal 28 is generated at the timing shown in this figure, the D flip-flop 25C to which the clock 220 is applied detects the external signal 28 earliest, so the synchronization signal 290 rises first. Therefore, in this case, the clock selection circuit 26
2c is selected as the image signal rate clock 31 (synchronization clock).

As is clear from the following explanation, according to the present embodiment, the external signal 28 and its earliest synchronization signals (29a to 29a)
Since the time delay in 29d) is less than a quarter of the clock period, the clock 22? Even if the frequency of L to 22d is the same as the master clock of the conventional device, four times the synchronization accuracy can be obtained. If the clock frequency is lowered to one quarter of the master clock frequency of the conventional device, the same synchronization accuracy can be obtained. It is clear that if the number of clocks is further increased, the synchronization accuracy can be further improved or the clock frequency can be further lowered, but in this embodiment, delay lines 24b, 240 .
False period from clock 22& using 24d, V2 period 1υ
19% Lap 1! Kuroyuri 22b delayed by 11 respectively
, 22C, 22(i), but the delay times of these delay lines are all equal to one clock period, and the clock 22b output from the delay line 24b is delayed by the IY extension line 24C to obtain the clock 22C. The delay line 24 (1) may be further extended to obtain the clock 22d.'1, another delay element may be used instead of the delay line.

Effects of the Invention As described above, the present invention has a configuration that achieves the same frequency disparity (equal ↓υ equivalent to the case where the -C1 clock frequency class is made higher using a mesh I cock). Therefore, it is possible to realize a synchronized clock generation device that has synchronization accuracy equal to or higher than conventional methods at a relatively low cost without using very high-speed devices, and it is also extremely difficult to realize it in the past due to the circuit amount and wiring etc. It is possible to achieve the effect of realizing a synchronized clock device with extremely high synchronization accuracy as previously described.

[Brief explanation of the drawings] Figure 1 is a schematic perspective view of the scanning unit of a laser printer, etc.;
The figure is a block diagram of a conventional synchronized clock generation device.
FIG. 4 is a block diagram of a synchronized clock generating device according to an embodiment of the present invention, and FIG. 4 is a timing diagram for explaining the operation of the device of the embodiment. 22a to 22d...Clock, 23...Reference oscillator, 24a to 24d=--Delay line, 25a
~25d...D flip-flop, 26...
. . . Clock selection circuit, 28 . . . Position detection signal (external signal), 31 . . . Image signal rate clock (synchronization clock).

Claims (1)

[Claims] means for generating a plurality of clocks having the same frequency and different phases; a plurality of signal detection means for detecting a common external signal at the timing of the corresponding one of the clocks; -4- Means for selecting and outputting the above-mentioned clock corresponding to one signal detecting means that has detected the distribution section signal.