JP3500243B2 - Image forming device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus such as a digital copying machine or a printer which forms a latent image on a photosensitive member by using a laser beam.

[0002]

2. Description of the Related Art A laser printer which drives a laser beam in accordance with a digital image signal to irradiate a photosensitive member to form a digital image, and an image forming apparatus such as a digital copying machine utilizing the same are known. . In such an apparatus, conventionally, a mechanism for scanning a single laser beam with a polygon mirror and irradiating the photosensitive member with the polygon mirror is used. Therefore, in order to speed up the operation, the rotation speed of the polygon mirror is set. It is necessary to increase the speed and increase the frequency of the video clock. However, since the polygon mirror is a mechanical component, high-precision processing technology and control technology are required to increase its rotation speed, which is difficult and causes a cost increase.
On the other hand, when the video clock frequency becomes excessively high, it is difficult to modulate the laser diode for generating the laser beam.

Therefore, in order to solve such a problem,
For example, Japanese Patent Application Laid-Open No. 57-8887 discloses a beam recording apparatus in which a plurality of laser beams are used and are simultaneously driven by a clock whose phase is adjusted by each synchronization detection signal. In this device, for example, when n beams are used, the video clock frequency is 1
/ N, the video clock frequency can be reduced, and conversely, if the frequency is the same, n times higher speed can be achieved. Moreover,
There is no need to increase the rotation speed of the polygon mirror.

[0004]

However, in the above-described method using a plurality of beams, the clock phase of each beam is synchronized by using the synchronization detection element of each beam, and thus the phase synchronization shift is lost. There is a problem in that the amount is sequentially added and increased and, for example, a drawn vertical line is bent. Therefore, it is an object of the present invention to provide an image forming apparatus capable of reproducing an image faithfully by reducing the shift amount of phase synchronization.

[0005]

An image forming apparatus according to claim 1, wherein a synchronization detecting element is provided corresponding to each of a plurality of laser beams, and image data of a plurality of lines are simultaneously recorded. And, by using a synchronization detection element provided corresponding to one beam, a phase synchronization means for synchronizing the phase of the video clock for the beam,
Positioning means for aligning the beam using the video clock phase-synchronized by the phase synchronization means, and the phase of the video clock phase-synchronized for the one beam to another beam. Other phase synchronization means for synchronizing using a correspondingly provided synchronization detecting element, and another phase alignment means for aligning the other beam using the video clock phase-synchronized by the other phase synchronization means The above-mentioned object is achieved by providing alignment means.

In this image forming apparatus, the video detection clock for one beam is phase-synchronized by using the synchronization detection element for one beam, and the beam is aligned by using the video clock that is phase-synchronized. Is done. on the other hand,
The video clock phase-synchronized with respect to the one beam is phase-synchronized with a synchronization detection element for another beam, and the position of the other beam is synchronized with the synchronized video clock. Matching is done.

According to a second aspect of the present invention, there is provided the image forming apparatus according to the first aspect.
In the image forming apparatus described above, a line memory for writing image data in units of main scanning lines is further provided for each beam, and a circuit for generating a dummy synchronization detection signal is provided, and the dummy synchronization detection signal is used. hand,
While the line data writing operation to each line memory is sequentially performed, the write reset and the read reset of each line memory are performed using the sync detection signal actually output from each sync detection element. It was done.

In this image forming apparatus, the writing operation of the line data to each line memory is sequentially performed by using the dummy sync detection signal, while the write reset and the read reset of each line memory are the sync detection elements. Is performed by using the synchronization detection signal actually output from the.

The image forming apparatus according to claim 3 is the image forming apparatus according to claim 2.
In the image forming apparatus described above, each line is further provided with means for dividing a write clock used for writing data to each line memory, and each line is provided with the clock divided by the dividing means. The image data is read from the memory. In this image forming apparatus, image data is read from each line memory using a clock created by dividing the write clock.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a diagram showing a horizontal arrangement of an optical system of an image forming apparatus according to an embodiment of the present invention. This optical system includes a laser diode unit (hereinafter referred to as an LD unit) 11 controlled by an LD control plate 10 and an LD unit 11
A collimator lens 12 for collimating a laser beam (hereinafter, simply referred to as a beam) emitted from the laser beam, a beam compressor 13 for vertically compressing the beam collimated by the collimator lens 12, and a high-speed rotation. Accordingly, the polygon mirror 14 that reflects the beam that has passed through the beam compressor 13 and scans the beam in the horizontal direction (main scanning direction) is provided.

Further, this optical system focuses the beam on the entire surface of the photoconductor 15 and the photoconductor 15 on which a latent image is formed by irradiation of the beam reflected by the polygon mirror 14. Fθ lens 1
6 and 17 and two sync detecting elements 18 and 19 arranged adjacent to the photoconductor 15. The two sync detecting elements are the sync detecting element 18,
They are arranged in the order of 19.

FIG. 2 shows the photosensitive member 1 from the polygon mirror 14.
It is a figure which simplifies and represents the state seen from the direction of arrow A of FIG. As shown in this figure, the two parallel beams reflected by the polygon mirror 14 enter the photoconductor 15 through the fθ lenses 16 and 17 while maintaining a space c in the vertical direction.

FIG. 3A shows the structure of the LD unit 11, and FIG. 3B shows the vertical arrangement of the optical system shown in FIG. In addition, in FIG. 3B, the polygon mirror 1
The reflection by 4 is omitted. As shown in FIG. 3A, the LD unit 11 includes a substrate 11a, and two LDs 11b-1 and 11b- arranged on the substrate 11a.
2 and. The horizontal distance between the LD 11b-1 and the LD 11b-2 is set to h, and the vertical distance is set to v. The LD unit 11 is arranged in the vertical direction as shown in FIG.

LD 11b-1, LD of the LD unit 11
The beams emitted from 11b-2 pass through the collimator lens 12, the beam compressor 13, and the fθ lenses 16 and 17, respectively so that they overlap each other in the vertical direction, and the synchronization detection elements 18 and 19 are arranged so as to be displaced in the vertical direction. Incident on each. Here, the beam compressor 13
Since the beams are focused only in the vertical direction (sub-scanning direction), the vertical spacing c between the two beams 21 and 22 shown in FIGS. 2 and 3B is as shown in FIG. It is much smaller than the vertical distance v between the LD 11b-1 and the LD 11b-2 shown in a).

FIG. 4 is a diagram showing a configuration of a synchronization detection circuit including the synchronization detection element 18. In this circuit, a synchronous detection element 18 including a photodiode whose cathode end is connected to a power supply, a resistor 18a whose one end is connected to the anode end of the synchronization detection element 18 and whose other end is grounded, and one input end are synchronized. Comparator 1 connected to the anode terminal of the sensing element 18 and adapted to apply the reference voltage Vref to the other input terminal
8b and. The synchronization detection element 18 is the LD 11b-
When the beam 21 from 1 is received, the current I flows through the resistor 18a, and the voltage V1 (= IR) is input to one input terminal of R. When V1 exceeds the reference voltage Vref, the positive synchronization detection pulse DETP1 is output from the output terminal of the comparator 18b. The synchronization detecting element 18 is not limited to the photodiode and may be another photoelectric conversion element. The same applies to the configuration and operation of the synchronization detection circuit including the other synchronization detection element 19,
A positive synchronization detection pulse DETP2 is output in response to the incidence of the beam 22 on the synchronization detection element 19.

FIG. 5 is a diagram showing a main configuration of a control circuit of this image forming apparatus. This circuit includes a CCD (charge coupled device) 50 for reading document information and an image processing gate array (IPU) 6 connected to the output end of the CCD 50.
0, a video processing gate array (GAVD) 70 connected to the IPU 60, two fifo memories (FIFOs) 71 and 72 and a data division / synchronization control unit 100 connected to the GAVD 70, and a data division / synchronization control unit. 1
Two LD control units 10-1, 10-2 connected to 00
And two fifo memories (FIFO) 101, 1
02 and.

From the IPU 60 to the SDA for the GAVD 70
In addition to TA and SCLK being input, the synchronization detection pulse DETP1 and the video clock VCLK are input. The FIFOs 71 and 72 are first-in first-out memories for timing adjustment provided because the reading and writing pixel frequencies are different.

The data division / synchronization control unit 100 is, for example, an ASIC (Application Specific).
IC) and receives the video data VDATA and the video clock VCLK from the GAVD 70, and the sync detection pulses DETP1 and DETP from the sync detection circuits including the sync detection elements 18 and 19, respectively.
2 is input, and control or the like for phase synchronization is performed based on these. Then, the data division / synchronization control unit 100 sends the video data VDATA to the LD control unit 10-1 that drives and controls the LD 11b-1 (FIG. 3).
1 and the video clock VCLK1 are output, and the video data VDATA2 and the video clock VCLK2 are output to the LD control unit 10-2 that drives and controls the LD 11b-2 (FIG. 3).

FIG. 6 shows a functional block of the data division / synchronization control unit 100 composed of an ASIC.
As shown in this figure, the data division / synchronization control unit 100
Has various functions such as write / read control for the FIFOs 101 and 102, phase control, clock division, generation of a dummy synchronization signal, generation of a signal LCLR, and the like. The FIFOs 101 and 102 are first-in first-out memories used for converting 1-beam data input from the GAVD 70 into 2-beam data.

FIG. 7 is a diagram specifically showing the main circuit of the data division / synchronization control unit 100 shown in FIG. 6 including the FIFOs 101 and 102. This circuit includes a JK flip-flop 103, FIFOs 101 and 102, two phase synchronization circuits 104 and 105, two frequency dividing circuits 106,
And 107. Both J and K terminals of JK flip-flop 103 are connected to the power supply (fixed to "H" level)
A signal LCLR described later is input to the clock terminal, and the sub-scanning image area effective signal FGAT is input to the gate terminal.
The E signal is input.

Output terminal Q of the JK flip-flop 103
Are branched into two, one of which is inverted and connected to the write enable terminal WE of the FIFO 101, and the other is connected to the write enable terminal WE of the FIFO 102 as it is.

Video data VDATA is input from the GAVD 70 (FIG. 5) to the write data terminals WDATA of the FIFOs 101 and 102, and the write reset terminals W are input.
The sync detection pulse DETP1 from the sync detection circuit (for the beam 21) (FIG. 4) including the sync detection element 18 is input to RES, and the write clock terminal WCK receives the video clock from the GAVD 70. VCLK is input.

The read reset terminal RRES of the FIFO 101 is supplied with the synchronization detection pulse DETP1 from the synchronization detection circuit of FIG. 4, and the read reset terminal RRES of the FIFO 102 is configured to include the synchronization detection element 19 (beam. The sync detection pulse DETP2 is input from the sync detection circuit (for 22). Further, read enable signals RE1 and R, which will be described later, are applied to the read enable terminals RE of the FIFOs 101 and 102, respectively.
E2 is input respectively. On the other hand, F
Each read data terminal RDATA of IFO 101, 102
From video data VDATA1 and VDAT respectively
A2 is output and supplied to the LD control units 10-1 and 10-2.

The phase synchronization circuit 104 has a synchronization detection pulse D
The ETP1 is input, and the synchronization detection pulse DETP2 is input to the phase synchronization circuit 105. The phase synchronization circuit 104 receives the input video clock signal VC
The phase of LK is synchronized with the synchronization detection pulse DETP1 and the video clock signal VCLKA is output. The video clock signal VCLKA is input to the frequency dividing circuit 106 and the phase synchronizing circuit 105. On the other hand, the phase synchronization circuit 105 receives the input video clock signal V
The phase of CLKA is synchronized with the synchronization detection pulse DETP2, and the video clock signal VCLKB is output. The video clock signal VCLKB is input to the frequency dividing circuit 107.

The output signal of the frequency dividing circuit 106 is the FIFO1.
01 is supplied to the read clock terminal RCLK and is also supplied to the LD control unit 10-1 as the video clock VCLK1. On the other hand, the frequency dividing circuit 10
The output signal of 7 is input to the read clock terminal RCLK of the FIFO 102 and is also supplied to the LD control unit 10-2 as the video clock VCLK2.

FIG. 8 is a diagram showing a circuit configuration for generating the write enable signals RE1 and RE2 shown in FIG. This write enable signal generation circuit 110 has 2
One counter 111, 112 and two comparators 1
13 and 114 are provided. The counter 111 receives the video clock signal VCLK1 output from the divider circuit 106 (FIG. 7), and the counter 112 receives the video clock signal VCLK output from the divider circuit 107 (FIG. 7).
CLK2 is input. The output terminal Q of the counter 111 is connected to the input terminal A of the comparator 113, and the output terminal Q of the counter 112 is the input terminal A of the comparator 114.
It is connected to the.

A predetermined set value 1 is input to the other input terminal B of the comparator 113, and a predetermined set value 2 is input to the other input terminal B of the comparator 114. The synchronous detection pulse DETP1 is input to the reset terminals of the counter 111 and the comparator 113, and the counter 112
The synchronization detection pulse DETP2 is input to each reset terminal of the comparator 114. Then, the comparators 113 and 114 compare the count values output from the counters 111 and 112 with the set values 1 and 2, and output the write enable signals RE1 and RE2 according to the comparison result. It has become.

FIG. 9 is a diagram showing a circuit configuration for generating the signal LCLR. This circuit is a counter 121
, The comparator 122, and the one-shot generation circuit 12
3, an OR gate 124, flip-flops 125 to 127 connected in series in three stages, an inverter 128,
AND gate 129. VCLK is input to the counter 121, and the count value is output from the output terminal Q. The count value from the counter 121 and a predetermined set value are input to the comparator 122, and the two are compared. The output end of the comparator 122 is connected to the one-shot generation circuit 123, and the output end of the one-shot generation circuit 123 is connected to one input end of the OR gate 124.

The synchronization detection pulse DETP1 is input to the other input terminal of the OR gate 124. OR gate 124
Is connected to the input terminal D of the first flip-flop 125 among the three-stage flip-flops.
VCLK is input to the clock terminals of these flip-flops 125 to 127. Flip-flop 127
The output terminal Q of is connected to one input end of the AND gate 129 via the inverter 128. The other input end of the AND gate 129 is connected to the output terminal Q of the flip-flop 125. And AND gate 12
The signal LCLR is output from the output terminal of the terminal 9.

With this circuit, the one-shot generation circuit 123
Outputs a dummy synchronization detection pulse DETP1. The OR gate 124 takes an OR from the real synchronization detection pulse DETP1 to form a pulse signal DETP1A. The dummy synchronization detection pulse DETP1 is the VC generated by the counter 121.
The pulse signal has a predetermined pulse width and is output when the count value of LK becomes equal to the set value.

Next, the operation of the image forming apparatus having the above configuration will be described with reference to FIG. The circuit of FIG. 9 has a real sync detection pulse DETP1 and a dummy sync detection pulse DTP.
Pulse signal DETP1 superimposed (mixed) with ETP1
A (FIG. 10A) and a signal LCLR (FIG. 10B) are generated. As shown in this figure, the signal LCLR is
The pulse signal DETP1A is a signal that becomes "H" level for two clocks during the "H" level period, and causes the JK flip-flop 103 to toggle, as described later.

In FIG. 7, FIFOs 101 and 102 are provided.
Are both write-reset (write-address reset) by the genuine synchronization detection pulse DETP1 (FIG. 10D) input to WRES, and the video data VDATA is written in synchronization with VCLK. As a result, one line of video data from the GAVD70 is FI
Two lines are formed by the FOs 101 and 102. Also,
The FIFO 101 is read reset (reset of read address) by the real sync detection pulse DETP1 (FIG. 10 (g)), and the FIFO 102 is sync detection pulse D.
Read reset is performed by ETP2 (FIG. 10 (h)).

The JK flip-flop 103 outputs the signal LC
The output is toggled according to LR. And J
When the output terminal Q of the K flip-flop 103 is at “L” level, the write enable terminal WE of the FIFO 101
Goes to the "H" level to enter the write enable state (FIG. 10 (e)), and the WE of the FIFO 102 goes to the "L" level to enter the write disable state ((f) in the figure). When the output terminal Q of the JK flip-flop 103 is at "H" level, the opposite, that is, the FIFO 10
1 becomes the write disable state, and the FIFO 10
2 is in the write enable state.

In FIG. 8, the counter 111 has VCLK.
When 1 is counted and the count value becomes equal to the set value 1, the reset signal RE1 (FIG. 10 (i)) is set to "H" level. As a result, the FIFO 101 enters the read enable state. Similarly, counter 112 has VCLK
2 is counted, and when the count value becomes equal to the set value 2, the reset signal RE2 (FIG. 10 (j)) is set to "H" level. As a result, the FIFO 102 enters the read enable state.

The phase synchronization circuit 104 synchronizes the phase of the video clock signal VCLK with the synchronization detection pulse DETP1 and outputs the video clock signal VCLKA. The video clock signal VCLKA is frequency-divided by the frequency dividing circuit 106, and LD11b− is used as the video clock VCLK1.
Is supplied to the LD control unit 10-1 for 1
It is input to the RCLK of the FO 101 and serves as its read clock. On the other hand, the phase synchronization circuit 105 is
The phase of the video clock VCLKA generated in 4 is further synchronized with the synchronization detection pulse DETP2, and the video clock VCLKB is output.

This video clock VCLKB is frequency-divided by the frequency dividing circuit 107, and L is used as the video clock VCLK2.
It is supplied to the LD control unit 10-2 for the D11b-2 and is also input to the RCLK of the FIFO 102 to serve as its read clock. Since the video data VDATA from the GAVD 70 is made into two lines by the FIFOs 101 and 102 and two beams (beams 21 and 22) are simultaneously driven, the video clocks VCLK1 and VCLK2 for reading the video data from the FIFOs 101 and 102 are
In both cases, the original video clock VCLK may be divided in half.

As shown in FIGS. 10 (i) and 10 (j), F
By adjusting the interval d between the rising timing of the read enable signal RE1 for the IFO 101 and the rising timing of the read enable signal RE2 for the FIFO 102, the main scanning misalignment between the beam 21 and the beam 22 is eliminated. be able to.

Next, the phase synchronization method will be specifically described. FIG. 11 is a diagram showing a specific circuit configuration of the phase synchronization circuit 104. The phase synchronization circuit 104 inputs delay signals 141 and 142 for delaying the original video clock VCLK (t1) sequentially by 1/8 phase thereof and outputting seven delay signals t2 to t8, and input terminals A1 to A8. Latched the generated signals t1 to t8 with the synchronization detection pulse DETP1,
Output terminals Q1 to Q8 and their inverted output terminals XQ1 to X
Flip-flops 143 and 144 output from Q8,
Eight 3-input NAND gates 145-1 to 145-8
And an 8-input NOR gate 146. The first input terminals of the NAND gates 145-1 to 145-8 are connected to the output terminals Q1 to Q8 of the flip-flops 143 and 144, respectively, and the second input terminals are connected to the flip-flop 1 respectively.
Inversion output terminals XQ2, XQ3, ... XQ of 43, 144
1 is connected to each. The signal t is applied to each third input terminal.
1 to t8 are input respectively.

Each input terminal of the NOR gate 146 is connected to each output terminal of the NAND gates 145-1 to 145-8. Synchronous clock VC is output from the output end of NOR gate 146.
LKA is output. The phase-locked circuit 105 has a similar circuit configuration, but in this circuit, VCLKA is input as the original video clock, DETP2 is input as the synchronization detection pulse, and VCLKB is input as the phase-locked clock. Is output.

FIG. 12 is a timing chart showing the operation of the phase locked loop circuit 104 shown in FIG. As shown in this figure, the phase-locked loop 104 has delay signals t2 to t8 (FIG. 11 (b)) whose phases are delayed by 1/8 with respect to the original input clock t1 (FIG. 11 (a)). (H)) is the delay element 1
41, 142 which have the closest phase to the synchronization detection pulse DETP1 ((i) in the figure) among the eight t1 to t8 are output as the synchronization clock VCLKA ((j) in the figure). In this figure, t2 is selected and output. The phase synchronization accuracy in this case is 1/8 dot.

Next, the effect of the 2-beam video clock synchronization system according to the present embodiment will be described in comparison with the conventional system. FIG. 13 is a circuit in which a main part of the data division / synchronization control unit 100 in FIG. 5 is configured by a conventional method and corresponds to the circuit in FIG. 7 in the present embodiment. Note that, in this figure, the same components as those in FIG. In this circuit, the phase detection circuit 104 synchronizes the synchronization detection pulse DETP1 with the original video clock signal VCLK, whereby the synchronized clock is divided to divide the video clock signal VCL.
The point to be K1 is the same as in FIG.
5, the synchronization detection pulse DETP2 is synchronized with the original video clock signal VCLK, and the synchronized clock is divided to generate the video clock signal VCLK2 '. That is, in this circuit, either of the two phase-locked circuits 104 and 105 is synchronized based on the original video clock signal VCLK. In this case, for example, the phase synchronization circuit 104,
Assuming that the phase synchronization accuracy of 105 is ⅛ dot, as shown in FIG.
A maximum of 1/4 dot (1/8 + 1/8 dot) is provided between K1 ((b) in the figure) and VCLK2 '((c) in the figure).
Deviation will occur.

On the other hand, in the circuit configuration of FIG. 7 according to the present embodiment, the synchronization detection pulse is generated by using the clock signal VCLKA generated by synchronizing the video clock signal VCLK with the synchronization detection pulse DETP1. DET
Since the phase of P2 is synchronized, as shown in FIG. 15, the video clock signal VCLK1 ((a) in the same figure).
Between VCLK2 and VCLK2 ((b) and (c) in the figure), only a maximum deviation of 1/8 dot occurs. In the present embodiment, the case where two lines of image data are simultaneously recorded by using two laser beams has been described, but the present invention is not limited to this, and when three or more beams are used. Of course, can also be applied.

[0043]

As described above, according to the image forming apparatus of the first aspect, the phase synchronization of the video clock for one beam is achieved by using the synchronization detecting element for one beam.
The beam is aligned using the phase-locked video clock, while the phase-synchronized video clock for the one beam is phase-synchronized using the synchronization detection element for another beam. Since the positions of the other beams are adjusted by using the synchronized video clock, it is possible to reduce the positional deviation amount of each of the plurality of beams in the main scanning direction.

Particularly, according to the image forming apparatus of the second aspect, the writing operation of the line data to each line memory is sequentially performed using the dummy synchronization detection signal, while the writing reset and the reading of each line memory are performed. Since the resetting is performed by using the sync detection signal actually output from each sync detecting element, the circuit can be realized with a simple configuration. According to the image forming apparatus of claim 3,
Since the image data is read from each line memory by using the clock generated by dividing the write clock, the circuit can be realized with a simple configuration.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an optical system of an image forming apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a simplified optical path from the polygon mirror in FIG. 1 to a photoconductor.

3A is a diagram showing a configuration of an LD unit, and FIG. 3B is a diagram showing a vertical arrangement of the optical system of FIG.

FIG. 4 is a circuit diagram showing a configuration of a synchronization detection circuit.

FIG. 5 is a circuit diagram showing a main part of a control circuit of the image forming apparatus.

FIG. 6 is a diagram showing functional blocks of a data division / synchronization control unit.

FIG. 7 is a circuit diagram specifically showing a main circuit of the data division / synchronization control unit of FIG.

FIG. 8 is a circuit diagram illustrating a configuration of a circuit that generates a write enable signal in FIG.

FIG. 9 is a circuit diagram illustrating a configuration of a circuit that generates a signal LCLR.

10 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 11 is a circuit diagram showing a specific circuit configuration of a phase locked loop circuit.

12 is a timing diagram illustrating an operation of the phase locked loop circuit of FIG.

13 is a circuit diagram in the case where a main part of the data division / synchronization control unit in FIG. 5 is configured by a conventional method.

FIG. 14 is a timing diagram showing the amount of deviation between two video clock signals in the circuit of FIG.

FIG. 15 is a timing diagram showing the amount of deviation between two video clock signals in the circuit of FIG. 7.

[Explanation of symbols]

10 (10-1, 10-2) LD control unit 11 LD unit 11b-1, 11b-2 Laser diode 14 Polygon mirror 15 Photosensitive member 18, 19 Synchronous detection element 21, 22 Laser beam 50 CCD 60 IPU 70 GAVD 100 Data Division / synchronization control unit 101, 102 FIFO 103 JK flip-flop 104, 105 Phase synchronization circuit 106, 107 Frequency divider circuit 110 Write enable signal generation circuit DETP1, DETP2 Sync detection pulse VCLK, VCLK1, VCLK2 Video clock signal

Claims (3)

(57) [Claims] 1. An image forming apparatus in which a synchronization detecting element is provided corresponding to each of a plurality of laser beams, and image data of a plurality of lines are simultaneously recorded, and the image forming apparatus is provided corresponding to one beam. Phase synchronization means for synchronizing the phase of the video clock for the beam using the synchronization detection element, and alignment means for aligning the beam using the video clock phase-synchronized by the phase synchronization means. Another phase synchronization means for synchronizing the phase of the video clock phase-synchronized with respect to the one beam using a synchronization detection element provided corresponding to another beam, and the other phase synchronization means An image including: another alignment means for aligning the other beam using a video clock phase-synchronized by Forming apparatus. 2. A line memory for writing image data in units of main scanning lines is provided for each beam, and a circuit for generating a dummy synchronization detection signal is provided, and using the dummy synchronization detection signal, While sequentially performing the write operation of the line data to each of the line memories, the write detection and the read reset of each line memory are performed by using the synchronization detection signal actually output from each of the synchronization detection elements. The image forming apparatus according to claim 1, wherein the image forming apparatus comprises: 3. Further, each beam is provided with means for dividing a write clock used for writing data to each of the line memories, and each line memory is supplied with the clock divided by the dividing means. The image forming apparatus according to claim 2, wherein the image data is read.