JP3500271B2 - Multi-beam image forming device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-beam image forming apparatus for writing images substantially simultaneously by using a plurality of beams, and more particularly, image data for a plurality of lines sequentially written in each of a plurality of line memories. The present invention relates to control when reading out data at substantially the same time.

[0002]

2. Description of the Related Art Generally, when an attempt is made to increase the speed of a copying machine or printer, the frequency of the video clock becomes high and there is no available IC or LD (laser diode) driver. A method has been proposed in which different images are assigned to a plurality of writing beams to perform optical modulation as shown in FIG. According to this method, when writing n lines simultaneously using n LDs, the frequency of the video clock can be reduced to 1 / n.

For example, when two LDs are used, two line memories are toggled to sequentially write image data of two lines line by line with a write clock, and the image data of each line written in this two line memory is written. , And can be applied to each of the two LDs by reading at substantially the same time with a read clock having a frequency half that of the write clock.

A conventional example of this type is, for example, Japanese Patent Laid-Open No. 57-57.
As disclosed in Japanese Patent Laid-Open No. 8887, there is proposed a method of reading with a read clock that is phase-matched by individual synchronization detection signals that detect a plurality of beams. According to this method, for example, even if the two light emitting elements are arranged with being shifted in the main scanning direction, emission of the beam modulated according to each image data is started according to each arrangement position.

[0005]

By the way, a phase synchronization circuit for generating a read clock by performing phase adjustment according to individual synchronization detection signals that detect a plurality of beams is normally used for phase adjustment in units of 1 / m dot. To do. Therefore, according to the conventional method, in the case of the two-beam method, the phase of the read clock for the first beam is advanced by 1 / m dot and the phase of the read clock for the second beam is delayed by 1 / m dot by the phase matching circuit. Then, the shift amount due to the phase adjustment is added to generate a phase difference of 2 / m dots, which causes an abnormal image such as a vertical line image being bent.

Further, when two LDs are used, depending on the interval in the main scanning direction, if there is no margin in the setup time and hold time of the read clock and the read reset signal of the line memory of the second beam, an abnormal image is generated. Occurs. Furthermore, if the write reset and read reset of the line memory are performed using a counter and a register, the circuit configuration becomes complicated.

In view of the above-mentioned conventional problems, the present invention has a structure in which a plurality of light emitting elements are arranged shifted in the main scanning direction, and the emission of a beam modulated according to each image data is started according to each arrangement position. It is an object of the present invention to provide a multi-beam image forming apparatus capable of realizing a high-quality image by reducing the shift amount of the phase difference of the read clock of each line memory.

[0008]

In order to achieve the above object, the first means is arranged so as to be displaced in the main scanning direction, and the emission of a beam modulated in accordance with each image data is emitted in accordance with each arrangement position. Starting n light emitting elements, n line memories for respectively storing image data for the n light emitting elements, and each beam emitted by the n light emitting elements is received and a synchronization detection signal is output. A first synchronization detecting element and a first light emitting element of the n light emitting elements emit the first light emitting element to perform phase synchronization of clocks based on a synchronization detection signal of a first beam detected by the first synchronization detecting element. A phase synchronization circuit, a first delay circuit for delaying the synchronization detection signal of the first beam by a scanning time interval in the main scanning direction by the light emitting element, and a first beam delayed by the first delay circuit. Sync detection signal N-1 phase-locked circuits that perform phase-locking of the clocks that are phase-locked by the first phase-locked loop circuit, and delay each clock that is phase-locked by the n-1 phase-locked circuits. N-1 second delay circuits for generating clocks for other beams, and the first
And a frequency dividing circuit for dividing the clocks generated by the second delay circuit into 1 / n to generate read clocks for the n line memories. Is characterized by.

A second means is an n for another light emitting element based on the synchronization detection signal of the first beam in the first means.
Generate one dummy sync detection signal, and
Write reset of the line memories is performed by the synchronization detection signal of the first beam, and writing of the n line memories is toggled based on the synchronization detection signal of the first beam and the n-1 dummy synchronization detection signals. It is characterized by operating.

A third means is characterized in that, in the first and second means, the phase synchronization circuit performs phase synchronization of write clocks of the n line memories.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of a multi-beam image forming apparatus according to the present invention, FIG. 2 is an explanatory diagram showing arrangement positions of two laser diodes in FIG. 1, and FIG.
4 is an explanatory view showing scanning positions of two laser beams in the sub-scanning direction in the multi-beam image forming apparatus of FIG. 1, and FIG. 4 shows scanning positions of two laser beams in the main-scanning direction in the multi-beam image forming apparatus of FIG. 5 is a circuit diagram showing a synchronization detection circuit of the multi-beam image forming apparatus of FIG. 1, FIG. 6 is an explanatory diagram showing a synchronization detection signal detected by the synchronization detection circuit of FIG. 5, and FIG. FIG. 8 is a block diagram showing a schematic configuration of a multi-beam image forming apparatus of FIG.
FIG. 9 is a block diagram showing the configuration of the SIC in detail, FIG. 9 is a block diagram showing the dummy synchronization detection signal generating circuit of FIG. 8 in detail, and FIG. 10 is a timing chart showing the main signals of the ASIC of FIG.

FIG. 11 is a block diagram showing the LCLR generation circuit of FIG. 8 in detail, FIG. 12 is a timing chart showing the LCLR signal of FIG. 11, and FIG. 13 is a detail of the read enable signal delay circuit in the ASIC of FIG. FIG. 14 is a block diagram showing in detail a main circuit in the ASIC of FIG. 8, FIG. 15 is a block diagram showing in detail an example of the phase locked loop circuit of FIG. 14, and FIG. 16 is a block diagram of the phase locked loop circuit of FIG. It is a timing chart which shows a main signal.

1 to 4, an LD unit 2 is mounted on an LD control plate 1, and two LD1 and LD2 are mounted on the LD unit 2 as an example. Note that L
Even if the number of D is 3 or more, the basic idea is the same. The laser beams emitted from LD1 and LD2 are
The beams are collimated by the common collimator lens 3, and then the beam compressor 4 focuses only the sub-scanning direction of the beam on the reflecting surface of the polygon scanner 5. The polygon scanner 5 rotates in the main scanning direction indicated by the arrow, whereby the laser beam is deflected in the main scanning direction at a constant angular velocity. This beam is corrected by the fθ lens 6 so as to be deflected at a constant velocity, and then is irradiated onto the photoconductor 7 and detected by the synchronization detection element 8. The photoconductor 7 rotates in the sub scanning direction.

Two LD1 and LD2 on the LD unit 2
2 are arranged at a distance a in the main scanning direction and at a distance b in the sub scanning direction. The two beams emitted from the LD1 and LD2 and reflected by the polygon scanner 5 as shown in FIG. 3 are separated by a distance C in the sub-scanning direction because the beam compressor 4 condenses only in the sub-scanning direction. Further, the distance C becomes a value much smaller than the distance b.

Further, as shown in FIG. 4, the two beams emitted from the LD1 and LD2 are received by the synchronization detection element 8 after being shifted by the distance a in the main scanning direction between the LD1 and LD2. As shown in FIG. 5, the synchronization detecting element 8 has a photodiode (PD) 9 as an example. When the PD 9 receives a beam, a current I flows, and when V1 (= IR) exceeds a reference voltage Vref, a comparator 10 is provided. Outputs a positive pulse sync detection signal DETP. In this case, as shown in FIG. 6, a synchronization detection signal DETP1 when the first beam of LD1 is detected and a synchronization detection signal DETP2 when the second beam of LD2 is detected are generated in one cycle, and the synchronization detection signal DETP2 is generated. The synchronization detection signal DETP2 lags behind the signal DETP1.

AS (application specific) IC 14 shown in FIG.
Constitutes the multi-beam image forming apparatus of the present invention.
In FIG. 7, the writing speed is half the reading speed, and the CCD 11 reads the original image and outputs the image signal to the IPU (image processing gate array) 12. I
The PU 12 outputs the image data SDATA and the clock signal SCLK to the GAVD (video processing gate array) 13 based on the image signal from the CCD 11.

The GAVD 13 is based on the signals SDATA and SCLK from the IPU 12, the first beam synchronization detection signal DETP1 and the image clock VCLK, which will be described later, and uses the FIFO memories 16 and 17 to output the image data VDATA and the clock. Signal VCLK to ASIC1
Output to 4. Here, the FIFO memories 16 and 17 are
Since the pixel frequency is different between reading and writing, the timing is adjusted. In the present embodiment, the first
The real sync detection signal of the beam (hereinafter, real sync detection signal) DETP1, the dummy sync detection signal (hereinafter, dummy sync detection signal) DETP1 'generated based on the real sync detection signal DETP1, and the second beam The synchronization detection signal DETP2 is used.

The ASIC 14 receives the signals VDATA and VCLK from the GAVD 13 and the real sync detection signal DETP.
Based on the first and second beam synchronization detection signals DETP2 and using the FIFO memories 18 and 19, the clock signal V
Image data VDAT for LD1 at 1/2 speed of CLK
A1 and its clock signal VCLK1 are generated to generate the first L
The image data VDA for the LD2, which is output to the D control unit 15a and also has a speed half that of the clock signal VCLK.
Second by generating TA2 and its clock signal VCLK2
It is output to the LD control unit 15b. FIFO memory 18, 1
Reference numeral 9 designates one beam data VDATA from the GAVD 13 as two beam data VDATA1 and VDATA as described later.
Used to convert to 2.

The ASIC 14, as shown in detail in FIG.
Write / read processing unit of the FIFO memories 18 and 19/1
It has a beam → two-beam converter 21, a dummy sync signal generator / LCLR generator 22, a phase lock circuit 23, and a clock divider 24. In the dummy sync signal generator (22), as shown in FIG. 9, the counter 31 counts the pixel clock VCLK, and then the comparator 32 counts the counter 31 and the real sync detection signal DET.
The set value corresponding to 1/2 of one cycle of P1 is compared. Then, the one-shot generation circuit 33 causes the comparator 3
When the comparison results of 2 match, a dummy synchronization detection signal DEPT1 'having a predetermined pulse width is generated, and then the OR gate 34 causes the dummy synchronization detection signal DEPT1' to be generated, as shown in FIG.
1'and the logical sum signal DET of the genuine synchronization detection signal DETP1
Output P1A.

The LCLR generator (22) has D flip-flops 35, 36, 37, an inverter 38 and an AND gate 39 as shown in FIG.
As shown in FIG. 2, a signal LCLR that goes high for two pixel clock periods is generated while the signal DETP1A goes high.

FIG. 13 shows a circuit for generating the read enable signal RE in the ASIC 14. Counter 10
Reference numerals 1 and 102 are cleared by the real sync detection signal DETP1 and the second beam sync detection signal DETP2, respectively, and count the pixel clocks VCLK1 and VCLK2. Comparators 103 and 104 are counters 101 and
Each count value of 102 is compared with each set value corresponding to the distance a of the LD1 and LD2 in the main scanning direction, and when they match, the reading of the FIFO memories 18 and 19 deviated by the time d as shown in FIG. It outputs enable signals RE1 and RE2.

FIG. 14 shows a write / read processing unit / one-beam → two-beam conversion unit 21 of the FIFO memories 18 and 19.
The phase synchronization circuit 23 and the clock frequency divider 24 are shown.
The phase synchronization circuit 23 includes two systems of phase synchronization circuits 23a and 23a.
b, and the clock frequency division section 24 also has frequency division circuits 24a and 24b of two systems.

The phase synchronization circuit 23a is a pixel clock VCL in which the pixel clock (= line memory write clock) VCLK is phase-synchronized by the synchronization detection signal DETP1.
The KA is output to the frequency dividing circuit 24a and the phase synchronizing circuit 23b. The synchronization detection signal DETP1 is delayed by the delay circuit 110 by the scanning time interval in the main scanning direction by the LD1 and LD2.
Is delayed by the phase synchronization circuit 23b.
The pixel clock VCLKA from 3a is supplied to the delay circuit 3
The delay circuit 11 delays the pixel clock VCLKB phase-synchronized by the synchronization detection signal DETP1a delayed by 0.
Output to 1.

The delay circuit 111 uses the pixel clock VCL
The pixel clock VCLKB1 obtained by delaying KB is divided by the frequency dividing circuit 2
4b, and the frequency dividing circuits 24a and 24b divide the pixel clocks VCLKA and VCLKB1 into halves to generate clocks VCLK1 and VCLK2, respectively.
It is applied as the read clock RCLK of the FO memories 18 and 19.

Here, the phase synchronization circuits 23a and 23b are connected to the input clock VCL as shown in FIGS. 15 and 16, for example.
The pixel clock VCL is generated by shifting K by 1/8 cycle to generate eight types of clock signals and selecting the clock signal having the closest phase to the synchronization detection signals DETP1 and DETP2.
It is possible to output KA and VCLKB. In this example, the phase synchronization accuracy is 1/8 dot.

As shown in FIGS. 14 and 10, FI
The FO memories 18 and 19 are both genuine synchronization detection signals DET.
Write reset (line address reset) by P1
(WRES shown). As other input signals, the pixel clock VCLK and the image data VDATA from the GAVD 13 are applied as the write data WDATA, and the Q signal of the FF 25 is applied as the write enable signal WE.

The FF 25 and the inverter 26 are used to toggle the write enable signal WE of the FIFO memories 18 and 19, and the sub-scanning image area effective signal FG.
Reset by ATE. The FF 25 is reset by the first real sync detection signal DETP1 after the start of the image effective area, and at this time, the write enable signal WE of the FIFO memory 18 becomes high. Further, the FF 25 toggles the outputs Q and / Q by the signal LCLR,
The write enable signal WE of the memories 18 and 19 is the signal L
Alternately high due to CLR.

FIG. 17 shows a conventional example, in which the delay circuits 110 and 111 are not provided as compared with FIG.
The second phase synchronization circuit 23b synchronizes the pixel clock VCLK with the second beam synchronization detection signal DETP2. With such a configuration, the phase of the pixel clock VCLKA of the LD1 is 1/0 by the phase synchronization circuit 23a.
LD2 pixel clock VCLKB along with 8 dots
When the phase is delayed by ⅛ dot by the phase synchronizing circuit 23b, the shift amount due to the phase adjustment is added as shown in FIG. 18, and the read clocks VCLK1 and VCLK2 generated by being divided by the frequency dividing circuits 24a and 24b are added. 1 in between
A phase difference of / 4 dots occurs.

On the other hand, in the configuration shown in FIG. 14, the phase synchronizing circuit 23b delays the pixel clock VCLKA from the phase synchronizing circuit 23a by the delay circuit 110 by the scanning time interval in the main scanning direction by the LD1 and LD2. Pixel clock VCLKB that is phase-synchronized with the synchronization detection signal DETP1 and is further delayed by the delay circuit 111.
Since B1 is output, the shift amount due to the phase adjustment is not added as shown in FIG. 19, and the read clock VCLK1,
There is a phase difference of 1/8 dot between VCLK2.

[0030]

As described above, according to the first aspect of the invention, the read clock of the line memory for the first beam is frequency-synchronized and frequency-divided based on the synchronization detection signal of the first beam. At the same time, for the read clocks of the line memories of the other beams, the synchronization detection signal of the first beam is delayed by the scanning time interval in the main scanning direction by the light emitting elements to perform phase synchronization, and this clock is further delayed. Since the frequency division is performed, it is possible to reduce the deviation amount of the phase difference of the read clock of each line memory and realize a high quality image. Further, by adjusting the clock delay amount, it is possible to increase the margin in the setup time and hold time of the read clock and the read reset signal of the line memory after the second beam, so that it is possible to prevent abnormal images. .

According to the second aspect of the present invention, the n-1 dummy sync detection signals for the other light emitting elements are generated based on the sync detection signal of the first beam, and the n line memories are written. The reset is performed by the sync detection signal of the first beam, and the write of the n line memories is toggled based on the sync detection signal of the first beam and the n-1 dummy sync detection signals. can do.

According to the third aspect of the present invention, the write clocks of the n line memories are phase-synchronized and frequency-divided to generate the read clock, which can be realized by a simple circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a multi-beam image forming apparatus according to the present invention.

FIG. 2 is an explanatory diagram showing an arrangement position of two laser diodes in FIG.

3 is an explanatory diagram showing scanning positions in the sub-scanning direction of two laser beams in the multi-beam image forming apparatus of FIG.

FIG. 4 is an explanatory diagram showing scanning positions in the main scanning direction of two laser beams in the multi-beam image forming apparatus of FIG.

5 is a circuit diagram showing a synchronization detection circuit of the multi-beam image forming apparatus of FIG.

6 is an explanatory diagram showing a synchronization detection signal detected by the synchronization detection circuit of FIG.

7 is a block diagram showing a schematic configuration of the multi-beam image forming apparatus of FIG.

FIG. 8 is a block diagram showing in detail the configuration of the ASIC of FIG.

9 is a block diagram showing in detail the dummy synchronization detection signal generating circuit of FIG.

10 is a timing chart showing main signals of the ASIC of FIG.

11 is a block diagram showing the LCLR generation circuit of FIG. 8 in detail.

12 is a timing chart showing the LCLR signal of FIG.

13 is a block diagram showing in detail a read enable signal generating circuit in the ASIC of FIG.

FIG. 14 is a block diagram showing in detail a main circuit in the ASIC of FIG.

15 is a block diagram showing an example of the phase locked loop circuit of FIG. 14 in detail.

16 is a timing chart showing main signals of the phase locked loop circuit of FIG.

FIG. 17 is a block diagram showing in detail a conventional main circuit.

18 is a timing chart showing a read clock generated by the circuit of FIG.

19 is a timing chart showing a read clock generated by the circuit of FIG.

[Explanation of symbols]

18, 19 FIFO memory 21 Write / read processing section of FIFO memory / 1 beam → 2 beam conversion section 22 Dummy synchronization signal generation section / LCLR generation section 23a, 23b Phase synchronization circuit 24a, 24b 1/2 frequency division circuit 25 FF 110 , 111 Delay circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) B41J 2/44 G02B 26/10

Claims (3)

(57) [Claims] 1. An n-number of light emitting elements, which are arranged in the main scanning direction at different positions to start emission of a beam modulated according to each image data, according to each arrangement position, and images for the n number of light emitting elements. N line memories for respectively storing data, one synchronization detection element for receiving each beam emitted by the n light emitting elements and outputting a synchronization detection signal, and a first of the n light emitting elements A first phase synchronization circuit that performs phase synchronization of a clock based on a synchronization detection signal of a first beam emitted by a light emitting element and detected by the synchronization detection element; and a synchronization detection signal of the first beam for the light emitting element And a first delay circuit that delays by a scanning time interval in the main scanning direction, and a first phase synchronization circuit that performs phase synchronization based on a synchronization detection signal of the first beam delayed by the first delay circuit. Was And the n-1 phase locked loop circuit for locking the phase locked, by delaying each is phase synchronous clock by the (n-1) phase-locked loop for generating a clock for the other beam n
-1 second delay circuit, each of the clocks generated by the first phase locked loop circuit and the second delay circuit is divided into 1 / n, and each of the n
A multi-beam image forming apparatus comprising: n frequency dividing circuits that generate read clocks for a plurality of line memories. 2. An n-1 dummy sync detection signal for another light emitting element is generated based on the sync detection signal of the first beam, and a write reset of the n line memories is performed for the first beam. The sync detection signal of
2. The multi-beam image forming apparatus according to claim 1, wherein the write of the line memory is toggled based on the sync detection signal of the first beam and the n-1 dummy sync detection signals. 3. The multi-beam image forming apparatus according to claim 1, wherein the phase synchronization circuit performs phase synchronization of write clocks of the n line memories.