JPH09284499A - Image forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of the break of a slash and the irregularity of density due to phase synchronizing deviation with respect to an image forming device for writing an image by a multibeam through the use of plural line memories. SOLUTION: Each of the plural line memories 18 and 19 is write-reset by real synchronization detecting signals DETP 1 and DETP 2 generated by the detection of a laser beam. Toggling operation for making the plural line memories alternately writable is executed by a dummy synchronization detection signal (LCLR) generated from the video clock. The write-enabling of the line memory 18 for a first laser beam is selected by the real synchronization detecting signal DETP 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus such as a copying machine, a printer, a facsimile machine or the like, which writes an image using a multi-beam (a plurality of laser beams).

[0002]

2. Description of the Related Art In an image forming apparatus such as a digital copying machine or a laser printer, it is necessary to increase the video clock frequency in order to speed up the process, and there is no usable IC or laser diode driver. Due to problems, multibeams are used. As a result, if the simultaneous writing of n lines at a time is performed by each laser beam generated by n laser diodes, the video clock frequency can be reduced to 1 / n.

A method of performing writing by using a plurality of line memories is known as disclosed in, for example, Japanese Laid-Open Patent Publication No. 4-20066. However, in such a conventional technique, a write enable signal of two line memories is generated from a true synchronization detection signal generated by detecting a laser beam at a predetermined position before the main scanning start position, or from a video clock. The dummy sync detection signal generated is toggled to select.

[0004]

Therefore, the case where the first laser beam is selected at the beginning of the image effective area and the case where the second laser beam is selected exist at the same probability. Therefore, when starting from the second laser beam, there is a problem that the phase synchronization of the main scanning is deviated and the connection of diagonal lines is interrupted.

Further, in the conventional method, the same video data is inputted to the two laser diodes, but the threshold current and slope efficiency of the laser diodes are slightly different depending on the laser diodes. There is a problem that density unevenness occurs in an image to be formed with a density.

The present invention is intended to solve the above-mentioned problem in an image forming apparatus for performing image writing by multi-beams using a plurality of line memories, and it is possible to solve the problems such as the discontinuity of diagonal lines due to the phase synchronization shift. The purpose is to prevent uneven density.

[0007]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an image forming apparatus for performing image writing by multi-beam by a plurality of line memories.
The dummy reset signal is generated from the video clock to perform the write reset of each line memory with the true sync detection signal generated by the detection of the laser beam, and the operation to make the multiple line memories writable alternately or sequentially. There is provided a read / write control circuit which performs the signal enable and selects the write enable of the line memory for the first laser beam by the true synchronization detection signal.

Further, phase synchronization of the clock of the first laser beam and read reset of the video data are performed by the synchronization detection signal by the first laser beam, and the synchronization detection signal by each of the second and subsequent laser beams is used for the first synchronization. It is advisable to provide a circuit for phase-locking the clocks of the lasers after the second laser and for resetting the read.

In such an image forming apparatus, it is possible to obtain an image with less density unevenness by providing a means for correcting the difference in the light emission amount characteristics of the individual laser diodes which generate each laser beam.

[0010]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 2 shows a configuration example of a scanning optical system using a laser beam. The description in this embodiment will be made by taking an example of using two laser diodes, but the present invention can be similarly implemented even when the number of laser diodes used is three or more.

The laser diode unit 1 is shown in FIG.
2 laser diodes LD1 and LD2
Are arranged at positions separated by a horizontal distance a and a vertical distance b. The laser light generated by each of the laser diodes LD1 and LD2 is collimated by the collimator lens 2 shown in FIGS. 2 and 5, condensed by the beam compressor 3, and laser beams LB1 and LB2 (FIGS. 3 and 5). ). The respective laser beams are scanned by the rotation of the polygon scanner 4 in the direction of arrow A by a regular hexagonal rotating double-sided mirror, and reach the photoconductor 7 through the fθ lenses 5 and 6.

Further, in the main scanning direction of the photoconductor 7 by the laser beam (direction of arrow S in FIG. 2), a synchronization detector 8 is arranged at a predetermined position before the photoconductor 7. The vertical arrangement of the synchronization detector 8 is as shown in FIG. Then, each laser diode LD1, LD2
The laser beams LB1 and LB2 generated by the laser light enter the synchronization detector 8 immediately before scanning the photoconductor 7.

Then, as shown in FIG. 3, two laser beams LB having an interval C in the vertical direction (sub-scanning direction).
After detecting 1 and LB2 by the synchronization detector 8, the photoconductor 7 is irradiated and main scanning is performed as shown in FIG. The distance C is much smaller than the vertical distance b between the laser diodes LD1 and LD2. The beam compressor 3 uses the two laser beams LB1 and LB2.
In the vertical direction (sub-scanning direction).

FIG. 6 shows an example of a sync detecting circuit by the sync detector 8. Although this shows an example in which the photodiode PD is used as the light receiving element of the synchronization detector 8, other light receiving elements may be used. When the photodiode PD receives the laser beam, a current I flows through a resistor R connected in series, and a voltage V1 (V1 = IR) generated at the resistor R is input to a comparator 9, which then outputs a reference voltage Vr. When it exceeds, the comparator 9 detects the positive pulse sync detection signal DE.
Generate TP.

This synchronization detection signal DETP is a true synchronization detection signal, and becomes a first synchronization detection signal DEPT1 by the laser beam LB1 and a second synchronization detection signal DETP2 by the subsequent laser beam LB2.

Next, FIG. 7 shows a structural example of an image data processing system in the image forming apparatus according to the present invention. In FIG. 7, reference numeral 10 is a reading element C for reading an image on a document.
CD, 11 is an image processing gate array (IPU), and 12 is a video processing gate array (GAVD).

Reference numeral 13 denotes an ASIC which is a gate array which is a main part for implementing the present invention, and is a circuit for driving the laser diode control units 14 and 15. 16 to 1
A fifo memory (hereinafter referred to as "FIFO") 9 is used for adjusting the timing of the FIFOs 16 and 17 because the reading and writing pixel frequencies are different. The FIFOs 18 and 19 are used as line memories.

FIG. 8 is a schematic block diagram of the ASIC 13.
A phase synchronization circuit and a frequency dividing circuit for controlling writing and reading of the FIFOs 16 and 17 are provided, and one beam data VDATA input from the video processing gate array (GAVD) 12 is converted into two beam data VDATA1 and VD.
Processing for converting to ATA2, generation of a dummy sync detection signal, generation of signal LCLR, and the like are performed.

A specific circuit configuration of the ASIC 13 is mainly shown in FIG. 1 and a part thereof is also shown in FIGS. 9, 11 and 12. First, FIG. 11 will be described. Dummy synchronization detection signal DETP1D and genuine synchronization detection signal DETP1
The signal obtained by the OR circuit 38 is the DETP1A. The dummy synchronization detection signal DETP1D is a signal which, when the count value of the video clock VCLK by the counter 35 becomes equal to the set value, generates a pulse having a pulse width determined by the one-shot generation circuit 37 by the output of the comparator 36. .

As shown in FIG. 12, the signal LCLR uses the signal DETP1A as input data for the video clock VC.
The three-stage counters 39, 40, and 41 for counting LK are provided, and the AND circuit 43 ANDs the output of the first-stage counter 39 and the signal obtained by inverting the output of the third-stage counter 41 by the symverter 42. It is the signal that took. As a result, this signal LCLR is a signal which becomes "H" for two clock periods while the above-mentioned signal DETP1A is "H", as shown in FIG.

The FIFO 18 in the circuit of FIG.
A line memory 19 is write reset (write address reset) by the real synchronization detection signals DETP1 and DETP2, respectively. These FIFOs 18,
The write clock of 19 is the video clock VCLK, and the write data is the video processing gate array (GAV).
D) Video data VDATA from 13.

The output of the flip-flop circuit (FF) 25 is toggled by the signal LCLR generated by the circuit of FIG. 12, and the F gate signal FG from the AND circuit 26 is output.
It is reset by the AND output of ATE and the first synchronization detection signal DETP1. Output of this FF25 / Q (Q
Means that the write enable of the FIFO 18 is "H", and when the output / Q of the FF25 is "L", the write of the FIFO 18 is disabled and the write of the FIFO 19 is enabled. become. 27
Is an inverter.

As shown in FIG. 13, the signal LCLR is a signal which becomes "H" for two clock periods when the true synchronization detection signal DETP1 or the synchronization detection signal DETP1A including a dummy is generated. The F gate signal FGATE is
The effective range of the sub-scanning image area is shown. In the phase synchronization circuit 21, the video clock VCLKA is a clock in which the video clock VCLK is phase-synchronized with the first synchronization detection signal DETP1. Further, in the phase synchronization circuit 22, the video clock VCLK is fed to the second synchronization detection signal DE.
The clock synchronized in phase with TP2 is the video clock V
CLKB.

True synchronization detection signals DETP1, DETP2
As shown in FIG. 17, the time t
It occurs at a timing that is just off. This shift time t is a time corresponding to the horizontal distance a between the laser diodes LD1 and LD2 shown in FIG. That is, the first laser beam L
In response to the first synchronization detection signal DETP1 from B1, the second synchronization detection signal DE from the second laser beam LB2
TP2 is delayed for time t.

FIG. 14 shows a timing chart of reading and writing of the FIFOs 18 and 19 which are line memories. Write reset of these FIFOs 18 and 19 (W RE
S) and read reset (R RES) are true first and second
Of the synchronous detection signals DETP1 and DETP2, and the write toggle operation is performed with the dummy synchronous detection signal DETP1D.

The FF 25 shown in FIG. 1 is a flip-flop for toggling the write enable of the FIFOs 18 and 19, the output of which is toggled by the signal LCLR, and the AND gate 26 of the F gate signal FGATE and the first sync detection signal DETP1. It is reset by the signal that took. Therefore, since the FF1 is reset by the first first synchronization detection signal when the image effective area starts, the FIFO
The write enable (WE) of 18 becomes "H".

The FIFO 18 is a line memory for the first laser beam. At the next LCLR signal (generated at the rising edge of the dummy sync detection signal DETO1D), FF25
Output is inverted, and the output / Q of FF25 becomes "L".
This enables the write enable (WE) of the FIFO 18.
Becomes non-active, and the write enable (WE) of the FIFO 19 becomes active. This FIFO 19 is a line memory for the second laser beam.

Since the system is as described above, when the F gate signal FGATE becomes "H" and the image effective area starts, the real first synchronization detection signal is DETP1 by DETP1.
FIFO1 which is a line memory for the first laser beam
8 write enable is selected. Therefore FIF
Since the read data of O also starts from the first laser beam, the laser diode that outputs the first laser beam emits light when the image effective area starts, so that an image with a small phase shift can be obtained.

The clock obtained by phase-locking the video clock VCLK with the first synchronization detection signal DETP1 is VCLK.
Although it has been described that the clock signal is A and VCLKB is a clock obtained by phase-locking VCLK with the second synchronization detection signal DETP2, there are various methods for achieving phase synchronization.

FIG. 15 shows an example of a circuit that implements the one method.
16 shows a timing chart. 1/8 (t
1) Create eight clocks whose phases are delayed from the input clock by -8/8 (t8) by the delay elements 51 and 52,
Forward / backward signal forming circuits 53 and 54, and NAND circuit group 5
A clock having the closest phase to the synchronization detection signal DETP is output as a synchronization clock output by the logic circuit including 5, 56 and the OR circuit. The phase synchronization accuracy in this case is 1 /
It becomes 8 dots.

As shown in FIG. 1, the video clock VC
The phase synchronization circuit 21 outputs the first synchronization detection signal DE to LK.
The clock that is phase-synchronized by TP1 and divided by the divider circuit 23 becomes the video clock VCLK1 of the laser diode LD1. A clock obtained by phase-locking the video clock VCLK with the second synchronization detection signal DETP2 by the phase-locking circuit 22 and frequency-dividing by the frequency-dividing circuit 24 is the video clock VCLK of the laser diode LD2.
It becomes 2.

The video processing gate array (G
AVD) Video data VDATA from 12 is FIFO
Since 18 and 19 are used to form 2 lines and 2 beams are simultaneously written, the video clock frequency is 1/2 of VCLK.
Is fine. That is, the video clock VCLK may be divided by 1/2. The FIFO 18 uses the first synchronization detection signal DE
The read reset (clear read address) is performed at TP1, and the FIFO 18 is read reset at the second synchronization detection signal DETP2.

As shown in the circuit of FIG. 9, the video clock VCLK1 is counted by the counter 31, and when the count count value becomes equal to the set value 1, the comparator 3
Read enable RE1 of FIFO 18, which is the output of 3
Becomes “H”. On the other hand, when the video clock VCLK2 is counted by the counter 32 and the count value becomes equal to the set value 2, the FIFO output from the comparator 34 is output.
The read enable RE2 of 19 becomes "H".

17 and 18 are block diagrams of the laser diode control units 14 and 15 in FIG. LUT6
1, 62 are input video data VDATA1, VDAT
It is a look-up table which carries out data conversion of each A2.

The laser diodes have slightly different threshold currents and slope efficiencies. Therefore, in order to correct the difference in the light amount characteristics of the laser diodes LD1 and LD2, the look-up table 6 as shown in FIGS.
The video data is corrected by 1, 62 so that the image having the same density can be obtained with the same video data. 63, 64
Are LD drivers for driving the laser diodes LD1 and LD2, respectively, and the laser diodes LD1 and LD2 are
In both cases, the laser diode LD and the photodiode for detecting the amount of emitted light are provided in the same case.

According to the above-described embodiment, each line memory write reset signal is generated when each laser beam is detected at a predetermined position before the main scanning start position by each laser beam. First,
Since the write enable of the line memory for the first laser beam is selected by the true synchronization detection signal from the laser beam, the laser diode emits light from the first laser beam when the image effective area starts, and the phase shift is small. An image is obtained.

Further, phase synchronization of the clock of the first laser beam and read reset of the video data are performed by the synchronization detection signal by the first laser beam, and by the synchronization detection signal by each of the second and subsequent laser beams, respectively. Since the clock phase synchronization and the read reset of each of the second and subsequent laser beams are performed, it is possible to obtain an image in which the deviation of the main scanning positions of the first and second laser beams from each other is small with a simple configuration. Further, since it is possible to correct the difference in the light emission amount characteristic of each laser diode that generates each laser beam, it is possible to obtain an image with little density unevenness.

[0038]

As described above, according to the present invention, in an image forming apparatus which uses a plurality of line memories for images using multi-beams, it is possible to prevent discontinuity of diagonal lines and uneven density due to phase synchronization shift. Therefore, the image quality can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of an ASIC 13 in FIG.

FIG. 2 is a plan view showing a configuration example of a scanning optical system using a laser beam of the image forming apparatus according to the present invention.

FIG. 3 is a simplified front view of the same.

FIG. 4 is an enlarged front view of the laser diode unit in FIG.

5 is a side view of the optical path of the laser beam from the laser diode unit 1 to the synchronous detector 8 in FIG.

6 is a circuit diagram showing an example of a synchronization detection circuit by the synchronization detector 1 shown in FIG.

FIG. 7 is a block diagram showing a configuration example of an image data processing system in the image forming apparatus according to the present invention.

8 is a configuration diagram showing an outline of an ASIC 13 in FIG.

FIG. 9 is a block diagram of a circuit that generates a read enable RE1 from a video clock VCLK1.

FIG. 10 is a block diagram of a circuit that generates a read enable RE2 from a video clock VCLK2.

FIG. 11 is a block diagram of a circuit that generates a dummy synchronization detection signal and a signal DETP1A from the video clock VCLK.

FIG. 12 is a signal DET generated by the circuit of FIG.
It is a block diagram of the circuit which produces | generates signal LCLR from P1A.

FIG. 13 is a waveform diagram showing a relationship between a signal DETP1A and a signal LCLR.

14 is a timing chart of reading and writing of the FIFOs 18 and 19 shown in FIG.

FIG. 15 is a circuit diagram showing an example of a circuit for phase-locking the video clock VCLK with a synchronization detection signal.

FIG. 16 is a timing chart showing the same operation.

FIG. 17 is a waveform diagram showing the relationship between the first synchronization detection signal DETP1 and the second synchronization detection signal DETP2.

18 is a block diagram showing a configuration example of the LD control unit 14 shown in FIG.

19 is a block diagram showing a configuration example of the LD control unit 15 shown in FIG.

FIG. 20 is a lookup table 61 in FIG.
20 is a diagram showing a characteristic example of a lookup table 62 in FIG.

[Explanation of symbols]

 1: Laser diode unit 2: Collimating lens 3: Beam compressor 4: Polygon scanner 5, 6: fθ lens 7: Photoconductor 8: Sync detector LD1, LD2: Laser diode LB1, LB2: Laser beam 10: CCD 11: Image processing gate array 12: Video processing gate array 13: ASIC 14, 15: LD control unit 16, 17: Fifo memory (FIFO) 18, 19: FIFO (line memory) 21, 22: Phase control circuit 23, 24: Frequency divider circuit 25: Flip-flop circuit (FF) 31, 32, 35: Counter 33, 34, 36: Comparator 37: One-shot generation circuit 61, 62: Look-up table 63, 64: LD driver

Claims (3)

[Claims] 1. An image forming apparatus in which image writing by multi-beam is performed by a plurality of line memories, wherein write reset of each of the plurality of line memories is performed by a true synchronization detection signal generated by detection of a laser beam. A read / write control in which the operation for making the line memories sequentially writable is performed by the dummy sync detection signal generated from the video clock, and the write enable of the line memory for the first laser beam is selected by the true sync detection signal. An image forming apparatus having a circuit. 2. The image forming apparatus according to claim 1, wherein
Phase synchronization of the clock of the first laser beam and read reset of the video data are performed by the synchronization detection signal from the first laser beam, and second and subsequent synchronization signals by the second and subsequent laser beams are respectively synchronized. An image forming apparatus comprising a circuit for phase synchronization of a laser clock and a read reset. 3. The image forming apparatus according to claim 1, further comprising means for correcting a difference in light emission amount characteristic of each laser diode which generates each laser beam.