JP3500263B2 - Multi-beam image forming device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-beam image forming apparatus that forms an image by writing images substantially simultaneously using a plurality of beams.

[0002]

2. Description of the Related Art Generally, when an attempt is made to increase the speed of a copying machine or printer, the frequency of the video clock becomes high and there is no available IC or LD (laser diode) driver. A method has been proposed in which different images are assigned to a plurality of writing beams to perform optical modulation as shown in FIG. According to this method, when writing n lines simultaneously using n LDs, the frequency of the video clock can be reduced to 1 / n.

Further, for example, when two lines are simultaneously written on the photosensitive member by two beams using two LDs,
Two beams are detected by one synchronization detection sensor, a dummy synchronization detection signal for the second beam is generated from the real synchronization detection signal detected by the first beam, and based on these two synchronization detection signals Image data for two lines is written in each line memory and transferred to the LD.

Another conventional example is Japanese Patent Laid-Open No. 5-6.
As disclosed in Japanese Patent No. 078, there is proposed a method of selecting the clock of each beam based on each synchronization detection signal of multi-beam.

[0005]

However, in this way, a plurality of light emitting elements are arranged displaced in the main scanning direction, and the emission of the beam modulated according to each image data is started according to each arrangement position. In the beam image forming apparatus, when one or more of the plurality of beams come to the outer edge of the synchronization detection sensor,
Since the jitter of the synchronization detection signal becomes large, when an image of that line is written based on such a synchronization detection signal, an abnormal image such as a vertical line bending due to each line shifting in the main scanning direction occurs. There is a point.

Further, unless the phase of the video clock of each line is adjusted by the synchronization detection signal of each beam, there is a problem that an abnormal image occurs such that the dots are displaced in the main scanning direction and the vertical lines are bent. .

In view of the above-mentioned conventional problems, the present invention is directed to a case where a plurality of light emitting elements are arranged displaced in the main scanning direction and emission of a beam modulated according to each image data is started according to each arrangement position. It is an object of the present invention to provide a multi-beam image forming apparatus capable of realizing a high quality image.

[0008]

In order to achieve the above-mentioned object, a first means is a multi-beam image forming apparatus which forms an image by writing with a multi-beam,
N is arranged to be displaced in the main scanning direction, and the emission of the beam modulated according to each image data is started according to each arrangement position.
Light emitting elements, one synchronization detecting element that receives each beam emitted by the n light emitting elements and outputs a synchronization detection signal of each beam, and one light emitting element of the n light emitting elements And a monitoring means for monitoring the jitter of each sync detection signal detected by the sync detection element by another light emitting element based on the sync detection signal detected by the sync detection element. It is characterized by

In a second means, in the first means, the monitoring means outputs a synchronization detection signal detected by the synchronization detection element by one light emitting element of the n light emitting elements, and the other. The light emitting element emits the light and issues a warning when the time between the respective synchronization detection signals detected by the synchronization detection element is equal to or more than a specified value.

The third means includes n line memories for respectively storing image data for the n light emitting elements in the first and second means, and synchronous detection of each beam detected by the synchronous detection element. It is characterized by further comprising a phase synchronization of a clock for each of the n light emitting elements based on a signal and a control means for performing a read reset of the line memory.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of a multi-beam image forming apparatus according to the present invention, FIG. 2 is an explanatory diagram showing arrangement positions of two laser diodes in FIG. 1, and FIG.
4 is an explanatory view showing scanning positions of two laser beams in the sub-scanning direction in the multi-beam image forming apparatus of FIG. 1, and FIG. 4 shows scanning positions of two laser beams in the main-scanning direction in the multi-beam image forming apparatus of FIG. 5 is a circuit diagram showing a synchronization detection circuit of the multi-beam image forming apparatus of FIG. 1, FIG. 6 is an explanatory diagram showing a synchronization detection signal detected by the synchronization detection circuit of FIG. 5, and FIG. FIG. 8 is a block diagram showing a schematic configuration of a multi-beam image forming apparatus of FIG.
FIG. 9 is a block diagram showing the configuration of the SIC in detail, FIG. 9 is a block diagram showing the dummy synchronization detection signal generating circuit of FIG. 8 in detail, and FIG. 10 is a timing chart showing the main signals of the ASIC of FIG.

FIG. 11 is a block diagram showing the LCLR generation circuit of FIG. 8 in detail, FIG. 12 is a timing chart showing the LCLR signal of FIG. 11, and FIG. 13 is a detail of the read enable signal delay circuit in the ASIC of FIG. FIG. 14 is a block diagram showing in detail a main circuit in the ASIC of FIG. 8, FIG. 15 is a block diagram showing in detail an example of the phase locked loop circuit of FIG. 14, and FIG. 16 is a block diagram of the phase locked loop circuit of FIG. 17 is a timing chart showing the main signals, FIG. 17 is a block diagram showing in detail the jitter detection circuit for the synchronization detection signal of FIG.
17 is a timing chart for explaining the operation of the jitter measuring circuit of FIG. 17, and FIG. 19 is a flow chart for explaining the jitter warning operation of the CPU of FIG. In the following description, since an image is formed by a well-known electrophotographic image forming unit after the image is written by the multi-beam, the description regarding the image forming unit is omitted here.

1 to 4, an LD unit 2 is mounted on an LD control plate 1, and two LD1 and LD2 are mounted on the LD unit 2 as an example. Note that L
Even if the number of D is 3 or more, the basic idea is the same. The laser beams emitted from LD1 and LD2 are
The beams are collimated by the common collimator lens 3, and then the beam compressor 4 focuses only the sub-scanning direction of the beam on the reflecting surface of the polygon scanner 5. The polygon scanner 5 rotates in the main scanning direction indicated by the arrow, whereby the laser beam is deflected in the main scanning direction at a constant angular velocity. This beam is corrected by the fθ lens 6 so as to be deflected at a constant velocity, and then is irradiated onto the photoconductor 7 and detected by the synchronization detection element 8. The photoconductor 7 rotates in the sub scanning direction.

Two LD1 and LD2 on the LD unit 2
2 are arranged at a distance a in the main scanning direction and at a distance b in the sub scanning direction. The two beams emitted from the LD1 and LD2 and reflected by the polygon scanner 5 as shown in FIG. 3 are separated by a distance C in the sub-scanning direction because the beam compressor 4 condenses only in the sub-scanning direction. Further, the distance C becomes a value much smaller than the distance b.

Further, as shown in FIG. 4, the two beams emitted from the LD1 and LD2 are received by the synchronization detection element 8 after being shifted by the distance a in the main scanning direction between the LD1 and LD2. As shown in FIG. 5, the synchronization detecting element 8 has a photodiode (PD) 9 as an example. When the PD 9 receives a beam, a current I flows, and when V1 (= IR) exceeds a reference voltage Vref, a comparator 10 is provided. Outputs a positive pulse sync detection signal DETP. In this case, as shown in FIG. 6, a synchronization detection signal DETP1 when the first beam of LD1 is detected and a synchronization detection signal DETP2 when the second beam of LD2 is detected are generated in one cycle, and the synchronization detection signal DETP2 is generated. The synchronization detection signal DETP2 lags behind the signal DETP1.

AS (application specific) IC 14 shown in FIG.
Constitutes a monitoring means and a control means in the multi-beam image forming apparatus of the present invention. In FIG. 7, the writing speed is half the reading speed, and the CCD 11 reads the original image and outputs the image signal to the IPU (image processing gate array) 12. The IPU 12 supplies the image data SDATA and the clock signal SCLK to the GAVD (video processing gate array) based on the image signal from the CCD 11.
It outputs to 13.

The GAVD 13 is based on the signals SDATA and SCLK from the IPU 12, the first beam synchronization detection signal DETP1 and the image clock VCLK, which will be described later, and uses the FIFO memories 16 and 17 to output the image data VDATA and the clock. Signal VCLK to ASIC1
Output to 4. Here, the FIFO memories 16 and 17 are
Since the pixel frequency is different between reading and writing, the timing is adjusted. In the present embodiment, the first
The real sync detection signal of the beam (hereinafter, real sync detection signal) DETP1, the dummy sync detection signal (hereinafter, dummy sync detection signal) DETP1 'generated based on the real sync detection signal DETP1, and the second beam The synchronization detection signal DETP2 is used.

The ASIC 14 receives the signals VDATA and VCLK from the GAVD 13 and the real sync detection signal DETP.
The image data VD based on the first and second beam synchronization detection signals DETP2 and by using the FIFO memories 18 and 19.
LD at half the speed of ATA and clock signal VCLK
1 image data VDATA1 and clock signal VCL
K1 is generated and output to the first LD control unit 15a, and the image data VDATA2 for LD2 and the clock signal VCLK2 are generated and output to the second LD control unit 15b. The FIFO memories 18 and 19 are GAVs as will be described later.
It is used to convert the one-beam data VDATA from D13 into two-beam data VDATA1 and VDATA2.

The ASIC 14 is also connected to the CPU 201 and the I / O port 202 via a data bus and an address bus. Further, as shown in detail in FIG. 8, the write / read processing unit / one beam of the FIFO memories 18 and 19 → The two-beam converter 21, the dummy sync signal generator / LCLR generator 22, the phase sync circuit 23, and the clock divider 24
And a jitter detection unit 25 for the synchronization detection signal. I / O
The port 202 is connected to the operation unit 203, and the operation unit 203 includes a display unit.

In the dummy sync signal generator (22), as shown in FIG. 9, the counter 31 controls the pixel clock VCLK.
Is counted, and then the count value of the counter 31 and 1 of the real synchronization detection signal DETP1 are counted by the comparator 32.
The set value corresponding to 1/2 of the cycle is compared. Then, when the comparison result of the comparator 32 is matched by the one-shot generation circuit 33, a dummy synchronization detection signal DEPT1 'having a predetermined pulse width is generated, and then the OR gate 34 is used to generate the dummy synchronization detection signal DEPT1' as shown in FIG. The logical sum signal DETP1A of the synchronization detection signal DETP1 is output.

The LCLR generator (22) has D flip-flops 35, 36 and 37, an inverter 38 and an AND gate 39 as shown in FIG.
As shown in FIG. 2, a signal LCLR that goes high for two pixel clock periods is generated while the signal DETP1A goes high.

FIG. 13 shows a circuit for generating the read enable signal RE in the ASIC 14. Counter 10
Reference numerals 1 and 102 are cleared by the real sync detection signal DETP1 and the second beam sync detection signal DETP2, respectively, and count the pixel clocks VCLK1 and VCLK2. Comparators 103 and 104 are counters 101 and
Each count value of 102 is compared with each set value corresponding to the distance a of LD1 and LD2 in the main scanning direction, and when they match, the read enable signals XRE1 and XRE2 of the FIFO memories 18 and 19 as shown in FIG. Is output.

FIG. 14 shows a write / read processor / one-beam → two-beam converter 21 of the FIFO memories 18 and 19.
The phase synchronization circuit 23 and the clock frequency divider 24 are shown.
The phase synchronization circuit 23 includes two systems of phase synchronization circuits 23a and 23a.
b, and the clock frequency division section 24 also has frequency division circuits 24a and 24b of two systems. Phase synchronization circuits 23a, 23
b indicates the pixel clock VCLK and the synchronization detection signal DE, respectively.
Pixel clocks VCLKA and VCLKB phase-synchronized by TP1 and DETP2 are output, and the frequency divider circuits 24a and
24b are pixel clocks VCLKA and VCLKB, respectively.
Is divided in half and applied as a write clock RCLK for the FIFO memories 18 and 19.

Here, the phase synchronization circuits 23a and 23b are connected to the input clock VCL as shown in FIGS. 15 and 16, for example.
The pixel clock VCL is generated by shifting K by 1/8 cycle to generate eight types of clock signals and selecting the clock signal having the closest phase to the synchronization detection signals DETP1 and DETP2.
It is possible to output KA and VCLKB. In this example, the phase synchronization accuracy is 1/8 dot.

As shown in FIGS. 14 and 10, both the FIFO memories 18 and 19 are reset by write (line address reset) by the genuine synchronization detection signal DETP1 (WRES in the figure). The other input signals are the pixel clock VCLK and the image data VD from the GAVD13.
ATA uses FF25 as write data WDATA.
/ Q (/ indicates an inverted signal) signal is applied as the write enable signal WE.

The FF 25 and the inverter 26 are provided for toggling the write enable signal WE of the FIFO memories 18 and 19, and the sub-scanning image area effective signal FGATE.
It is reset by the logical product signal of the real synchronization detection signal DETP1. Therefore, the write enable signal WE of the FIFO memory 18 becomes high at this time because it is reset by the first real sync detection signal DETP1 after the start of the image effective area. In addition, FF25 is a signal LC
LR toggles outputs Q and / Q, and FIFO memory 1
The write enable signals WE of 8 and 19 alternately become high by the signal LCLR. Therefore, since the FIFO memory 18 is selected by the first real sync detection signal DETP1 after the start of the image effective area, LD1 always emits light first, and as a result, the arrangement positions of LD1 and LD2 in the main scanning direction are changed. Even if they are deviated, there is no problem that the phase synchronization in the main scanning direction is deviated and the oblique lines are interrupted.

The ASIC 14 also has a circuit 25 for measuring the jitter of the second beam sync detection signal DETP2 with reference to the rising edge of the first beam sync detection signal DETP1 as shown in detail in FIGS. 17 and 18, when the JK-FF211 is set at the rising edge of the synchronization detection signal DETP1 on the first line, the input terminal EP of the counter 212 becomes high, and the counter 212 starts counting the clock CLK. In addition, the JK-FF211 outputs the second synchronization detection signal D
When reset by ETP2, the input terminal EP of the counter 212 goes low and the counter 212 stops counting.

The FFs 216 to 218 include delay elements 21.
3, the counter 214 and the gate 215, the first synchronization detection signal DETP1 and the sub-scanning image area effective signal FGAT.
The clock signal based on E is applied, and the counter 212
7 is latched by the FF 216 and sent to the CPU 201 shown in FIG. 7 via the I / O port 219. Similarly, the JK-FF 211 and the counter 212 operate in the second line and the count value of the counter 212 is latched by the FF 217, and the JK-FF 211 and the counter 212 similarly operate in the third line and the count value of the counter 212. Are latched by the FF 218.

The CPU 201 is the first to the first as shown in FIG.
The first and second synchronization detection signals DETP1 for every third line,
On the basis of the count value of the clock CLK during the DETP2, if the absolute value of the difference between the clock count numbers in the first line and the second line is not equal to or less than the specified value as shown in FIG. 19 (step S1), the second line And the absolute value of the difference between the clock count numbers on the third line is not less than the specified value (step S2), the absolute value of the difference between the clock count numbers on the third line and the first line is less than the specified value (step S2). In any of S3), a warning is displayed on the operation unit 203 (step S4).

[0030]

As described above, according to the first aspect of the invention, one light emitting element among the n light emitting elements emits the other light emitting element based on the synchronization detection signal detected by the other light emitting element. Since the jitter of each sync detection signal that is emitted and detected is monitored, a plurality of light emitting elements are arranged offset in the main scanning direction, and the emission of the beam modulated according to each image data is arranged in each arrangement. High quality images can be achieved when starting according to position.

According to the second aspect of the present invention, a warning is issued when the time between each synchronization detection signal is equal to or more than a specified value, so that a high quality image can be realized by performing repair.

According to the third aspect of the invention, the phase synchronization of the clock for each light emitting element and the read reset of the line memory are performed based on the synchronization detection signal of each beam. It is possible to realize a high-quality image with no deviation.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a multi-beam image forming apparatus according to the present invention.

FIG. 2 is an explanatory diagram showing an arrangement position of two laser diodes in FIG.

3 is an explanatory diagram showing scanning positions in the sub-scanning direction of two laser beams in the multi-beam image forming apparatus of FIG.

FIG. 4 is an explanatory diagram showing scanning positions in the main scanning direction of two laser beams in the multi-beam image forming apparatus of FIG.

5 is a circuit diagram showing a synchronization detection circuit of the multi-beam image forming apparatus of FIG.

6 is an explanatory diagram showing a synchronization detection signal detected by the synchronization detection circuit of FIG.

7 is a block diagram showing a schematic configuration of the multi-beam image forming apparatus of FIG.

FIG. 8 is a block diagram showing in detail the configuration of the ASIC of FIG.

9 is a block diagram showing in detail the dummy synchronization detection signal generating circuit of FIG.

10 is a timing chart showing main signals of the ASIC of FIG.

11 is a block diagram showing the LCLR generation circuit of FIG. 8 in detail.

12 is a timing chart showing the LCLR signal of FIG.

13 is a block diagram showing in detail a read enable signal generating circuit in the ASIC of FIG.

FIG. 14 is a block diagram showing in detail a main circuit in the ASIC of FIG.

15 is a block diagram showing an example of the phase locked loop circuit of FIG. 14 in detail.

16 is a timing chart showing main signals of the phase locked loop circuit of FIG.

FIG. 17 is a block diagram showing in detail the jitter detection circuit for the synchronization detection signal of FIG. 8.

FIG. 18 is a timing chart for explaining the operation of the jitter measuring circuit of FIG.

19 is a flow chart for explaining a jitter warning operation of the CPU of FIG.

[Explanation of symbols]

LD1, LD2 Laser diode 14 ASIC 18, 19 FIFO memory 21 FIFO memory write / read processing unit / 1 beam → 2 beam conversion unit 22 Dummy sync signal generator / LCLR generator 25 Sync detection signal jitter measuring circuit 201 CPU 203 Operation part

Claims (3)

(57) [Claims] 1. A multi-beam image forming apparatus for forming an image by performing writing with a multi-beam, which is arranged so as to be displaced in the main scanning direction and emits a beam modulated according to each image data according to each arrangement position. Start n
Light emitting elements, one synchronization detecting element that receives each beam emitted by the n light emitting elements and outputs a synchronization detection signal of each beam, and one light emitting element of the n light emitting elements And a monitoring unit for monitoring the jitter of each synchronization detection signal detected by the synchronization detection element by another light emitting element based on the synchronization detection signal detected by the synchronization detection element. Multi-beam image forming device. 2. The synchronization means detects the synchronization detection signal detected by the synchronization detecting element by one of the n light emitting elements, and the synchronization detecting signal by another light emitting element. 2. The multi-beam image forming apparatus according to claim 1, wherein a warning is issued when the time between each synchronization detection signal detected by the detection element is a specified value or more. 3. An n number of line memories for respectively storing image data for the n number of light emitting elements, and each of the n number of light emitting elements based on a synchronization detection signal of each beam detected by the synchronization detection element. 3. The multi-beam image forming apparatus according to claim 1, further comprising: a phase synchronization of a clock and a control unit that resets the read of the line memory.