JPS62128272A - Recorder - Google Patents

Abstract

PURPOSE:To correct the phase difference between respective optical beams with a simple constitution by reading image information corresponding to the plural optical beams by a picture scanning clock corresponding to the optical beams of the plural optical beams photodetected by an optical sensor initially. CONSTITUTION:When a synchronizing sensor FS photodetects the optical beam from a laser diode LD1 of a semiconductor laser array LD, a phase locked loop circuit PS outputs a clock signal CK0 according to this output, inputs to a column management address counter CA and a control circuit CC and the image information of the designated address is read from a memory ME and latched to a latch circuit LC. A delay circuit TC produces the image scanning clocks signals CK1-CKm corresponding to the respective laser diodes LD1-LDm of the semiconductor laser array LD and outputs, they are inputted to respective shift registers SL1-SLm as shift clocks and the respective image information is outputted successively. Since there is the phase difference of a delay time according to the phase shift in a main scanning direction in the signals CK1-CKm, the phase difference between the respective beams is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a recording device that scans an object with a plurality of light beams.

BACKGROUND OF THE INVENTION Conventionally, there is generally a scanning type recording apparatus that scans an object with, for example, a plurality of light beams.

Incidentally, in such a recording apparatus, for example, a semiconductor laser array, which is a light source for generating a light beam, is mounted at an angle in order to make the scanning line spacing close.

Therefore, when a plurality of light beams are simultaneously scanned, there is a problem that a phase difference (phase shift) in the main scanning direction occurs between the light beams.

This invention has been made in view of the above points, and it is an object of the present invention to correct the phase difference between each light beam with a simple configuration.

In order to achieve the above object, the present invention reads image information corresponding to a plurality of light beams using an image scanning clock corresponding to the light beam that is first received by a photosensor among the plurality of light beams. It was designed to be released.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The semiconductor laser array LD consists of a plurality (m) of laser diodes LD, to LDm, and is arranged at an angle θ with respect to the main scanning direction, for example, as shown in FIG. 2 (A). .

Therefore, the beam spots of the light beams output from each laser diode LDI-LDm of this semiconductor laser array LD are shifted in the main scanning direction as shown in FIG. 2(b).

The synchronous sensor FS is provided outside the image scanning area by the light beams from each of the laser diodes LD1 to LDm of the semiconductor laser array LD.
It consists of an optical sensor that first receives the light beam from the laser diode LD in D, and a circuit that performs shaping processing on the output of this optical sensor.

The phase synchronized circuit PS is a circuit that generates and outputs a clock signal CKo when the output corresponding to the first light beam received from the synchronous sensor FS is input, and this clock signal CKo is generated when the synchronous sensor FS first receives the light beam. The light beam is synchronized with the light beam. Further, this phase synchronization circuit PS performs phase adjustment within 1/N of one clock. however.

N≧2.

The delay circuit TC inputs the clock signal CKo from the one-phase synchronization circuit PS, generates and outputs image scanning clock signals CKH-CKm corresponding to each laser diode LD, to LDm of the semiconductor laser array LD.

Image information (data) to be recorded is stored in the memory ME, and data at addresses specified by the one-row management address counter RA and the column management address counter CA is read out from the terminals Q1 to Qm.

The column management address counter CA is a one-phase synchronous circuit PS.
The specified address is updated every time the clock signal CKo from the CK is input.

The control circuit CC controls the memory M based on the output of the synchronous sensor FS and the clock signal CKo from the phase synchronous circuit PS.
Generates a control signal LltL2 necessary when transferring image information from E using a clock signal CK, and generates a control signal LltL2.
! is output to the column management address counter CA, and a control signal L2 is output to the row management address counter RA.

Note that the control signal output from this control circuit CC is 1
This is a signal to determine the valid range of data on the line.
Control signal L2 is a signal for line feed.

The latch circuit LC inputs the output from each terminal Q1 to Qm of the memory ME to the terminal D1 to Dm, and the phase locked circuit PS
output from terminals Q1 to Qm in synchronization with clock signal CKo from.

In other words, the latch circuit LC is a buffer circuit for resynchronizing data read out from the memory ME by the clock signal CKo with the clock signal CK. Therefore, in this latch circuit LC, the outputs from the terminals Q1 to Qm of the memory ME are the shift registers SL, to S.
This is not necessary unless a phase shift occurs before reaching Lm.

The shift registers SL, ~SLm are connected to each terminal Q! of the latch circuit LC. The outputs from ~Qm are read as shift clocks from the respective clock signals CK1-CKm from the delay circuit TC and output.

That is, this shift register SL is a circuit that corrects the phase difference between each light beam emitted from each laser diode LD, to LDm of the semiconductor laser array LD.

The video control circuit VC is a shift register SL.

A video signal is generated and output using the clock signal CK from the phase synchronization circuit PS as a control clock in accordance with the input from ~SLm and the input from the synchronization sensor FS.

Note that the video signal output from the video control circuit VC includes a synchronization modulation signal that falls when the output from the synchronization sensor FS is obtained.

Moreover, this synchronization modulation signal does not need to be applied to the other laser diodes LD2 to LDm, except for the synchronization modulation signal of the laser diode LD, which is input first to the synchronization sensor FS.

The drive circuits DR, ~D Rm modulate the respective laser diodes LD, ~LDm of the semiconductor laser array LD with each video signal from the video control circuit VC.

Next, the operation of this embodiment configured as described above will be explained with reference to FIG. 3 and subsequent figures.

When the synchronization sensor FS receives a light beam from the laser diode LD of the semiconductor laser array LD, the phase synchronization circuit PS outputs a clock signal CKo based on this output.

Thereby, this clock signal CKo is input to the column management address counter CA and the control circuit CC, and the memory M
Image information at a designated address is read from E and latched into latch circuit LC.

On the other hand, the delay circuit TC controls each laser diode LD1 to LDm of the semiconductor laser array LD, for example, as shown in FIG.
Image scanning clock signals CK1 to CKm corresponding to the image scanning clock signals CK1 to CKm are generated and output.

In FIG. 3, t d k (k=1 to m) represents the delay time of the image scanning clock signal CKk (k=, to m) from the clock signal CKo. However, there is no regulation regarding the magnitude relationship between the delay times tdl to tdm.

As a result, each image scanning clock signal CK, ~CKm from this delay circuit TC is inputted as a shift clock to each shift register SL, ~SLm, and each image information from the latch circuit LC is sequentially inputted from the shift register SL, ~SLm. Output.

At this time, each image scanning clock signal CK, ~CKm from the delay circuit TC has a delay time corresponding to the phase shift in the main scanning direction between each light beam of each laser diode LD, ~LDm of the semiconductor laser array LD. Because there is a time difference,
Each laser diode LD of the semiconductor laser array LD, ~
The phase difference between each beam of the LDm is corrected.

Therefore, the video control circuit VC uses this shift register S.
Image information and synchronization sensor F transferred from LI-8Lm
The drive circuit DR generates a video signal according to the output of S.
~D Rm, and each laser diode LD of the semiconductor laser array LD is outputted by this drive circuit DR, -DRm.
, ~modulates LDm.

Figure 4 shows the laser diode L of the semiconductor laser array LD.
A timing chart is shown when the output of D is first input to the synchronous sensor FS.

In the same figure, TDk (k=t ~ m) is the memory M
From when each data (image information) is read from E.

It represents the delay time until each laser diode LD, to LDm of the semiconductor laser array LD is modulated with each image information. However, during the delay time TD, ~TDm, TDm>
There is a relationship of ・・・・・・・・・> T D 2 > T D t.

In this way, in this recording device, the image information corresponding to the plurality of light beams is read out using the image scanning clock corresponding to the first light beam received by the optical sensor among the plurality of light beams. The configuration for correcting the phase difference of the light beam becomes simple.

That is, each data (
This is because the reading clock for image information only requires one clock signal (clock signal CKO).

Only one type of address counter is required, which simplifies the memory configuration.

Further, since the phase difference between each light beam is determined by the clock signal (clock signal CK, -CKm) corresponding to each light beam, high accuracy and high printing quality can be obtained.

Furthermore, when there is only one data readout line, a clock with a frequency N times higher than the image scanning clock (N is the number of light beams) or more is required, whereas the readout clock for each image information (data) is Advantageously, the frequency can be the same as that of the image scanning clock.

Furthermore, in order to correct the phase difference between each light beam, it is conceivable to simply read out the image information corresponding to each semiconductor laser using the image scanning clock corresponding to each semiconductor laser, but in this case, the memory On the other hand, it is difficult to secure a phase difference within one clock by correcting the output data from.

By synchronizing with the light beam input to the photosensor first and reading the image information corresponding to each semiconductor laser using the clock, a phase difference within one clock can be easily ensured.

As described above, according to the present invention, the phase difference between each light beam can be corrected with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is an explanatory diagram for explaining the arrangement of the semiconductor laser array and the light beam. FIG. 3 is a timing chart of the image scanning clock, and FIG. 4 is a timing chart when the light beam from the laser diode LD is first input to the optical sensor. LD...Semiconductor laser array LD1-LDm...Laser diode FS...Synchronization sensor PS...Phase synchronization circuit TC...Delay circuit ME...Memory SLY-8Lm...Shift register VC...・Video control circuit sub-scanning direction LD-electronic D

Claims (1)

[Claims] 1 Scanning an object with a plurality of light beams, and synchronizing the main scanning direction of the plurality of light beams based on the output of a photosensor that receives the light beams and is provided outside an image scanning area. In the recording device that uses the plurality of light beams, image information reading is performed in which image information corresponding to the plurality of light beams is read out using an image scanning clock corresponding to the light beam first received by the optical sensor among the plurality of light beams. A recording device characterized by being provided with means.