JPH01162073A - Synchronizing clock generating circuit - Google Patents

Abstract

PURPOSE:To shorten a synchronizing time and to reduce dispersion by executing the sampling of an input signal with the rising and falling of an original clock, obtaining two dividing clocks and causing a logical OR to be a synchronizing clock. CONSTITUTION:A first dividing circuit 6a is operated by the rising of an original clock CLK and a second dividing circuit 6b is operated by the falling of the original clock CLK. Accordingly, when the logical OR between first and second dividing clocks CL1 and CL2 is obtained by an OR gate 6c, a synchronizing clock CLS, which goes to be 'high' by the rising of the second dividing clock CL2 and goes to be 'low' by the falling of the first dividing clock CL1, can be obtained. A synchronizing time Td is not over 1/2Ts+alpha(<=1/2 of the period of the clock CLK) and the synchronizing time Td can be widely shortened. Thus, in a laser printer, the time dispersion goes to be small and a jitter can be decreased.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial application field (Figure 3) Prior art (Figure 4) Problems to be solved by the invention Means for solving the problems (Figure 1) Functional Embodiment (a) Description of one embodiment (Fig. 2) (b) Explanation of another embodiment Effects of the invention [Summary] Synchronization in which a source clock is synchronized with an input signal and frequency-divided to generate a synchronous clock Regarding clock generation circuits, the purpose of the synchronous clock generation circuit is to shorten the synchronization time and generate a synchronous clock with less variation.In a synchronous clock generation circuit that generates a frequency-divided clock of an original clock synchronized with an input signal as a synchronous clock,
a first frequency dividing circuit that synchronizes the rising edge of the original clock with the input signal to generate a first frequency-divided clock; and a second frequency-divided clock that synchronizes the falling edge of the original clock with the input signal. and an OR circuit that outputs the logical sum of the first and second divided clocks as a synchronization clock.

[Industrial Application Field] The present invention relates to a synchronous clock generation circuit that synchronizes an input signal with an original clock and divides the frequency to generate a synchronous clock.

Circuits that divide and generate clocks synchronized with input signals are widely used.

For example, in an optical scanning device used in a laser printer or the like, it is used to detect the start of scanning using light and generate a video clock synchronized with this.

FIG. 3 is an explanatory diagram of such an optical scanning device.

The optical scanning device includes a light source (laser light source) 1 and an optical scanning means 2, and the output light from the light source 1 is optically scanned by the optical scanning means 2, and is irradiated onto a photosensitive drum 3, which is an object to be scanned. This example shows an application to an electrophotographic printing apparatus, in which a charged photosensitive drum 3 is scanned and exposed, and after development, the image is transferred onto paper.

The optical scanning means 2 includes a cylinder lens 20, a polygon mirror 21, a spindle motor 22, an F-θ lens 23, a cylinder mirror 24, and a start detection mirror 25.

Output light from the light source 1 is focused by a cylinder lens 20, enters a polygon mirror 21 rotated by a spindle motor 22, is reflected, and enters an F-〇 lens 23. The scanning light from the F-theta lens 23 has a long optical path length and a cylinder mirror 24 for expanding the scanning width.
The light is reflected by the light beam and enters the photosensitive drum 3, which is a scanning surface.

On the other hand, a start detection mirror 25 that reflects light at the left end of the optical scanning width is provided between the F-θ lens 23 and the cylinder mirror 24, and the reflected light from the start detection mirror 25 is transmitted to a start detection photodetector. The light is received by a photodiode (photodiode) 4, and a scanning light detection circuit 5 generates a start detection signal BD based on the light reception signal.

This start detection signal I3D is input to the synchronous clock generation circuit 6, which generates a video clock VCL synchronized with the start detection signal BD, and uses it to control each section.

That is, as shown in FIG. 3(B), the photodetector 4 is located on the scanning plane (
The mirror 25 is arranged so as to detect the laser beam scanned from the left on the photosensitive drum 3) at the left end, and the paper area PP and the printing area PA are located after the position in the scanning direction.

Therefore, the start signal BD indicates the start of the - line scanning light, and in the printing apparatus, as shown in FIG. After the waiting time, the video signal VDO is outputted to the light source 1 in a manner corresponding to the print area PA.

Therefore, the accuracy of the writing start position is determined by the accuracy of the clock VCL with respect to the start signal BD.

In such a synchronous clock generation circuit, it is desired to output a synchronous clock with a short delay time with respect to an input signal (start signal BD).

[Conventional technology]

FIG. 4 is an explanatory diagram of the prior art.

The circuit shown in FIG. 4(A) uses a counter circuit 61, which includes a register 60 that stores the input signal BD at the timing of the original clock CLK, and a register 60 that is loaded with the output of the register 60 and counts the original clock CLK. counter 61
The divided output of the counter 61 is used as a synchronous clock CLS.
(VCL).

The frequency division is done here by sampling the original clock with a short period, so that the synchronized clock C is accurately synchronized.
This is to obtain LS.

On the other hand, the flip-flop 6 shown in FIG.
2 to 64 is used in the frequency dividing circuit, and the original clock C
Three flip-flops 62 to 64 that operate at the rising edge of LK are connected to form a quaternary counter.

This operation is performed by input signal BD as shown in FIG. 4(C).
is sampled at the rising edge of the original clock CLK and set in the flip-flop 62.
4 is operated using the original clock CLK to generate a synchronous clock CLS having a period Ts obtained by dividing the frequency by 1/4.

[Problem that the invention seeks to solve]

Incidentally, in such a synchronous clock generation circuit 6, the shorter the time Td from when the input signal BD is turned on until the synchronous clock CLS is output, the faster the clock CLK can be made (i.e., the speed of the laser printer can be increased). ), it is possible to perform synchronous operation, the variation is small, and the printing start position of each line can be controlled to be constant.

However, in the configuration shown in FIG. 4(A), the clock vs. data set-up time of the counter 61 and the output delay time are relatively long, and the synchronization time Td can be shortened only by TT.
There is a problem that this is difficult with L-level ICs.

On the other hand, in the configuration shown in FIG. 4(B), the counter 6
1 is not used, the clock-to-data set-up time and output delay time are faster than those in FIG. There were problems such as synchronization becoming impossible and variations becoming large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous clock generation circuit that can shorten synchronization time and generate a synchronous clock with little variation.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, 6a is a first frequency dividing circuit, which generates the first frequency divided clock CLI by synchronizing the rising edge of the original clock CLK with the input signal BD, and 6b is a second frequency dividing circuit, 6c is an OR circuit that synchronizes the fall of the original clock CLK with the input signal BD to generate the second divided clock CL2, and the first and 20th divided clocks CLI, C
The logical sum of L2 is output as the synchronous clock CLS.

[Effect]

In the present invention, as shown in FIG. 1(B), the original clock CL
Sample the input signal BD at the rise and fall of K,
Two frequency-divided clocks CLI and CL2 are obtained, and the logical sum thereof is used as the synchronization clock CLS.

Therefore, even if the input signal BD rises as shown in FIG.
Divided clock CI sampled at the earlier falling edge,
Since it turns on from the tip of 2, the synchronization time Td is 1 /
It can be shortened to about 2 T s + α, and this α is the original clock C
This is less than 1/2 of the period of LK.

Therefore, even if the original clock CLK is made faster, it can sufficiently catch up and synchronize.
It can be realized with an inexpensive TTL IG without using an expensive RC such as an UPLED COGIC element.

Further, variations are also reduced, and for example, in a laser printer, it contributes to stabilizing the printing start position and reduces jitter.

〔Example〕

(a) Description of one embodiment FIG. 2 is a detailed explanatory diagram of the present invention.

In FIG. 2(A), the same parts as those shown in FIGS. 1 and 4 are indicated by the same symbols. 6d is an inverter that inverts the original clock CLK, and 6e is an AND gate, which converts the original clock CLK into the first frequency dividing circuit 6.
The clocks inputted to the flip-flops 62 to 64 of a are flip-flops 65 to 67, which constitute a quaternary counter, and are connected in series to constitute the second frequency division circuit l116b.

The first frequency dividing circuit 6a operates on the rising edge of the original clock CLK, and the second frequency dividing circuit 6b operates on the falling edge of the original clock CLK, that is, the rising edge of the inverted original clock CLK.

Therefore, as shown in FIG. 2(B), when the input signal BD turns on after the rise of the original clock CLK and before the fall of the original clock CLK, first, at the rise of the inverted original clock CLK by the inverter 6d (the fall of the original clock CLK). , a flip-flop (hereinafter referred to as FF) 65 is set and outputs Q, which causes FF66 to operate at the rising edge of the inverted source clock CLK, divide the frequency by 1/2, and generate Q4 output, and further FF67 to output the inverted source clock CLK. It operates at the rising edge of clock n, and further divides the frequency by 1/2 to generate a second divided clock CL2.

On the other hand, in the first frequency dividing circuit 6a, the FF 62 is set at the rising edge of the original clock CLK after the input signal BD is turned on.
Q, generates an output, which causes FF63 to output the original clock C.
It operates on the rising edge of LK, divides the frequency by 172 and outputs Q2, and furthermore, FF64 operates on the rising edge of the original clock CLK.
The frequency is further divided by 1/2 to generate a first frequency divided clock CLI.

Therefore, the first and second frequency divided clocks CLI, C1,
When the OR gate 6c calculates the logical sum of 2, the synchronized clock CL becomes "high" at the rising edge of the second frequency-divided clock CL2 and becomes "low" at the falling edge of the first frequency-divided clock CLI.
S is obtained.

Moreover, when the input signal BD turns on after the fall of the original clock CLK but before the rise, the temporal operations of the first and second frequency dividing circuits are reversed, and the synchronized clock CLS is the same as that of the first frequency divided clock CLI. It becomes "high" at the rising edge, and becomes "low" at the falling edge of the second divided clock CL2.

In any case, the synchronization time Td is I / 2 T s
The synchronization time Td can be significantly shortened without exceeding +α (1/2 or less of the period of the clock CLK).

Therefore, in the laser printer, the time variation is small, and the distance from the beam detection position to the printing start position is the same for each scan, and jitter can be reduced.

Also, since it can be realized with TTL level IC, expensive EC
, Lrc, and can be realized at low cost.

(b) Description of other embodiments In the above embodiments, the case of frequency division by 1/4 was explained, but other frequency division ratios may be used, and the original clock pulse also needs to have a duty ratio of 50:50. Ha Naku, 60:4
0 etc. may be used.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

〔Effect of the invention〕

As described above, according to the present invention, the synchronization time can be shortened without using an expensive ECL element, and an inexpensive synchronization clock generation circuit capable of high-speed operation can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a detailed explanatory diagram of the present invention, Figure 3 is an explanatory diagram of the optical scanning device; FIG. 4 is an explanatory diagram of the prior art. In the figure, 6-synchronous clock generation circuit; 6a-first frequency divider circuit; 6b - second frequency divider circuit; 6cm - OR circuit.

Claims (1)

[Claims] In a synchronous clock generation circuit that generates a frequency-divided clock of an original clock synchronized with an input signal as a synchronous clock, a first frequency-divided clock is generated by synchronizing the rising edge of the original clock with the input signal. a first frequency dividing circuit (6a) that generates a second frequency divided clock by synchronizing the falling edge of the original clock with the input signal; A synchronous clock generation circuit comprising: an OR circuit (6c) that outputs the logical sum of the second frequency-divided clocks as a synchronous clock.