JPH03213010A - Clock generator - Google Patents

Abstract

PURPOSE:To output a clock pulse at a delay within a half clock pulse by applying the clock pulse of an opposite phase to each clock input of two-flip-flops, and validating only a flip-flop set when a control signal for pulse generation is started to use as a data input is supplied. CONSTITUTION:When a main clock pulse MCK of a positive phase is fed to a flip-flop 51 in a couple of D flip-flops 51, 52, a main clock pulse of a negative phase passing through an inverter 53 is fed to the flip-flop 52. Inhibit means 55, 60 are provided respectively to the flip-flops 51, 52 and the inhibit means 55, 60 are operated to validate the flip-flop 51 or 52 only set early to logical '1' to a control signal TRG commanding the start of pulse generation. Since the main block pulses MCK in opposite phase are delayed only by a half clock mutually, a synchronization clock signal CLK is obtained by the delay of a half clock at maximum by a trigger signal TRG is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock generator that can be applied to optical scanning devices such as laser beam printers. Concerning vessels.

``Prior Art J'' An optical scanning device such as a laser beam printer is generally constructed as shown in FIG. 5 or 6.

In the optical scanning device 10 shown in FIG. 5, an image signal (binary information corresponds to black and white image information) is supplied to the semiconductor laser 11 as its modulation signal.

The laser beam emitted from the semiconductor laser 11 passes through a collimating lens 12, an aperture 13, and a cylindrical lens 14, and is bent by a mirror 15. The bent laser beam further passes through an imaging lens 16 and is deflected by a polygon mirror or the like. The light is irradiated onto the vessel 17. The course of the laser beam deflected by the deflection 8!17 is deflected by a reflection mirror 18, and the deflected laser beam passes through a cylindrical lens 19 and forms an image on a photosensitive drum (scanned recording medium) 20.

Since the deflector 17 is rotating in one direction at a predetermined speed,
The laser beam formed on the photoreceptor drum 20 scans the photoreceptor drum 20 in one direction. As a result, an electrostatic latent image corresponding to the input image information is formed on the photosensitive drum 20.

In the example shown in FIG. 6, the laser beam deflected by the deflector 17 passes through the spherical lens 31 and the toroidal lens 32 and reaches the folding mirror 18.
The optical path is deflected to focus on the image.

Note that the optical scanning device 10 having such a configuration is
"Laser Beam Printer", Electronics, 1989
Since it is well known in ``April issue, P, 70-74'', further detailed explanation will be omitted.

Then, as shown in FIGS. 5 and 6, the laser beam emitted from the semiconductor laser 11 scans the photoreceptor drum 20 via the deflection 1117 and other optical systems. Before starting the process, the light reflected by the mirror 21 is guided to the beam detector 23 directly or via the toroidal lens 22 (example shown in FIG. 5).

A trigger signal is output from the beam detector 23 at the timing when the laser beam scans this mirror 21, and a printing clock signal is obtained in synchronization with this. The printing timing on the photosensitive drum 20 is determined based on this printing clock signal.

This is done in order to prevent variations (jitter) in the printing timing caused by the scanning of the laser light emitted from the semiconductor laser 11 for each scanning.

Here, when fO is a clock frequency corresponding to a pixel component necessary for printing, if the beam detector 23 is synchronized with the clock frequency fO, the printing timing will be shifted by one pixel at worst.

Therefore, if the beam detector 23 is synchronized using a synchronization clock (No. 8 (frequency is mfo) with m times the frequency), the deviation in printing timing can be suppressed to (1/m) pixels. .

The printing clock signal (frequency: fO) is obtained by dividing the synchronization clock No. 8 (frequency: mfO) by 1/m.

Here, to set the distance from the position of the beam detector 23 (specifically, the position of the mirror 21) to the point on the photoreceptor drum 20 where printing is started, a clock signal for printing (frequency: fO) is used. are using.

Therefore, the accuracy of distance setting is determined by the frequency fO of the printing clock signal, and there is a drawback that the accuracy of distance setting is worse than the accuracy of printing timing.

In order to improve the accuracy of printing timing, a synchronous circuit 40 as shown in FIG. 7 can be used as a circuit for obtaining a printing clock signal.

As will be explained with reference to FIGS. 7 and 8, in this synchronization circuit 40, the trigger signal T from the beam detector 23 is
The RS flip-flop 41 is set by R, and the n-bit shift registers 42a, 42b, . followed by n logic “0”
shift. Thereafter, this shift operation is repeated.

Note that the register output FOn of the final stage register 42n is fed back to the first stage register 42a via the inverter 43 and the AND circuit W844.

As a result, each shift register 42a, 42b,...4
Register output F00, FOl, FO output from 2n
2, --- and FOn are provided with a synchronization signal C.
This is examined by obtaining an output signal having a frequency component of (1/2 n ) of LK.

Moreover, register output FOO, FOI, FO2,...
, FOn each have a phase difference of one period of the synchronization clock signal CLK. Therefore, use any output signal to detect the beam! #23 to photosensitive drum 20
If the distance to the print start point is set in , the distance setting error at that time will be (1/2 n ) pixels, so the distance setting error to the print start point can be significantly improved compared to the conventional method.

By the way, the synchronization clock signal CLK mentioned above is actually generated after the trigger signal TR is obtained and then the reset signal R3 is generated.
It is desirable to be able to obtain it until T is obtained.

This clock signal CL is applied only from when the trigger signal TR is obtained until when the reset signal R5T is obtained.
This is because K may be used to drive a counter (not shown) or the like.

A clock generator 50 configured as shown in FIG. 9 is used, which generates a clock signal only for a certain period of time.

This clock generator 50 includes a D-type flip-flop 45
．． It is composed of an OR circuit 46 and an AND circuit 47.

Next, the operation will be explained with reference to the waveform diagram in FIG.

The reset signal R3T initializes the flip-flop 45, that is, sets the output Q to logic "O". Next, when the trigger signal TRG instructing the start of pulse generation comes,
This trigger (g TRG) is input to the D terminal of the flip-flop 45 via the NOR circuit 46.

As a result, the output Q is inverted to logic "1" at the next rising timing of the main clock pulse MCK. The output is fed back to the D terminal via the aforementioned OR circuit 46, and even if the trigger signal TRG disappears, the output Q remains at the logic "
1'' and continues to hold this state until the next reset signal R5T arrives.

Output Q and main clock pulse MCK are AND circuit 47
Since the main clock pulse MCK can be gated only during the period when the output Q is at a high level, this is eventually used as the synchronization clock signal CLK.

"Problems to be Solved by the Invention" As shown in FIG. 9, in the clock generator 50, depending on the phase relationship between the trigger signal TRG instructing the start of clock pulse generation and the main clock pulse MCK, the flip-flop output Q In the worst case, the setting of logic "1" will be delayed by one clock pulse.

In this case, the register output FO1 shown in FIG. 8 will also be delayed by one clock pulse in the worst case, making it impossible to improve the accuracy of the synchronization clock signal CLK.

Therefore, the present invention has been made in view of the above points, and an object of the present invention is to provide a clock generator that can obtain a synchronizing clock signal with a delay of only half a clock pulse in the worst case from the trigger signal TRG. There is.

"Means for Solving the Problem" In order to solve the above-mentioned problem, in the present invention, clock pulses of opposite phases are applied to each clock input of two flip-flops to instruct the start of pulse generation as a data input. When a #signal is applied to set one of the flip-flops, a prohibiting means is provided that can inhibit data input to the other flip-flop, and the set flip-flop will cause the set flip-flop to respond to the clock pulse. This device is characterized in that the clock pulse can be output with a delay of less than half a clock pulse.

``Function'' In the case of FIG. 1, the two flip-flops 51 and 52 have used up the main clock pulse MCK, which has opposite phases to each other, as their synchronization clock. Then, the inhibiting means 55 and 60 operate so that only the flip-flop 51 or 52 on the side that can be set to logic "1" quickly in response to the 1IIj signal (trigger signal) TRG instructing the start of pulse generation becomes effective. .

Since the main clock pulses MCK, which have opposite phases to each other, are delayed by only 1/2 clock pulse, the synchronizing clock signal CLK can be obtained with a delay of only 1/2 clock pulse in the worst case after the trigger signal TRG is obtained. I can do it.

Therefore, the accuracy is twice as high as before.

Embodiment Next, an example of a clock generator according to the present invention applied to the above-described synchronous circuit 40 will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention, which will be described with reference to the waveform diagram of FIG. 2. This example has a pair of D-type flip-flops 51 and 52.

When the first flip-flop 51 is supplied with the positive phase main clock pulse MCK, the second flip-flop 52 is supplied with the inverter 5.
The main clock pulse MCK of the opposite phase that has passed through 3 is supplied as the clock.

Each of these flip-flops 51 and 52 has first and second inhibiting means 55 for inhibiting its own operation.
．． The inhibiting means 55 and 60 have their inhibiting operations controlled by flip-flop outputs (FF outputs) Ql and Q2 obtained from the flip-flops 51 and 52 on the opposite side.

Therefore, the first inhibiting means 55 is constituted by the following logic circuit.

That is, this means that the second flip-flop 52 is OFF.
An inverter 56 that inverts the output Q2, and an AND circuit 57 to which this reverse phase output and the trigger signal TRG are supplied.
and this AND output and the first flip-flop 5
and an OR circuit 58 to which the 1OFF output Q1 is supplied. This OR output is D of the first flip-flop 51.
Supplied to the terminal.

The second inhibiting means 60 can also be configured in the same way, and the inverter 61
The first FF output Q1 and the trigger signal TRG inverted by
The AND circuit 62 that can supply the AND output and the second
and an OR circuit 1163 to which the FF output Q2 of is supplied, and the OR output is supplied to the D@ terminal of the second flip-flop 52.

Note that an AND circuit 64 is provided so that the main clock pulse MCK is AND gated by the first FF output Q1, and an AND circuit 65 is provided so that the main clock pulse MCK is AND gated by the second OFF output Q2. . Then, these AND outputs are logically summed by an OR circuit 66 to form the final output pulse (synchronization clock signal) CLK.

Its operation is as follows. This will be explained with reference to FIG.

First, the flip-flop 51.5 is reset by the reset signal R3T.
2 is initialized, that is, reset.

Next, a trigger signal TRG instructing the start of pulse generation
When input, this trigger signal TRG is simultaneously input to the D terminals of flip-flops 51 and 52 via inhibiting means 55 and 60, respectively.

Since the flip-flops 51 and 52 are supplied with the main clock pulses MCK and MCK having opposite phases to each other, the flip-flop 51 or 52 which rises first among the main clock pulses MCK and MCK outputs logic "1". is set to

Here, as shown in FIG. 2A, the flip-flop 5
Assume that it is set to 1. As a result, the FF output Q
1 is inverted to logic "1" (high level).

Since the FF output Q1 is also supplied to the inverter 61, the AND circuit 62 is turned off due to its function.
Input of the trigger signal TRG to the second flip-flop 52 is prohibited. Therefore, the FF output Q2 is logical "
The state of "o" is maintained.

On the other hand, since the FF output Ql is fed back to the D terminal of the first flip-flop 51 via the OR circuit 58, the FF output Q1 remains at logic "1" even if the trigger signal TRG is absent.
” continue to hold. This state continues until the reset signal RST is input again.

During the period when the FF output Q1 is logic "1", the AND circuit 64 is in the on state, so the main clock pulse MC
K itself is output as the synchronization clock I8 CLK.

Contrary to the above, if the second flip-flop 52 is set first by the trigger signal TRG, the second FF output Q2 becomes logic "1" as shown in FIG. 2B. becomes.

Then, the inhibiting means 55 is operated by this FF output Q2, and the trigger signal TR to the first flip-flop 51 is activated.
Prohibit input of G.

Therefore, the first FF output Q1 maintains the logic "0" state.

During the period when the second FF output Q2 is at logic "1", the main clock pulse M is sent via the AND circuit 65.
Since CK can be supplied to the OR circuit 66, the trigger signal T
During the period from when RG is input until the reset signal RST is input again, this main clock pulse is output as the synchronization clock signal CLK.

As mentioned above, the main clock pulses MCK1MCK, which are in opposite phase relation to each other, are delayed by only 1/2 clock pulse from each other, so in the worst case, the main clock pulses MCK1MCK are delayed by only 1/2 clock pulse after the trigger signal TRG is obtained. A clock signal CLK can be obtained. Therefore, its accuracy is twice as high as before.

Next, other examples of the present invention will be shown.

Figure 3 shows a flip-flop 51.5 without a reset function.
2 is used.

In this case, AND circuits 70 and 71 are added to each inhibiting means 55 and 60, and the output of the OR circuit 58 and 63 and the reset signal RST are ANDed here.

In this way, either the flip-flop 51 or 52 is fully set by the trigger signal TRG, and is reset by the reset signal 4g R3T.

Also, the reset in Figure 1 is the main clock pulse MCK.
Although this is a direct reset that is not related to the above, when configured as shown in FIG. 3, it becomes a reset that is synchronized with the main clock pulse MCK.

The third embodiment shown in FIG. 4 uses RS type flip-flops 51 and 52.

In this case, the inhibiting means 55.60 connected to the set terminals S1.32 are simplified and the AND circuits 81.60, respectively, are simplified.
It can be configured with only 82 and inverters 56 and 61.

The AND circuit 81 is supplied with the trigger signal TRG and the inverted output of the second FF output Q2, and the AND circuit 82 is supplied with the trigger signal TRG and the inverted output of the first FF output Q1.

Then, a reset signal R5T inverted by an inverter 85 is supplied to each reset terminal.

Even in this configuration, the flip-flop 51 or 52 that rises faster can be completely set, and when it is set, the inhibiting means 55 and 60 operate. Further, since the reset signal R3T can be used to complete the reset, the synchronization clock signal CLK can be obtained only for a predetermined period.

"Effects of the Invention" As described above, the clock generator according to the present invention can generate a clock signal with a delay of less than half a clock pulse in the worst case with respect to the control signal instructing the start of pulse generation. The accuracy of the clock signal can be improved with a relatively simple circuit configuration.

Therefore, as described above, it is extremely suitable for application to a synchronization circuit of an optical scanning device.

[Brief explanation of drawings]

FIG. 1 is a connection diagram of a clock generator according to the present invention, and FIG.
The figure is a waveform diagram for explaining its operation, Figures 3 and 4 are connection diagrams showing other embodiments of the invention, Figures 5 and 6 are configuration diagrams of the optical system of the Leb beam printer, Figure 7 is a connection diagram of the synchronous circuit used for this, Figure 8 is an explanation diagram of its operation, Figure 9 is a connection diagram of a conventional clock generator, and Figure 10 is a diagram of the connection of a conventional clock generator.
The figure is an explanatory diagram of the operation. 10 ・ 40 ・ 50 ・ 51.52 ・ 55.60 ・ ・Optical scanning device・Synchronization circuit・Clock generator・Free-chip flop・Inhibition means

Claims (1)

[Claims] (1) When clock pulses with opposite phases are applied to each clock input of two flip-flops, and a control signal instructing the start of pulse generation is applied as a data input, when one of the flip-flops is set, , has a prohibition means that prohibits data input to the other flip-flop, and outputs a clock pulse from the set flip-flop with a delay of less than half a clock pulse with respect to the above clock pulse. Features a clock generator.