JPH0580191B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image recording apparatus using a rotating polygon mirror as a light beam scanning means.

(Background of the Invention) One type of image recording device is a photosensitive roll-shaped recording device in which a light beam output from a light source is reflected by a rotating polygon mirror to form a scanning light beam, and the scanning light beam is modulated with a print signal. Some devices are configured to perform photosensitive recording by irradiating the medium.

FIG. 3 is a block diagram showing an example of such an image recording device. In Figure 3, 1 is, for example, He
-Ne laser light source. The output beam of the light source 1 is transmitted through shutter 2→mirror 3→pinhole 4→mirror 5→acoustooptic modulator.
modulator; hereinafter abbreviated as AOM) Lens 6 → AOM
7 → Neutral density
density; hereinafter abbreviated as ND) filter 8 → AOM lens 9 → beam expander (beam
expander (hereinafter abbreviated as BE) unit 11 → mirror 12 → pinhole 13 → cylindrical lens (hereinafter abbreviated as CL) 14 → CL1
The light enters the rotating polygon mirror 18 through an optical system consisting of 5→mirror 16→mirror 17, and is reflected as a scanning light beam. The scanning light beam reflected by the polygon mirror 18 is passed through a condenser lens 19 using an fθ lens and a CL
The light is applied to the photoreceptor 21 via the photoreceptor 20 . A mirror 22 is disposed near the scanning end of the photoreceptor 21,
The scanning light beam reflected by the mirror 22 is incident on a light receiving element 23 disposed substantially on the same surface as the photoreceptor 21 . Note that the light receiving element 23 outputs a horizontal synchronization signal. Further, a surface detection sensor 24 for detecting the reflective surface of the rotating polygon mirror 18 is arranged near the rotating polygon mirror 18.

Here, the shutter 2 is closed in a non-printing state and opened in a printing state. Also, the photoconductor 21 is not operated when the shutter 2 is open and the AOM 7 is turned off.
The light receiving element 23 is sensitive to the O-order light output, but does not respond to the O-order light output. That is, in order to obtain a horizontal synchronization signal from the light receiving element 23, it is necessary to turn on the AOM 7.

FIG. 4 is a timing chart for explaining the printing operation of the apparatus configured as described above. In FIG. 4, a indicates the output of the surface detection sensor 24, b indicates the output of the light receiving element 23, and c indicates the output of the light receiving element 23.
Shows the output of AOM7. Immediately after switching to printing operation, the AOM 7 is off, but it is turned on according to the first output of the surface detection sensor 23. As a result, a horizontal synchronizing signal is output from the light receiving element 23. Then, print data for modulation is added to the AOM 7 in accordance with the horizontal synchronization signal, and the photoreceptor 21 is exposed to the scanning light beam modulated by the print data.

By the way, in such a device, the light receiving element 23
The recording start position is controlled by starting counting of clock pulses by outputting a horizontal synchronizing signal from the recording head, and starting recording when the counted value reaches a predetermined number.

At this time, if the clock pulse to be counted and the dot clock are the same, a counting error of one clock corresponding to one dot will occur at maximum.
This will cause a maximum of one dot deviation (jitter) in the recorded results.

Therefore, in order to reduce such jitter, for example, Japanese Patent Application Laid-Open No. 51-46141 and Japanese Patent Publication No. 58-
As disclosed in Japanese Patent No. 32543, the dot clock is generated by generating a reference clock with a frequency n times that of the dot clock (n is a positive integer) and dividing the frequency of the reference clock by 1/n. It is proposed that it be generated.

(Problems to be Solved by the Invention) However, according to this method, when the frequency of the dot clock is increased in order to obtain a high-speed, high-resolution image recording device, the frequency of the reference clock also increases. That is, for example, if the frequency of the dot clock is 6 MHz and the frequency of the reference clock is set to 16 times the frequency of the dot clock, the frequency of the reference clock will be 96 MHz, and it will have to be configured as a high frequency circuit, which will increase the cost. It also becomes more expensive.

The present invention has been made in view of the above-mentioned problems, and its purpose is to reduce the frequency of the reference clock to 1/2 of that of the conventional one, simplify the circuit and reduce costs, and at the same time achieve higher speed. An object of the present invention is to realize an image recording device with high resolution.

(Means for Solving the Problems) The present invention, which solves the above problems, provides an image recording apparatus using a rotating polygon mirror as a light beam scanning means, which includes a reference clock generation circuit and an output of the reference clock generation circuit. an inversion circuit that inverts the level of a signal; a first frequency division circuit that divides the output clock of the reference clock generation circuit by a predetermined frequency; a second frequency divider circuit that divides the frequency at the same frequency division ratio as the frequency division ratio; a first gate circuit that controls passage of the output clock of the first frequency divider circuit; a second gate circuit that controls passage of the output clock; a photodetector that is disposed outside the recording area of the scanning light beam and detects the light beam;
The level of the reference clock or the inverted clock is detected at the timing when the scanning light is incident on the photodetector, and depending on whether the detected level is high or low, one of the output clocks of the first or second frequency dividing circuit is selected. a clock selection circuit that supplies a pass control signal to each of the first and second gate circuits so as to selectively pass the clock whose valid edge appears earlier; Second
The clock selectively output from the gate circuit is used as a dot clock for image recording.

(Function) According to the image recording device of the present invention, of the first dot clock related to the reference clock and the second dot clock related to the inverted signal of the reference clock, the clock that rises first after detection of the scanning light beam is selected. Any associated dot clock will be selectively output.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a main part of an embodiment of the present invention. In FIG. 1, 25 is a reference clock generation circuit which outputs a reference clock CLa. The reference clock CLa is a D-type flip-flop circuit 2.
6 and the first 1/8 frequency divider circuit 27, and the inverting clock CLb is applied directly to the D terminal of
After being inverted as , it is applied to the second 1/8 frequency divider circuit 29 . The first 1/8 frequency divider circuit 27 outputs a first dot clock DCLa, which is the frequency of the reference clock CLa divided by 1/8, and the second 1/8 frequency divider circuit 29 outputs an inverted clock CLb. The frequency of is 1/
A second dot clock DCLb whose frequency is divided by 8 is output. Reference numeral 30 denotes a monomulti circuit, which outputs a pulse signal P having a predetermined pulse width by applying the horizontal synchronizing signal HS output from the light receiving element 23. The pulse signal P is applied to the clock terminal of the D-type flip-flop circuit 26 and to the clear terminal of each of the 1/8 frequency divider circuits 27 and 29. Reference numeral 31 denotes a selection circuit, which is composed of AND gates 32, 33 and a NOR gate 34. To describe this configuration in detail, the output of the D-type flip-flop circuit 26 is applied as the selection signal SE ₁ to one input terminal of the AND gate 32, and the first 1/8 frequency divider circuit 27 is applied to the other input terminal.
The output signal DCLa of is added, and the AND gate 33
The output of the D-type flip-flop circuit 26 is applied as the selection signal SE ₂ to one input terminal of the , and the output signal DCLb of the second 1/8 frequency dividing circuit 29 is applied to the other input terminal of the NOR gate 34 . The output signal of AND gate 32 is applied to one input terminal, and the output signal of AND gate 33 is applied to the other input terminal.

The operation of the apparatus configured as described above will be explained using the timing chart shown in FIG. In FIG. 2, a indicates the reference clock CLa, and b
indicates the inverted clock CLb. C is a horizontal synchronizing signal HS, which is output when the reference clock CLb is at L level and the inverted clock CLb is at H level. d is a selection signal _SE1 , which corresponds to the "L" level of the reference clock CLa at the time when the horizontal synchronizing signal HS is applied. e indicates a pulse signal P outputted from the monomulti circuit 30 upon application of the horizontal synchronizing signal HS, and f indicates a dot clock outputted from the selection circuit 31. In this state, since the reference clock CLa rises after the horizontal synchronization signal HS is applied, the dot clock DCLa related to the reference clock CLa output from the first 1/8 divider circuit 27 is output. . on the other hand,
g is an inverted clock when the reference clock CLa is at H level.
Horizontal synchronization signal output when CLb is at L level
Shows HS. h is the selection signal _SE2 , which corresponds to the "H" level of the reference clock CLb at the time when the horizontal synchronizing signal HS is applied. i is the horizontal synchronization signal from the mono multi circuit 30
Indicates a pulse signal P output in synchronization with HS,
j indicates a dot clock output from the selection circuit 31. In this case, the horizontal synchronization signal HS
Since the inverted clock CLb rises after the addition of
DCLb will be output.

With this configuration, the horizontal synchronization signal
Timing control between HS and dot clocks DCLa and DCLb is essentially done by controlling the reference clock CLa by 1/2.
This can be done with the same accuracy as when the frequency is divided by 16. Therefore, for example, the dot clock DCLa,
If 6MHz is required as the frequency of DCLb, and 1/16 precision is required for timing control, the frequency of the reference clock CLa is
48MHz will suffice. As a result, the configuration can be simplified and costs can be increased compared to conventional circuits. Furthermore, if the circuit configuration has high frequency characteristics equivalent to that of the conventional circuit, the accuracy of timing control can be doubled.

Incidentally, in the above embodiment, an example using a 1/8 frequency divider circuit was shown, but it is sufficient to use one depending on timing control accuracy.

Further, the circuit configuration is not limited to the one shown in FIG. 1, as long as the dot clock related to the reference clock and the dot clock related to the inverted clock are selectively output.

Further, the recording medium is not limited to a photosensitive roll-like one, and may be, for example, a cut recording paper.

(Effects of the Invention) As explained above, according to the present invention, the frequency of the reference clock can be reduced to 1/2 compared to the conventional one, and the circuit can be simplified and cost reduced. An image recording device with high resolution can be realized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing essential parts of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a configuration diagram showing an example of a conventional image recording device. , FIG. 4 is an explanatory diagram of the operation of the apparatus shown in FIG. 3. 23... Light receiving element, 25... Reference clock generation circuit, 26... D-type flip-flop circuit, 2
7, 29... 1/8 frequency dividing circuit, 28... Inverting circuit,
31...Selection circuit.

Claims (1)

[Scope of Claims] 1. An image recording device using a rotating polygon mirror as a light beam scanning means, comprising: a reference clock generation circuit; an inversion circuit for inverting the level of an output signal of the reference clock generation circuit; and a reference clock generation circuit. a first frequency divider circuit that divides the output clock of the circuit at a predetermined frequency division ratio; and a second frequency divider circuit that divides the output clock of the inverting circuit at a frequency division ratio that is the same as the frequency division ratio of the first frequency divider circuit. a first gate circuit that controls passing of the output clock of the first frequency dividing circuit; and a second gate circuit that controls passing of the output clock of the second frequency dividing circuit; , a photodetector disposed outside the recording area of the scanning light beam and detecting the light beam; detecting the level of the reference clock or the inverted clock at the timing when the scanning light is incident on the photodetector; and detecting the level of the reference clock or the inverted clock; The first and second gates are configured to selectively pass the clock whose valid edge appears earlier among the output clocks of the first or second frequency divider circuit depending on whether the clock is high or low. Each of the circuits has a clock selection circuit for supplying a pass control signal, and the clock selectively output from the first or second gate circuit is used as a dot clock for image recording. An image recording device using a rotating polygon mirror.