JPH04316269A - Scanning beam synchronization controller - Google Patents

Abstract

PURPOSE:To improve the timing precision of a scanning beam with a simple constitution by generating reference signals, which are different in phase by 180 deg. and have the same frequency as a timing pulse, by a reference signal and using one of them as a timing clock pulse. CONSTITUTION:A reference oscillator 100 outputs a reference signal (a), and reference signal output generating circuits 101 and 104 generate reference signals (b) and (c) different in phase by 180 deg. by the reference signal (a). Reference signal output holding circuits 102 and 105 hold the levels of reference signals (b) and (c) by a synchronizing signal (d) of a photodetector 108, and comparing circuits 103 and 106 compare levels of reference signals (b) and (c) held by holding circuits 102 and 105 with levels (e) and F1 to output comparison signals (g) and (h). A clock selecting circuit 107 selects one of comparison signals (g) and (h) to output a timing clock pulse (i). Thus, the timing precision of the scanning beam is improved with the inexpensive constitution.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applicable to laser printers, laser facsimile machines, laser recording devices, laser processing devices, laser information reading devices, etc. The present invention relates to a scanning beam synchronization control device suitable for devices that perform processing, information reading, etc.

0002

2. Description of the Related Art Generally, in a laser beam printer, for example, the modulation timing of a scanning beam must be controlled with extremely high precision for each scan. In this case, it is common to place a photodetector on the optical path of the scanning beam and start modulating the scanning beam in synchronization with the synchronization signal of this photodetector. Since it is not possible to obtain sufficient synchronization accuracy with this method, various proposals have been made.

Conventionally, this type of scanning beam synchronization control device has been disclosed in Japanese Patent Application Laid-open No. 51-46141 and Japanese Patent Application Laid-open No. 51-46141.
As shown in Publication No. 89347, a highly stable reference oscillator such as a crystal oscillator is used, and the oscillation frequency is set to n times the frequency of the timing clock pulse for dot position setting necessary to form the printed dot pattern (n is It is configured to divide the frequency as an integer) in synchronization with the synchronization signal of the photodetector. In this case, the phase difference between the synchronization signal and the timing clock pulse is 1 of the period of the timing clock pulse.
/n or less.

[0004] Another conventional device is the one disclosed in Japanese Patent Application Laid-open No. 5
As shown in Japanese Patent Publication No. 6-126378, Japanese Patent Application Laid-Open No. 61-150567, and Japanese Patent Publication No. 62-26221, a plurality of pulses having the same period and whose phase is slightly shifted from the timing clock pulse are generated by a delay circuit or the like. For example, the synchronization accuracy is improved by selecting the earliest pulse as the timing clock pulse (Japanese Patent Publication No. 62-26221).

[0005]

[Problems to be Solved by the Invention] However, in the conventional devices disclosed in Japanese Patent Application Laid-open No. 51-46141 and Japanese Patent Application Laid-open No. 51-89347, a highly stable reference oscillator such as a crystal oscillator is used. The pulse frequency is 30MHz, and the tolerance for synchronization is 1/16.
(n=16), the reference oscillator is 480MH
There is a problem that a high frequency output of z is required, and therefore the configuration is complicated and expensive.

On the other hand, Japanese Patent Application Laid-open No. 126378/1983,
JP 61-150567, JP 62-262
The conventional device disclosed in Japanese Patent No. 21 does not divide the reference frequency, so the above problem can be solved. However, since synchronization accuracy is determined by the number of pulses used to select timing clock pulses, in order to improve synchronization accuracy, it is necessary to increase the number of delay circuits and improve the synchronization accuracy of the delay circuits. is complicated,
The problem is that it is expensive.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a scanning beam synchronization control device that can control the timing of a scanning beam with high accuracy using a simple and inexpensive configuration.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the first means is to provide a scanning beam synchronization control device that generates a timing clock pulse for determining the timing of a scanning beam, at the same frequency as the timing clock pulse. a reference oscillator that generates a reference signal of the reference oscillator; a pair of reference signal generation circuits that generate a reference signal that has a phase difference of 180 degrees with the reference signal of the reference oscillator and has the same frequency as the timing clock pulse; a photodetector that outputs a beam timing synchronization signal; a pair of holding circuits that respectively maintain the level of the reference signal of the pair of reference signal generation circuits using the synchronization signal of the photodetector; a pair of comparison circuits that each output a comparison signal according to the difference between the level of the reference signal and the reference signal of the holding circuit; and a selection circuit that selects the comparison signal of the pair of comparison circuits and outputs it as a timing clock pulse. and an output signal from the selection circuit is used as a timing clock pulse for setting the dot position of the scanning beam.

The second means is that the oscillation frequency from the reference oscillator is N times the pixel frequency (N is an integer of 2 or more),
The dot position setting timing clock pulse is characterized in that a signal selected by a clock selection circuit among signals obtained by frequency-dividing the output signal from the comparison circuit by N is used. The third means is that the oscillation frequency from the reference oscillator is N times the pixel frequency (N is an integer of 2 or more), and the output of the comparison circuit is the pixel frequency as the timing clock pulse for setting the dot position. The present invention is characterized in that a signal obtained by dividing the frequency of the signal selected by the selection circuit by N is used.

The fourth means is characterized in that the reference signal generation circuit outputs a triangular wave signal or a sine wave signal as the reference signal.

[0011]

[Operation] In the first means, with the above configuration, a reference signal having the same frequency as the timing clock pulse is generated by the reference oscillator, and a pair of reference signals having a phase difference of 180° and the same frequency as the timing clock pulse are generated by the reference oscillator. is generated, and a pair of comparison signals are generated based on the difference between the level of this reference signal and the level of the reference signal when the photodetector detects the synchronization signal, one of which is selected as the timing clock pulse. Therefore, when improving the synchronization accuracy of the modulation timing of the scanning beam, it is easy and simple because the frequency of the reference oscillator is not divided or multiple pulses are not generated for selecting the timing clock pulse as in the conventional example. The timing of the scanning beam can be controlled with high precision using an inexpensive configuration.

In the second and third means, a reference oscillator generates a signal with a frequency N times that of the timing clock pulse, and this reference signal generates a pair of reference signals having a phase difference of 180°. A pair of comparison signals is generated by the difference between the level and the level of the reference signal at the time of detection of the synchronization signal of the photodetector, and one of the comparison signals is selected.
/N to generate a timing clock pulse. Therefore, since timing clock pulses with the same duty ratio can be generated, it is possible to simplify the configuration of the subsequent control circuit and scanning beam modulation circuit. , the timing of the scanning beam can be controlled with high precision with a simple and inexpensive configuration.

According to the fourth means, since a triangular wave signal or a sine wave signal is generated as the reference signal, the reference signal generating circuit does not become expensive or complicated.

[0014]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 is a block diagram showing an embodiment of a scanning beam synchronization control device according to the present invention, FIGS. 2 and 3 are timing charts showing main signals of the scanning beam synchronization control device of FIG. 1, and FIG. FIG. 5 is a circuit diagram showing a detailed configuration of the clock selection circuit of FIG. 1. FIG. 5 is a timing chart showing main signals of the clock selection circuit of FIG.

In FIG. 1, a reference oscillator 100 outputs a reference signal a having the same frequency f as a timing clock pulse i for starting the modulation timing of a laser beam printer, etc.
4 respectively generate reference signals b and c of the same frequency f, such as a triangular wave or a sine wave, whose phases are shifted by 180° from the reference signal a. The photodetector 108 is disposed, for example, on the optical path of a laser beam scanned by a rotating polygon mirror, and outputs a scanning timing synchronization signal d. In this case, the timing clock pulse i must be output at the rising edge of the synchronization signal d, for example.

The reference signal output holding circuits 102 and 105 respectively hold the levels of the reference signals b and c from the reference signal output generation circuits 101 and 104 at the rising edge of the synchronizing signal d, respectively, and the comparison circuits 103 and 106 respectively The levels of the reference signals b and c from the reference signal output generation circuits 101 and 104 are compared with the levels e and F1 of the reference signals b and c held by the reference signal output holding circuits 102 and 105, and the comparison signals g and h are Output. The clock selection circuit 107 is
Immediately after the synchronization signal d is generated, a high level or one of the comparison signals g and h that is at a high level is selected and outputted as a timing clock pulse i.

Next, the detailed operation of the above embodiment will be explained with reference to FIGS. 2 and 3. The reference oscillator 100 outputs a reference signal a having the same frequency f as the pixel period (1/f) of a recorded image in, for example, a laser beam printer, and the reference signal output generation circuits 101 and 104 each output a reference signal a using this reference signal a. For example, triangular wave signals b and c having the same frequency f and having a phase shift of 180° are output as reference signals.

When the scanning beam passes over the light receiving surface of the photodetector 108, the photodetector 108 outputs a synchronization signal d that becomes high level while the scanning beam passes, and the reference signal output holding circuits 102 and 105 Level e of the triangular wave signals b and c from the reference signal output generation circuits 101 and 104, respectively;
F1 is held at the rising edge of the synchronization signal d, for example. The comparison circuits 103 and 106 respectively compare the levels of the triangular wave signals b and c from the reference signal output generation circuits 101 and 104 and the levels e and F1 of the triangular wave signals b and c held by the reference signal output holding circuits 102 and 105, respectively. Compare and compare signal g
, h.

As shown in detail in FIG. 3, the triangular wave signals b, c and the synchronization signal d are not synchronized at all, but the comparison signals g and h are inverted signals synchronized with the synchronization signal d. Therefore, the clock selection circuit 107 selects the comparison signals g and h that are at a high level or at a high level immediately after the synchronization signal d is generated.
, and outputs it as the timing clock pulse i.

Next, the configuration and operation of the clock selection circuit 107 will be explained with reference to FIGS. 4 and 5. Note that this clock selection circuit 107 is configured to select one of the comparison signals g and h that are at a high level immediately after the synchronization signal d is generated. In FIG. 4, comparison signals g and h are input to one input terminal of AND circuits 601 and 604, respectively, and input terminals of one of AND circuits 603 and 606, and a synchronization signal d is input to one input terminal of AND circuits 601 and 604. One-shot timer IC (integrated circuit) 602, 60 through
Input to each clear terminal of 5.

The output terminals of the AND circuits 601 and 604 are respectively connected to the input terminals A1 and A2 of the one-shot timer ICs 602 and 605.
Inverting output terminals Q1 and Q2 of C602 and C605 are respectively connected to the other input terminals of AND circuits 604 and 601. One-shot timer IC602, 605
Time constant circuits (R1, C1), (R2,
C2) is connected, and each non-inverting output terminal Q1, Q2 is connected to the other input terminal of AND circuits 603, 606, respectively. Each output terminal (signal j, k) of the AND circuits 603 and 606 is connected to each input terminal of an OR circuit 607, and a timing clock pulse i is output from the output terminal of the OR circuit 607.

Next, the operation of this clock selection circuit 107 will be explained with reference to FIG. Synchronous signal d is inverter 6
00 to each clear terminal of one-shot timer IC602, 605, one-shot timer IC6
02 and 605 are cleared for a predetermined time from the rise of the synchronizing signal d, and the output signals of the inverting terminals Q1 and Q2 become high level (the non-inverting terminals Q1 and Q2 are low level), and therefore the gates of the AND circuits 601 and 604 opens.

In the circuits 601 to 603 in the upper stage of the figure, the output signal of the AND gate 601 goes high at the rise of the comparison signal g, and the non-inverting terminal Q1 of the one-shot timer IC 602 goes high. In addition, the time constant circuit (R1, C1) of the one-shot timer IC602, 605,
(R2, C2) is composed of a time constant that is sufficiently longer than the period of the synchronization signal d. Therefore, AND gate 603
The gate of 603 and O is opened and the comparison signal g is output to the AND gate 603 and O.
It is output via R gate 607.

On the other hand, in the lower circuits 604 to 606 in the figure, the output signal of the AND gate 601 becomes high level at the rise of the comparison signal g, and the one-shot timer IC 60
When the inverting terminal Q1 of 2 becomes low level, the AND circuit 6
Gate 04 closes. Therefore, regardless of the level of the comparison signal h, the non-inverting terminal Q2 of the one-shot timer IC 605 remains at low level, so the AND gate 606 is closed, and therefore the comparison signal h
is not selected. Also, since the upper circuits 601 to 603 and the lower circuits 604 to 606 are the same circuit, if the comparison signal g falls and the comparison signal h rises immediately after the synchronization signal d is generated, the comparison signal h is selected. be done.

Therefore, according to the above embodiment, when improving the synchronization accuracy of the modulation timing of the scanning beam, the frequency f of the reference oscillator 100 is not divided as in the conventional example, and the timing clock pulse i is selected. Since multiple pulses are not generated for this purpose, the modulation timing of the scanning beam can be controlled with high accuracy using a simple and inexpensive configuration. Further, in this embodiment, since triangular wave signals and sine waves are output as the reference signals b and c, the reference signal output generation circuits 101 and 104 are not complicated or expensive.

Next, a second embodiment will be described with reference to FIGS. 6 and 7. FIG. 6 is a block diagram showing a second embodiment of the scanning beam synchronization control device according to the present invention, and FIG.
3 is a timing chart showing main signals of the scanning beam synchronization control device of FIG. In the first embodiment, the levels of the reference signals b and c from the reference signal output generation circuits 101 and 104 are compared with the levels e and F1 of the reference signals b and c held by the reference signal output holding circuits 102 and 105. Since the comparison signals g and h, that is, the timing clock pulse i, are generated, the duty ratio of the timing clock pulse i differs for each scan, but in this embodiment, the timing clock pulse J with the same duty ratio is generated. It is composed of

In FIG. 6, the reference oscillator 300 has a frequency (2) that is twice the timing clock pulse J (frequency f).
・Output the reference signal A of f) and use the reference signal output generation circuit 4
01 and 404 each have a phase of 18 due to the reference signal A.
Frequencies such as triangular waves and sine waves that differ by 0° (2
・Generate reference signals B and C of f). The photodetector 408 is disposed on the optical path of a laser beam scanned by a rotating polygon mirror in, for example, a laser beam printer, and outputs a scanning timing synchronization signal D. In this case, the timing clock pulse J must be output at the rising edge of the synchronization signal D, for example.

The reference signal output holding circuits 402 and 405 respectively hold the levels of the reference signals B and C from the reference signal output generation circuits 401 and 404, for example, at the rising edge of the synchronizing signal D, and the comparison circuits 403 and 406 respectively The levels of the reference signals B and C from the reference signal output generation circuits 401 and 404 are compared with the levels E and F2 of the reference signals B and C held by the reference signal output holding circuits 402 and 405, and the comparison is made according to the level difference. Outputs signals G and H. Similar to the clock selection circuit 107 described above, the clock selection circuit 407 selects a high level or one of the comparison signals G and H (signal I) that is at a high level immediately after the generation of the synchronization signal D, and
A frequency divider 409 divides the frequency of this comparison signal I into 1/2 and outputs a timing clock pulse J having a frequency f.

Next, the detailed operation of the above embodiment will be explained with reference to FIG. The reference oscillator 400 outputs a reference signal A having twice the frequency (2·f) of the pixels of a recorded image in, for example, a laser beam printer, and the reference signal output generation circuits 401 and 404 each use this reference signal A for reference. The same frequency (2・f
) triangular wave signals B and C are output.

When the scanning beam passes over the light receiving surface of the photodetector 408, the photodetector 408 outputs a synchronization signal D that becomes high level while the scanning beam passes, and the reference signal output holding circuits 402 and 405 The levels of the triangular wave signals B and C from the reference signal output generation circuits 401 and 404 are held at the rising edge of the synchronization signal D, respectively. Comparison circuits 403, 4
06 are reference signal output generation circuits 401 and 404, respectively.
The levels of the triangular wave signals B and C from the reference signal output holding circuits 402 and 405 are compared with the levels E and F2 of the triangular wave signals B and C held by the reference signal output holding circuits 402 and 405, and the reference signal output generation circuit 401
, 404 outputs comparison signals G and H that are at a high level while the triangular wave signals B and C of the signals B and C are at a high level. One of the comparison signals G and H is selected by the clock selection circuit 407, and the N frequency divider 409 divides the frequency (2·f) of this selection signal I by 1/
2 and outputs a timing clock pulse J of frequency f.

Therefore, according to the above embodiment, the reference oscillator 400 generates the timing clock pulse J (frequency f).
A reference signal A with a frequency (N f) that is N times as large as 1 is output, and an N frequency divider 409 divides the selection signal I by 1/N, thereby generating a timing clock pulse J with the same duty ratio. Therefore, the configurations of the subsequent control circuit and scanning beam modulation circuit can be simplified. Note that the reference oscillator 400 and the N frequency divider 409 of this embodiment are used to generate timing clock pulses J having the same duty ratio, and have no relation to synchronization accuracy, so they have a simple and inexpensive configuration. The modulation timing of the scanning beam can be controlled with high precision. Also, in this embodiment, triangular wave signals and sine signals are output as the reference signals B and C, so
The reference signal output generation circuits 401 and 404 do not need to be complicated or expensive.

[0032]

As described above, according to the invention as set forth in claim 1, the timing of the scanning beam can be controlled with high accuracy with a simple and inexpensive configuration. According to the inventions recited in claims 2 and 3, timing clock pulses having the same duty ratio can be generated, and therefore, the configurations of the control circuit and the scanning beam modulation circuit in the subsequent stage can be simplified. . Further, since the reference oscillator and the frequency divider have no relation to synchronization accuracy, the timing of the scanning beam can be controlled with high precision with a simple and inexpensive configuration. In the fourth aspect of the invention, the reference signal generation circuits according to the first, second, and third aspects output triangular wave signals or sine wave signals as reference signals, so that the reference signal generation circuits do not become expensive or complicated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a scanning beam synchronization control device according to the present invention.

FIG. 2 is a timing chart showing main signals of the scanning beam synchronization control device in FIG. 1;

FIG. 3 is a timing chart showing main signals of the scanning beam synchronization control device of FIG. 1;

FIG. 4 is a circuit diagram showing a detailed configuration of the clock selection circuit of FIG. 1;

FIG. 5 is a timing chart showing main signals of the clock selection circuit of FIG. 3;

FIG. 6 is a block diagram showing a second embodiment of a scanning beam synchronization control device according to the present invention.

FIG. 7 is a timing chart showing main signals of the scanning beam synchronization control device of FIG. 6;

[Explanation of symbols]

100, 400 Reference oscillator 101, 104, 401, 404 Reference signal output generation circuit 102, 105, 402, 405 Reference signal output holding circuit 103, 106, 403, 406 Comparison circuit 108,
408 Photodetector 107, 407 Clock selection circuit 409 N frequency divider

Claims (4)

[Claims] 1. A scanning beam synchronization control device that generates a timing clock pulse for determining the timing of a scanning beam, comprising: a reference oscillator that generates a reference signal having the same frequency as the timing clock pulse; and a reference signal of the reference oscillator. a pair of reference signal generation circuits that generate reference signals having a phase difference of 180° and the same frequency as the timing clock pulse; a photodetector that detects the scanning beam and outputs a timing synchronization signal of the scanning beam; a pair of holding circuits that respectively hold the level of the reference signal of the reference signal generation circuit with the synchronization signal of the photodetector; a pair of comparison circuits that output comparison signals respectively, and a selection circuit that selects the comparison signals of the pair of comparison circuits and outputs them as timing clock pulses; A scanning beam synchronization control device characterized by using timing clock pulses for position setting. 2. The oscillation frequency from the reference oscillator is N times the pixel frequency (N is an integer of 2 or more), and the output signal from the comparison circuit is used as the timing clock pulse for setting the dot position by N times the pixel frequency. 2. The scanning beam period control device according to claim 1, wherein a signal selected by a clock selection circuit from among the rotated signals is used. 3. The oscillation frequency from the reference oscillator is N times the pixel frequency (N is an integer of 2 or more), and the output of the comparison circuit is N times the pixel frequency as the timing clock pulse for setting the dot position. 2. The scanning beam period control device according to claim 1, wherein a signal obtained by dividing the frequency of the signal selected by the selection circuit by N is used. 4. The scanning beam synchronization control device according to claim 1, wherein the reference signal generation circuit outputs a triangular wave signal or a sine wave signal as the reference signal.