JP2526201B2 - Recording controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a recording control device for outputting image data to a printer section.

[Prior Art] In the case of a printer in which the printer unit and the control unit are independently separated,
The pixel clock signal is generated in the printer unit, and the horizontal synchronizing signal and the pixel clock signal are sent to the control unit. The control unit uses the horizontal synchronizing signal as the start signal of the image signal transmission, and the image signal is sent to the printer unit in synchronization with the pixel clock. I was sending it out. However, if such a method is adopted, when the cable between the printer unit and the control unit is long, the phase delay of the image signal sent to the pixel clock of the printer unit becomes large, and the image signal received by the printer unit becomes large. However, there is a problem in that the image is out of sync with the pixel clock and the data is lost.

[Object] In view of the above-mentioned drawbacks of the conventional example, an object of the present invention is to provide a recording control device capable of stable image recording without data loss by synchronizing an image signal with a pixel clock signal.

[Means for Solving the Problems] In order to achieve the above object, the recording control apparatus of the present invention has the following configuration. That is, a recording control device that outputs image data to a printer unit, a memory that stores the image data, an input unit that inputs a pixel clock signal that is output from the printer unit, and image data that is output from the memory. An address counter that counts a pixel clock signal input by the input unit to generate an address signal to be read; a pixel clock signal output unit that outputs the pixel clock signal input by the input unit to the printer unit; Image data sending means for sending the image data synchronized with the pixel clock signal to the printer section.

[Operation] In the above configuration, the pixel clock signal output from the printer unit is input, the input pixel clock signal is counted by the address counter, and the image data is read from the memory storing the image data, The pixel clock signal input by the input unit is output to the printer unit, and the image data synchronized with the pixel clock signal is sent to the printer unit.

[Embodiment] FIG. 1 is a diagram for explaining an entire recording apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 100 is a control section for controlling the entire apparatus, 200 is a printer section for recording an image by a laser beam, 3 is a paper size detector for detecting the size of a sheet to be recorded, and 2 is an input section of the printer section. , S1 is a horizontal sync signal, S3 and S4 are pixel clock signals, S2
Is an image signal from the latch 11, and these will be described in detail with reference to FIGS.

The operation of the printer unit 200 shown in FIG.
The image signal 24 from 2 is input to the acousto-optic modulator (optical modulator) 13 through the driver 27, and is transmitted to the optical modulator.
Reference numeral 13 modulates a laser beam 23 emitted from a laser oscillator 22, the modulated laser beam scans the photosensitive drum 20 in the direction of the arrow by a rotary polygon mirror 21, and the photosensitive lens 20 by an imaging lens 25. The image is formed on the top. When the laser beam 23 reaches the left end of the photosensitive drum 20, it is reflected by the reflecting mirror 26, detected by the photodetector 5, and the detection signal S7 is input to the printer input section 2.

FIG. 2 is a diagram showing the relationship between the printer input unit 2 and the control unit 100, and those common to FIG. 1 use the same symbols.
Reference numeral 1 is a part of the control unit 100, and 4 is a counter for counting a count value according to the paper size. Reference numeral 6 is a pixel clock oscillator of the printer unit, and the output clock is counted by the counter 4, and the output of the counter 4 is input to the horizontal synchronizing signal generating circuit 7 so as to generate the horizontal synchronizing signal.
Reference numeral 9 is an address counter, and 10 is an image memory into which an image signal is input. The image memory is composed of, for example, a random access memory (RAM), and the image signal is read in synchronization with the pixel clock signal S4 which is an output signal of the address counter 9 and the pixel clock oscillator 6. .

FIG. 3 shows a pixel clock oscillator 6, a counter 4, a horizontal synchronizing signal generating circuit 7, an address counter 9, and an image memory 10.
FIG. 4 is a diagram for explaining the relationship of the above in more detail, and FIG. 4 is a diagram showing the timing chart thereof. Now, the paper size detector 3 is outputting the currently selected paper size to the counter 4, and when the photodetector 5 detects the laser beam 23, the detection signal S7 is input as a load pulse for the counter 4, and the counter 4 is supplied to the counter 4. The value corresponding to the paper size is preset. Thus, the output signal 302 of the zero detection NOR circuit 301 becomes LOW level (Fig. 4 T ₁ timing), the counter 4 is no longer reset state, the pixel clock signal S4
The countdown is started by the falling edge of. After the countdown is started, when the count corresponding to the paper size is counted, the output signal 302 of the zero detection NOR circuit 301 becomes high level again (timing of T ₂ in FIG. 4).
2 is input to the horizontal synchronizing signal generating circuit 7 and a horizontal synchronizing signal S1 having a predetermined pulse width is generated. Here, as the horizontal synchronizing signal generation circuit 7, a simple one-shot circuit triggered by rising is used.

On the other hand, the control unit 100 writes an image signal in advance in a built-in image memory 10 by a method (not shown) so that the data can be read according to the address signal from the address counter 9. The address counter 9 outputs the flip-flop 303 and the address of one line.
-2 and a counter 9-1 which outputs a scanning line address, and a flip-flop when the horizontal synchronizing signal S1 is output.
The output 305 of the 303 HIGH level and in summer (FIG. 4 T ₂ timing), the counter 9-2 starts counting from 0, performs a counting by the fall of the pixel clock signal S4, together with the counter 9-1, image Specify the address of memory 10.
On the other hand, the counter 9-1 receives the carry signal 30 of the counter 9-2.
Every time 4 is output (timing T _{3 in} FIG. 4), the count is incremented by 1, and the outputs Y _{0 to} Ym output the address of the scanning line.

CT _{0 to} CTn in FIG. 4 indicate the output state of the address counter 9, where CT ₀ is the timing when the 0th address of the image memory 10 is read, CT ₁ is the 1st address of the image memory 10, and CTn is the nth address. It represents the timing to be given. Latch 11
Are latched by the rising edge of the pixel clock signal S4, and the output S2 of the latch 11 has a timing waveform as shown in FIG.
Here, (n) indicates the data at the memory address n. This output
S2 is input to the latch 12 of the printer unit input unit 2,
The latch 12 is designed to be latched by the trailing edge of the pixel clock signal S4 in consideration of the timing delay. The fourth timing diagram of the image signal 24 output from the latch 12
Shown in the figure.

Counter 9-2 Kiyarii signal 304 when the beam scanning of one line from a counter corresponding to the number of data of one line is completed is output (Fig. 4 T ₃ timing), Kiyarii signal 304 inverter circuit 306 Through
Is input to Purisetsuto terminal of flip-flop 303, the output 305 of the flip-flop 303 becomes the LOW level (Fig. 4 T ₃ time), the counter 9-2 is cleared, do not operate until the re-input horizontal synchronizing signal S1, 0 Will remain. The counter 9-1 is counted up by the carry signal 304 and outputs the next scanning line address by Y _{0 to} Ym. For example, when the maximum number of data in one line is 4096, the output of the counter 9-2 is Q _{0 to} Q ₁₁ , which takes a hexadecimal value of ₀ to FFF (decimal value of 0 to 4095).
The outputs Y _{0 to} Ym of -1 are in the thousands of hexadecimal numbers, that is, the image memory 10
It shows more than 13th bit of the address.

When the beam is detected again by the photodetector 5 at the start of the next line scanning after the end of one line scanning, the counter 4 is loaded with the data corresponding to the paper size from the paper size detector 3 (T ₄ timing in FIG. 4). ), The same operation as described above is performed. The difference from the above operation is that the output Yo of the counter 9-1 is 1, so that the output of the address counter 9 starts from, for example, address 1000 (hexadecimal number),
Content from address 1000, such as CT1000 and CT1001, is sequentially output from the image memory 10.

The counter 4 in the above embodiment does not have to be a down counter, and may be an up counter or a combination of an up counter and a comparator. Further, the image memory 10 and the address counter 9 which the control unit 100 has are described for the purpose of explaining the interface. The digital image is synchronized with the horizontal synchronizing signal and the pixel clock signal like a TV camera or a CCD sensor. Any device that outputs a signal may be used.

In this embodiment, the latch 11 is the pixel clock signal S
It is said that the S3 rising edge and the latch 12 are latched at the falling edge, but the invention is not limited to this.
Any of 12 may be latched at the falling edge or the rising edge of the pixel clock signals S2, S4.

As described above, the configuration is such that the synchronizing signal for reading the image signal is sent from the printer unit to the control unit, and the image signal and the pixel clock used for synchronizing the image signal are sent from the control unit to the printer unit. Therefore, the pixel clock and the image signal can be synchronized, and there is an effect that stable image recording can be performed without data loss.

[Effects of the Invention] As described above, according to the present invention, a recording control device for outputting image data to a printer unit, in which a pixel clock signal output from the printer unit is input, and the pixel clock signal is used An address signal for reading the image data is generated, the image data is read from the memory, the pixel clock signal is output to the printer unit, and the image data synchronized with the pixel clock signal is transmitted to the printer unit. Therefore, there is an effect that it is possible to prevent the image disturbance and the image data loss due to the out-of-synchronization in the printer unit without providing the recording control device with the oscillation source for generating the pixel clock signal.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention, FIG. 2 is a relational diagram of a printer input unit and a control unit, and FIG. 3 is a circuit showing a relation of a horizontal synchronizing signal generating circuit, a counter address and an image memory. FIG. 4 and FIG. 4 are timing charts showing the timing of each part of FIG. Here, 1 ... part of control part, 2 ... printer part input part, 3 ... paper size detector, 4 ... counter, 5 ... photodetector, 6 ... pixel clock oscillator, 7 ... horizontal Sync signal generation circuit, 9 ... Address counter, 10 ... Image memory, 13 ... Optical modulator, 301 ... Zero circuit for zero detection, 303 ... Flip-flop, S1 ... Horizontal sync signal, S
3, S4 ... Pixel clock signal.

Claims (1)

(57) [Claims] 1. A recording control device for outputting image data to a printer unit, comprising: a memory for storing the image data; an input unit for inputting a pixel clock signal output from the printer unit; An address counter that counts a pixel clock signal input by the input unit to generate an address signal for reading image data, and a pixel clock signal output that outputs the pixel clock signal input by the input unit to the printer unit A recording control device comprising: a means for transmitting image data synchronized with the pixel clock signal to the printer section.