JPS60747A - Resin molded ic package - Google Patents
Resin molded ic packageInfo
- Publication number
- JPS60747A JPS60747A JP58107687A JP10768783A JPS60747A JP S60747 A JPS60747 A JP S60747A JP 58107687 A JP58107687 A JP 58107687A JP 10768783 A JP10768783 A JP 10768783A JP S60747 A JPS60747 A JP S60747A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead frame
- die
- resin
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はレジンモールドＩＣパッケージに係り、特には
んだディップ面付実装用に好適なレジンモールドＩＣパ
ッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a resin molded IC package, and particularly to a resin molded IC package suitable for solder dip surface mounting.
第１図は従来のレジンモールドＩＣパンケージの断面図
を示し、１はモールドレジン部、２はＩＣチップ、５は
グイリードフ１／−ム、４はボンディングワイヤ５を介
してＩＣチップ２に接続するリードである。前記ＩＣチ
ップ２とダイリードフレーム５とは、剛性の大きいＡｕ
−Ｓ ｉ。FIG. 1 shows a cross-sectional view of a conventional resin molded IC pancase, in which 1 is a mold resin part, 2 is an IC chip, 5 is a guide dome 1/-, and 4 is a lead connected to the IC chip 2 via a bonding wire 5. It is. The IC chip 2 and die lead frame 5 are made of highly rigid Au.
-Si.
やＡｇペーストでなるダイボンディング部材６によって
接着されている。またＩｃチップ２底面のダイリードフ
レーム３への接着面積は、該ＩＣチップ２の底面積全域
となっている。They are bonded together using a die bonding member 6 made of silver or Ag paste. Further, the adhesive area of the bottom surface of the IC chip 2 to the die lead frame 3 is the entire bottom surface area of the IC chip 2.
ところで、前記の１７ジンモールドＩＣパツケージをは
んだディップ面付実装法に適用した場合、即チレジンモ
ールドＩＣパッケージを、面付部品と共に回路基板に接
着剤で仮固定してはんだ浴にジャブ漬した場合、はんだ
の熱衝撃によりパッケージ内部に大きな応力が加わるこ
とになる。By the way, when the above-mentioned No. 17 resin molded IC package is applied to the solder dip surface mounting method, the resin molded IC package is temporarily fixed to the circuit board together with surface-mounted components with adhesive and then dipped in a solder bath. , large stress is applied inside the package due to the thermal shock of the solder.
しかし、従来のレジンモールドＩＣパッケージにおいて
は、前述したようにＩＣチップ２とダイリードフレーム
３とを剛性の大きいダイボンディング部材６により接着
しているため、ダィリードフレーム６の熱膨張による歪
がＩＣチップ２、に変形応力を発すさせ、該ＩＣチップ
２が図示のようにダイリードフレーム３と共に重ね板の
如く変形してしまう。However, in the conventional resin molded IC package, as described above, the IC chip 2 and the die lead frame 3 are bonded together by the die bonding member 6 having high rigidity, so that distortion due to thermal expansion of the die lead frame 6 is caused. A deforming stress is generated in the IC chip 2, and the IC chip 2 deforms like a stacked plate together with the die lead frame 3 as shown in the figure.
第２図はＩＣ’チップ面に働く応力と、ＩＣチップ表面
とモールドし・ジン部との界面剥離率の関係を表わした
グラフ図を示し、ＩＣチップ２に働く応力の大きさにζ
王ぽ比例してＩＣチップ２表面のモールドレジン部１と
の剥離が増すと。Figure 2 is a graph showing the relationship between the stress acting on the IC' chip surface and the rate of interfacial peeling between the IC chip surface and the mold/jin part.
If the peeling from the mold resin part 1 on the surface of the IC chip 2 increases in proportion to the temperature.
その剥離部分に水膜が生して耐湿機能を損う問題が発生
する。A problem arises in that a water film forms on the peeled part, impairing the moisture resistance function.
本発明の目的は、前述した従来技術の問題点を解消し、
はんだディラグ面付実装法に適用してもダイリードフレ
ームの熱膨張による歪を緩和してＩＣチップの変形応力
を小さくシ、該■Ｃチップ表面とモールドレジン部との
界面剥離率を大幅に減少ゼしめて、耐湿信頼性の大幅同
上を図れるレジンモールドＩＣパッケーシヲ提供１−る
ことにある。The purpose of the present invention is to solve the problems of the prior art described above,
Even when applied to the solder dilag surface mounting method, it alleviates the strain caused by thermal expansion of the die lead frame, reduces the deformation stress of the IC chip, and significantly reduces the peeling rate at the interface between the C chip surface and the mold resin part. In summary, it is an object of the present invention to provide a resin molded IC package that can significantly improve moisture resistance and reliability.
この目的を達成するために１本発明のレジンモールドＩ
Ｃパッケージは、ＩＣチップとダイリードフレームとを
熱可塑性樹脂によって接着すると共に、ＩＣチップ底面
のダイリードフレームへの接着面積を該ＩＣチップの底
面積よりも少さい面積に制限して、前記熱可塑性樹脂と
モールドレジンとの間に隙間を形成したことを特徴とす
る。To achieve this purpose, a resin mold I of the present invention is used.
In the C package, an IC chip and a die lead frame are bonded together using a thermoplastic resin, and the area where the bottom surface of the IC chip is bonded to the die lead frame is limited to an area smaller than the bottom area of the IC chip. A feature is that a gap is formed between the plastic resin and the mold resin.
以下１本発明の一実施例を第５図により説明する。第３
図は本発明によるレジンモールドＩＣパッケージの断面
図を示し、第１図と同一符号のものは同じもの、もしく
は相当するものを表わしている。本発明によるレジンモ
ールドＩＣパッケージは、グイボンディング部材７とし
て、熱可塑性樹脂を用いてＩＣチップ２とダイリードフ
レーム６とを接着している。またｌＣチップ２底面のダ
イリードフレーム５への接着面積を該ＩＣチップ２の底
面積よりも小さい面積に即１限して、前記ボンディング
部材７の周囲に環状の隙間８を形成しである。An embodiment of the present invention will be described below with reference to FIG. Third
The figure shows a sectional view of a resin molded IC package according to the present invention, and the same reference numerals as in FIG. 1 represent the same or equivalent parts. In the resin mold IC package according to the present invention, the IC chip 2 and the die lead frame 6 are bonded together using a thermoplastic resin as the bonding member 7 . Further, the bonding area of the bottom surface of the IC chip 2 to the die lead frame 5 is limited to one area smaller than the bottom surface of the IC chip 2, and an annular gap 8 is formed around the bonding member 7.
詳しく説明すると、熱可塑性樹脂として１例えば塩化ビ
ニル樹脂を用い、該塩化ビニル樹脂にて厚さ５０μｍ程
度、直径がＩＣチップ２の一辺の長さの６割となす円板
状フィルムを形成し。To explain in detail, for example, a vinyl chloride resin is used as the thermoplastic resin, and a disc-shaped film having a thickness of about 50 μm and a diameter of 60% of the length of one side of the IC chip 2 is formed using the vinyl chloride resin.
該円板状フィルムをＩＣテップ２とダイリードフレーム
６との間に挿入し、加重しながら熱を加えてＩｃチップ
２とダイリードフレーム６とを接着している。The disc-shaped film is inserted between the IC chip 2 and the die lead frame 6, and the IC chip 2 and the die lead frame 6 are bonded together by applying heat while applying weight.
本発明は前記の如き構成としたから、はんだディップ面
付実装法による′はんだディップ時において、ダイリー
ドフレーム５が熱膨張による歪を起こしても、グイボン
ディング部材７である塩化ビニール樹脂の柔軟々伸縮性
で吸収、緩和されるので、ＩＣチップ２には変形応力が
ほとんど発生しない。従って、ＩＣチップ２表面とモー
ルドレジン部１との界面剥離率が大幅に減少し、耐湿信
頼性が大幅に同上する。Since the present invention is configured as described above, even if the die lead frame 5 is distorted due to thermal expansion during solder dipping using the solder dip surface mounting method, the vinyl chloride resin that is the bonding member 7 is flexible. Since it is absorbed and relaxed by its elasticity, almost no deformation stress is generated in the IC chip 2. Therefore, the rate of interfacial peeling between the surface of the IC chip 2 and the mold resin portion 1 is significantly reduced, and the moisture resistance reliability is greatly improved.
第４図は一般的ダイボンディング部材の弾性率と、−Ｉ
Ｃチップ２に働く応力の関係を示したグラフ図で、Ａは
塩化ビニルフィルム、ＢはＡｇペースト、ＣはＡｕ −
Ｓ ｉを示す。この図からも明らかガように、塩化ビニ
ル樹脂をグイボンディング部材として使用することでＩ
Ｃチップ２の変形力を小さく抑えられることが分る。Figure 4 shows the elastic modulus of a general die bonding member and -I
This is a graph showing the relationship of stress acting on the C chip 2, where A is a vinyl chloride film, B is an Ag paste, and C is an Au-
Indicates S i. As is clear from this figure, by using vinyl chloride resin as a bonding material, I
It can be seen that the deforming force of the C-chip 2 can be kept small.
また１本発明においては、グイボンディング部材７の周
囲に環状の隙間８が形成されていて、グイボンディング
部材７である塩化ビニル樹脂の熱膨張による体積増加分
を吸収できる。つまり塩化ビニル樹脂の体積増加分によ
るパッケージの内圧増加を防げるので、ＩＣチップ２．
ダイリードフレーム５とモールドレジン部１との界面で
のクラックの発生を防止できる。Further, in the present invention, an annular gap 8 is formed around the guinea pig bonding member 7, so that an increase in volume due to thermal expansion of the vinyl chloride resin that is the guibonder 7 can be absorbed. In other words, it is possible to prevent an increase in the internal pressure of the package due to the increase in the volume of the vinyl chloride resin.
Cracks can be prevented from occurring at the interface between the die lead frame 5 and the mold resin portion 1.
また１本発明による１、 Ｃパッケージを試験したとこ
ろ、パッケージ内部応力がｏｌに９／ ＊ｔｌに緩和さ
れ、かつＩＣチップ２表面とモールドレジン部１との界
面剥離率が２％以下になることが確認された。In addition, 1. When the C package according to the present invention was tested, it was found that the internal stress of the package was relaxed to ol9/*tl, and the peeling rate at the interface between the surface of the IC chip 2 and the mold resin part 1 was 2% or less. was confirmed.
尚、前記の実施例においては、ダイボンディング部材７
として塩化ビニル樹脂フィルムを用いた例を示したが、
フッ素樹脂、ポリエステルのフィルムまたはこれらの接
着剤ペーストを使用することも可能である。In addition, in the above embodiment, the die bonding member 7
An example using a vinyl chloride resin film was shown as
It is also possible to use fluororesin, polyester films or adhesive pastes thereof.
以上説明したように、本発明によれば、はんだディップ
面付実装法に適用してもダイリードフレームの熱膨張に
よる歪を緩和してＩＣチップの変形応力を小さくできる
ので、ＩＣチップ表面とモールドレジン部との界面剥離
率が大幅に減少され、耐湿信頼性の大幅向上を図れる。As explained above, according to the present invention, even when applied to the solder dip surface mounting method, it is possible to reduce the strain caused by thermal expansion of the die lead frame and reduce the deformation stress of the IC chip. The interfacial peeling rate with the resin part is significantly reduced, and moisture resistance reliability can be significantly improved.
また、ダイボンディング部材の熱膨張による体積増加分
を吸収してパッケージの内圧増加を防げるので、ｌＣチ
ップ、ダイリードフレームとモールドレジン部との界面
でのクラックの発生を防止できる。Further, since an increase in volume due to thermal expansion of the die bonding member can be absorbed and an increase in the internal pressure of the package can be prevented, cracks can be prevented from occurring at the interface between the LC chip, the die lead frame, and the mold resin portion.
第１図は従来のレジンモールドＩＣパッケージの断面図
で、ＩＣチップ及びダイリードフレームが変形している
状態を示す、第２図はＩＣチップ面に働く応力と界面剥
離率との関係を示すグラフ図、第３図は本発明レジンモ
ールドＩＣパッケージの一実施例を示す断面図、第４図
は一般的ダイボンデイング部材の弾性率とＩＣチップ面
に働く応力との関係を示すグラフ図である。
１・・・モールドレジン部、２・・・ｌＣチップ、５・
・・ダイリードフレーム、４・・・リード、５・・・ボ
ンディングワイヤ、７・・・ダイボンディング部材（塩
化ビニル樹脂）、８・・・隙間。Figure 1 is a cross-sectional view of a conventional resin molded IC package, showing the deformed state of the IC chip and die lead frame. Figure 2 is a graph showing the relationship between stress acting on the IC chip surface and interfacial peeling rate. 3 are cross-sectional views showing one embodiment of the resin molded IC package of the present invention, and FIG. 4 is a graph showing the relationship between the elastic modulus of a general die bonding member and the stress acting on the IC chip surface. 1...Mold resin part, 2...LC chip, 5...
...Die lead frame, 4...Lead, 5...Bonding wire, 7...Die bonding member (vinyl chloride resin), 8...Gap.
Claims (1)
レームとがダイボンディング部材により接続されて成る
レジンモールドＩＣパッケージにおいて、前記ｌＣチッ
プと前記ダイリードフレームとを熱可塑性樹脂によって
接着すると共に、ＩＣチップ底面のダイリードフレーム
への接着面積を該ＩＣチップの底面積よりも小さい面積
に制限して、前記熱可塑性樹脂とモールドレジンとの間
に隙間を形成したことを特徴とするレジンモールドＩＣ
パッケージ。In a resin molded IC package in which an IC chip and a die lead frame in a mold resin part are connected by a die bonding member, the IC chip and the die lead frame are bonded with a thermoplastic resin, and the die lead on the bottom surface of the IC chip is bonded to the IC chip and the die lead frame using a thermoplastic resin. A resin molded IC characterized in that the adhesive area to the frame is limited to an area smaller than the bottom area of the IC chip to form a gap between the thermoplastic resin and the mold resin.
package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58107687A JPS60747A (en) | 1983-06-17 | 1983-06-17 | Resin molded ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58107687A JPS60747A (en) | 1983-06-17 | 1983-06-17 | Resin molded ic package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60747A true JPS60747A (en) | 1985-01-05 |
Family
ID=14465419
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58107687A Pending JPS60747A (en) | 1983-06-17 | 1983-06-17 | Resin molded ic package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60747A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4857989A (en) * | 1986-09-04 | 1989-08-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| EP0843358A3 (en) * | 1992-11-27 | 1998-05-27 | Esec Sempac S.A. | Electronic flat-pack module and chipcard |
| US6472730B1 (en) * | 1999-04-23 | 2002-10-29 | Sharp Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| WO2005078794A1 (en) * | 2004-02-16 | 2005-08-25 | Infineon Technologies Ag | Non-planar integrated circuit system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5772337A (en) * | 1980-10-24 | 1982-05-06 | Hitachi Ltd | Semiconductor device |
-
1983
- 1983-06-17 JP JP58107687A patent/JPS60747A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5772337A (en) * | 1980-10-24 | 1982-05-06 | Hitachi Ltd | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4857989A (en) * | 1986-09-04 | 1989-08-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| EP0843358A3 (en) * | 1992-11-27 | 1998-05-27 | Esec Sempac S.A. | Electronic flat-pack module and chipcard |
| US6472730B1 (en) * | 1999-04-23 | 2002-10-29 | Sharp Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| WO2005078794A1 (en) * | 2004-02-16 | 2005-08-25 | Infineon Technologies Ag | Non-planar integrated circuit system |
| US7633149B2 (en) | 2004-02-16 | 2009-12-15 | Infineon Technologies Ag | Integrated circuit arrangement |
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