JPS6074669A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to increase the density and the integration of a BIC memory and a mask ROM by prevention of the positional slippage of the element-forming region of a memory device and an electrode contact window by a method wherein the write is performed by conduction of a P type region and an Al film wiring via diode, and the readout is performed by application of a forward bias between the wiring and the band form region and then by detection of its current. CONSTITUTION:A plurality of arrays of the first band form isolation oxide film 12 arranged in the direction of X at intervals d1 corresponding to the dimension of the window are formed on the surface of an N type Si substrate 11 having a specific resistance of e.g. approx. 10 [OMEGA-cm]. Next, with this film 12 as a mask, B<+> is ion-implanted to the surface of the element-forming region. Then, a plurality of lines of the second band form isolation oxide films 14 arranged at intervals d2 corresponding to the dimension of the contact window in the direction of Y rectangularly intersecting with the first band form isolation oxide film is formed on the substrate with a similar oxidation resistant film as a mask. As<+> is activated and re-distributed by heat treatment, and an island form N<+> type region 16 of a fixed depth is formed in a band form P type region 13 under an aperture 15. An Al film wiring 19, a surface protection insulation film, etc. are formed, and accordingly the BIC memory is completed.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a storage-only memory in which information can be electrically stored using electrostatic breakdown of an insulating film. The present invention relates to a continuous read only memory (Mask ROM) in which information is fixed by phosphorography technology using a mask corresponding to a variable speed, and a manufacturing method thereof.

(b) Background of the technology Memory that uses electrostatic breakdown of an insulating film to write and provide information (
Breakdown of Insul
ator for conduction memory
known as y'. Hereinafter, this will be abbreviated as BIC memory.

As shown in the circuit diagram in FIG. 1, the BIC memory has a structure in which a diode Di and an insulator 19IC are connected in series at the intersection of a matrix consisting of a bit edge BL and a word iWL. By electrostatically destroying the membrane,
Bit edge BL at desired intersection via diode DI
Information is written by making the word 1ilWL conductive. (In some cases, the direction of Di is reversed, and in some cases, the positions of Di and C swapped in series.) In this way, BIC memory elements have an unlimited potential for electrostatic breakdown of the insulating film. Since it is formed using a phenomenon in a small area, it is possible to significantly reduce the cell area compared to memory elements formed using ordinary transistors.
This is extremely effective for increasing the density and integration of ROM.

(C) Conventional technology and problems A conventional BIC memory cell is schematically shown in FIG. It was formed into a arrogant structure. In these figures, 1 is an n-type silicon (St) substrate, 2 is a field oxide film, 3 is an element formation region, 4 is a band-shaped p-type region (bit line), and 5 is a phosphosilicate glass (PSG) insulator. film,
Reference numeral 6 designates an electrode contact window, 7 an island-like n medium-sized region, 8 a polycrystalline Si electrode, 9 a polycrystalline Si oxide film, and 10 an aluminum (At) film wiring (word line).

In the conventional structure, a band-shaped p-type region 4, that is, a self-line is formed on the bit line (boiled oxidation llll!2), and is formed in the p-type region 4 at the intersection of the bit line and the word line. The formation of the n-type region 7 (formation of a diode) and the electrical connection between the p-type region 4 and the At film wiring 10, which is a word line, via the diode,
This was done through an electrode contact window 6 formed on a dielectric film 5 disposed on the mold region 4 using photolithography.

Therefore, in the conventional structure, when the memory cell is highly integrated at high density and the width of the element formation region 3 defined by the field oxide film 2 is further miniaturized, the photolithography technique Due to an error in mask alignment, the electrode contact window 6 is formed offset from the element formation region 3. As a result, the diode formed in alignment with the electrode contact window 6 is not formed as designed, and the contact resistance of the At film arrangement 1110 with respect to the diode increases.
Problems such as these occur, and the electrical performance of the memory element deteriorates.

(d) Purpose of the Invention In view of the above-mentioned problems, the present invention provides a structure and a method for manufacturing the same that prevents misalignment of the element formation @ clay and the electrode contact window in a semiconductor memory device. The purpose is to enable higher density and higher integration of BIC memories and mask ROMs.

(e) Structure of the invention, that is, the present invention includes a semiconductor substrate having a first conductivity type, and a plurality of rows of first semiconductor substrates formed in one direction on the surface of the semiconductor substrate.
a strip-shaped isolation insulating film formed on the semiconductor substrate;
a plurality of rows of strip-shaped second conductivity type regions defined by a strip-shaped isolation insulating film and arranged in one direction; and a plurality of rows of strip-shaped second conductivity type regions formed on the semiconductor substrate surface in a direction intersecting the first strip-shaped isolation insulating film. a second strip-shaped isolation insulating film; a second strip-shaped isolation insulating film and a second strip-shaped isolation insulating film;
a plurality of island-shaped first conductivity type regions selectively formed in the strip-shaped second conductivity type mound in contact with the openings; a plurality of rows of electrode wiring that bridges the top in a direction crossing the first strip-shaped isolation insulating film, and contacts the island-like first conductivity type territory when the opening is completely destroyed; The first conductivity type polycrystalline silicon layers are individually arranged on the island-like first conductivity type regions exposed in the internuclear pores.
A voltage is applied between the electrode wiring corresponding to information and the band-shaped second conductivity type area, which is composed of a pattern and an oxide film formed on the surface of the polycrystalline silicon pattern, and the oxide film is destroyed by electrostatic discharge. A collapsible read-only memory element in which information is written by
A semiconductor device characterized by being provided with a read-only memory element that fixes information by selectively removing a 7-letter insulating thin film provided on a conductive type region surface using a mask corresponding to the information. , a plurality of first rows arranged in one direction on the surface of a semiconductor substrate having a first conductivity type.
forming a strip-shaped isolation insulating film on the semiconductor substrate, forming a plurality of rows of strip-shaped second conductivity type regions aligned with the first strip-shaped isolation insulating film on the semiconductor substrate surface; A plurality of rows of second strip-shaped isolation insulating films arranged in a direction crossing the insulating film are formed, and the second strip-shaped isolation insulating films are aligned with the openings defined by the first strip-shaped isolation insulating films and the second strip-shaped isolation insulating films. A diagonal number of island-like first conductivity type regions are selectively formed in the band-like second conductivity type region, and first conductivity type regions in contact with the core island-like first conductivity type regions are formed on the openings.
A conductive polycrystalline silicon pattern is formed, an oxide film is formed on the surface of the polycrystalline silicon pattern, and the polycrystalline silicon pattern is in contact with the polycrystalline silicon pattern having the oxide film on the substrate. The first strip-shaped isolation film 8 - The method for manufacturing the semiconductor device described above, and forming a plurality of rows of first strip-shaped isolation insulating films arranged in one direction on the surface of a semiconductor substrate having a first conductivity type, forming a plurality of rows of strip-shaped second conductivity type regions aligned with the first strip-shaped isolation insulating film;
forming a plurality of rows of second strip-shaped isolation insulating films arranged in a direction intersecting the first strip-shaped isolation insulating films on the semiconductor substrate surface; A plurality of island-like first conductivity type areas are selectively formed in the band-like second conductivity type region in alignment with the openings defined by the openings, and the island-like first conductivity type areas are exposed within the openings. forming an insulating thin film on the area;
selectively etching away the insulating thin film within the opening using a mask corresponding to the information, and etching the opening onto the substrate by touching the inner surface of the opening and intersecting the opening with the first strip-shaped isolation insulation film. The present invention relates to a method of manufacturing the semiconductor device described above, comprising a step of forming a plurality of rows of electrode wirings bridging in a direction.

(f) Examples of the invention DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments and drawings.

FIG. 3 is a schematic top view (a), A-A/arrow sectional view (b), B-B/arrow sectional view e →, in an embodiment in which the structure of the present invention is applied to a BIC memory Figures 4 to 8 are the same B.
A top view of the process in one embodiment of the IC memory manufacturing method (
A), A-A” arrow view process cross-sectional view (B), B-B” arrow view process cross-sectional view (C), and Figure 9 show the structure of the present invention as a mask ROM.
Schematic top view (A) of an example applied to
'Arrow cross-sectional view (b), B-B arrow cross-sectional view (c), 1st
0 to 7] The figures are a top view of the process in one embodiment of the mask ROM manufacturing method (A), A-A': A cross-sectional view of the process in the direction of the J-arrow (B), and a process in the direction of the B-BZ arrow. Cross-sectional view (c), 12th
The figure is an impurity concentration profile diagram of diodes formed by the methods of these examples. Note that in FIGS. 3 to 11, each part is indicated by the same symbol.

For example, the BIC memory to which the present invention is applied is shown in FIG.
, (b) and (c), n-type silicon (Si)
The substrate 11 and silicon nitride (S i
A plurality of rows of first strip-shaped isolation oxides 11!112 are formed in line in the X direction by a selective oxidation method using an oxidation-resistant film such as sN4) as a mask, and the first strip-shaped isolation oxides are formed on the Sl substrate 11. The band-shaped p-type head region 13 of the Cypress number sequence formed in alignment with the isolation oxide film 12 is formed on the semiconductor substrate 11 using a selective oxidation method or the like using an oxidation-resistant film such as Si or N4 as a mask. A plurality of rows of second strip-shaped isolation oxide films 14 formed in line with each other, the first strip-shaped isolation oxide film 12 and the second strip-shaped isolation oxide film 14
a plurality of island-shaped n medium-sized regions 16 that are selectively formed in the band-shaped p-type head region 13 in alignment with the aperture 15; Information is written by electrostatic discharge damage formed on the surfaces of the n-type polycrystalline Si electrode patterns 17 individually arranged on the exposed island-shaped n-type regions 16 and the polycrystalline silicon medium patterns 17. It has a plurality of rows of aluminum (Az) film wiring 19 bridging the oxide M18 of the polycrystalline S1 and the polycrystalline Si electrode pattern 17 having the oxide film 18 in the X direction. In this embodiment, the arrangement interval (dl) of the first strip-shaped isolation oxide film 12 and the arrangement interval (d,) of the second strip-shaped isolation oxide film *i4 are selected to be, for example, 2 [2 μm]. , in this case the first separated oxidation 8! i! x2 and second isolation oxide film 14
The dimensions of the aperture 15, that is, the electrode contact window, defined by this are 2×2 [μm]. Further, the band-shaped p-type head region 13 has a surface impurity concentration 'O'' (a tm/cd
] Formed to a depth of about l (μm), island-like n0 regions 16
For example, the impurity concentration is 101it~I O” (a tm
/m ), and the depth is approximately 2000 to 3000 (A:).The thickness of the first strip-shaped isolation oxide film 12 is initially 60 mm.
00[A], and the second strip-shaped isolation oxide film 14
is formed to a thickness of about 4,000 to 6,000 (ku).

Also, the thickness of the polycrystalline St electrode pattern 17 is 1000 (A)
The thickness of the oxide film 18 formed on the polycrystalline Sl electrode pattern 17 is set to about 200 mm because it is necessary to be able to write with a normal voltage for driving the memory element and to maintain a desired breakdown voltage. ~400(A) is appropriate. Also n
The impurity concentration of the type polycrystalline St electrode pattern 17 is 10"
~10'' (atm/cII) is appropriate.

Based on the information to be stored in the BIC memory element, the p-type head area is placed between the desired 9m strip area (bit line) 13 and the desired At film wiring (word line) 19. 13 and the At film wiring 19 have an island-like n medium-sized region 16 at the junction point.
A voltage is applied so that the diode formed by the strip-shaped p-type head region 13 is in the forward direction, and the oxide film 18 on the polycrystalline St electrode 7 is electrostatically destroyed and the polycrystalline Si electrode pattern 17 is and p, the membrane arrangement IIi! By short-circuiting the p-type head region 13 and the At film wiring (word connection) 19 through the diode, information is written. Also, for reading, At film wiring (word a) 19
This is done by selecting one each of the p-type head area (bit line) 13 and applying a forward bias between them, and detecting the current flowing depending on the presence or absence of writing. Note that FIG. 3 shows a state in which no scouring is performed.

The BIC memory having the structure of the present invention described above is manufactured, for example, by the following method.

Refer to FIGS. 4(a), (b), and (c). For example, using an n-type Sl group, 1lt211, having a specific resistance of about 10 [Ω-m], the 81
On the surface of the substrate 11, first strip-shaped isolation oxide films 12 arranged in the X direction at intervals (dl) of, for example, 2 [μm], which correspond to the desired electrode contact window dimensions, are formed with a thickness of, for example, 6000 (dl).
A), and then, using the first band-shaped isolation oxide film 12 as a mask, the exposed substrate surface, that is, the surface of the element formation region, is coated with a voltage of, for example, lXl0'' (atm/cfA), 140 (KeV).
Boron (B+) ions are implanted under certain implantation conditions.

Here, the selective oxidation method is a method in which a thick oxide film is selectively formed on the surface of the 81 substrate by thermal oxidation using an oxidation-resistant film such as silicon nitride (S is Na) as a mask. The surface of the 81-base layer is coated with a thickness of, for example, 500 (A) by thermal oxidation.
) initial oxidation [OXI] is formed, and chemical vapor deposition (C
For example, a thickness of 1000 mm is formed on the initial oxide film OX by the VD) method.
[A) Form a 5isN4 film (cavity) and photo-coat.
Using lithography technology, the Si3N4 film is divided into a plurality of strip patterns having a predetermined width corresponding to the electrode contact windows and lined up at desired intervals in the X direction, and the first strip pattern 81s
The first strip-shaped isolation oxide film 1 is exposed on the substrate surface by thermal oxidation using the N4 film pattern (not shown) as a mask.
This is the method of forming 2. In addition, in this method, Sin
When patterning N4m, even the initial oxide film interposed below may be removed.

Further, B+ ion implantation is performed using the first strip-shaped isolation oxide film 12 as a mask after removing the Si, N, and film patterns (not shown). This ion implantation is usually done through a thin oxide film to prevent damage to the substrate.
In this embodiment, the process is performed through the initial oxide film OXI. Note that when removing the Si8N4 film pattern, the S
i3N.

When the initial oxide film OXr under the film pattern (not shown) is also removed, it is necessary to form a new thin oxide film on the surface of the element formation region.

Refer to FIGS. 5(a), (b), and (c). Next, on the substrate after the B+ ion implantation, a selective oxidation method is applied using the same oxidation-resistant film, for example, a 5isN4 film pattern (not shown in FIG. 15) as a mask. Accordingly, the second strip isolation oxide film of divisor rows is arranged at an interval (d,) corresponding to the contact window size, for example, 2 [μm], in the direction perpendicular to the first strip isolation oxide film, that is, in the Y direction. An oxide film 14 is formed. By the heat treatment during the selective oxidation, the B+ implanted into the substrate surface is activated and redistributed, forming a band-shaped p-type head region 13.

Next, after removing the 5llN4 film pattern, the second
the strip-shaped isolation oxide film 14 and the first strip-shaped isolation oxide film 12
The isolation oxide film 12.14 is used as a mask to cover the band-shaped p-type region 13 exposed through the initial oxide film OX in the opening 15 defined by the initial oxide Jl! Selective arsenic (A?) through OX r, e.g. 1x lOIH (
ion implantation is performed under conditions of approximately 120 (KeV) and 120 (KeV).

In this example, since the first initial oxide film OX was left, the second 5isN4 film pattern (not shown) was formed on it, but the Si plane of the element formation region was exposed. When exposed, it is necessary to form a second initial oxide film on the surface of the element formation region 16 before forming the second 5ijN4111. Further, in this embodiment, Aa+B+ is implanted to form the second Si and N layers.

Only the film pattern was removed, and implantation was performed through the first initial oxide film underneath, but the first initial oxide film, the damage prevention oxide film formed during B+ implantation, and the second initial oxide film were also removed. If the p-type head region 13 surface is exposed in the opening 15, a thin oxide film for damage prevention is formed on the surface of the implanted image region, and A8+ is implanted through the thin oxide film. is desirable.

Referring to FIGS. 6(a), (b), and (c), a predetermined heat treatment is then performed to activate and redistribute the pre-MeAg+ into the band-shaped p sub-region 13 below the opening (electrode contact window) 15. , depth e.g. 2000-3000
An island-like n-type region 16 of approximately [A] size is formed. Note that due to the heat treatment, B+ in the p-type band-shaped region 13 is further dispersed and becomes C1.
For example, a p-type teisho ryokan 13 having a predetermined depth of about 1 [μm] is completed.

Refer to FIGS. 7(a), (b), and (c). Next, the first initial oxide film 0XI (or second initial oxide film, thin oxide film formed during ion implantation, etc.) inside the opening 15 is removed. After that, a non-contact film with a thickness of about 1000 to 2000 [A], for example, is deposited on the substrate using a normal CVD method.
A doped polycrystalline Si layer is formed, and the non-doped polycrystalline St layer is coated with, for example, IXIOII (atm/ej), 40[:Ke
Phosphorus (P+) was ion-implanted under implantation conditions of about 1V].
After annealing for about 10 minutes at a temperature of about 1,000 degrees Celsius to make the polycrystalline St layer electrically conductive, patterning is performed using normal photo-phosphorography technology, Said 1st. Second strip-shaped isolation oxide film 1
2. Form an n-type polycrystalline St electrode pattern 17 in contact with the island-like n-type region 16 on the opening 15 defined by For example, the thickness is 200~300[:A
) oxidation 11118 of polycrystalline S1 is formed. Note that the electric field strength (withstand voltage) of the polycrystalline Si fermented membrane 18 is
As the dose of impurities to t increases, it decreases,
In the case of non-doped polycrystalline Si, about 6 [M/crn] f
In contrast, in the case of the polycrystalline SI of the dose lid 2 (
MY/crn). The thickness of the polycrystalline St oxide film 18 is determined by the electric field strength and the dipping voltage.

FIG. 8 (a), (b), (c) Next, an HT (including alloy) film with a thickness of about 1 [μm] is formed on the substrate by vapor deposition or sputtering as usual. Pattern ninder is performed using a photolithography technique or the like to form a number bridging the polycrystalline S1 electrode pattern 17 having the oxide film 18 in a direction perpendicular to the band-shaped P sub-region (bit line) 13, that is, in the X direction. Row At film wirings (word lines) 19 are formed.

Although not shown, a surface protection insulating film and the like are formed to complete the BIC memory to which the present invention is applied.

Further, a mask ROM to which the present invention is applied includes an n-type Si substrate 11 and a layer of Si, N, etc. on the surface of the Si substrate 11, as shown in FIGS. A plurality of rows of first strip-shaped isolation oxide films 12 are formed in line in the X direction by a selective oxidation method performed using an oxidation-resistant film as a mask, and the Si substrate 11 is aligned with the first strip-shaped isolation oxide films 12. A plurality of rows of strip-shaped p sub-regions 13 are formed as shown in FIG.
Formed side by side in the Y direction using a selective oxidation method using an oxidation-resistant film such as an N4 film as a mask 2! The openings 15 are defined by the second strip-shaped isolation oxide film 14 in the nth rows, the first strip-shaped isolation oxide film 12 and the second strip-shaped isolation oxide film 4; A plurality of island-like n green regions 16 selectively formed in the band-like p sub-region 13 in alignment, and information arranged on the surface of the island-like n medium region 16 exposed in the opening 15. It includes a fixing silicon dioxide (Sift) film 20 having a thickness of, for example, about 500 to 1000 (A), and a plurality of rows of AtJI@ wiring 19 bridging the opening 15 in the X direction.

In addition, in the mask ROM, as shown in the manufacturing method described later, the Sin in the opening 15 and the film 20 are adjusted in advance according to information.
are selectively removed. FIG. 9 shows this state. Further, in this embodiment, the first and second strip-shaped isolation oxide films 12
．． 14 formation intervals (dl.

d, ) and thickness, impurity concentration and depth of band-like p sub-region 13, impurity concentration and depth of island-like n-type region At film distribution +v
The thickness of j19, etc., are formed in the same manner as in the embodiment of the BIC memory, for example.

The mask ROM having the structure of the present invention described above is formed, for example, by the following method.

Figure 6 (a), (b), (c) ■6 First, the above B
A plurality of rows of first strip-shaped isolation oxide films 12 arranged in the X direction are formed on the surface of the n-type S1 substrate 11 by a method similar to the example of the IC memory, and aligned with the first strip-shaped isolation oxide films 12. Then, a plurality of rows of strip-shaped p sub-regions 13 are formed on the S1 substrate, and a plurality of rows of second strip-shaped isolation oxide films 14 arranged in the Y direction are formed on the substrate surface. Second strip-shaped isolation oxide film 12°1
A hole (electrode contact window) 15 defined by 4 is formed, and an island shape n is formed in the band-like p-type region 13 aligned with the hole 15.
A green mold area 16 is formed. Note that OX1 in the figure is an initial oxide film.

Refer to FIGS. 10(a), (b), and (c). Next, after removing the initial oxide film OXl, thermal oxidation is performed again, and the island-shaped n-type head region 1 exposed in the opening 15 is removed.
A Sin film 20 with a thickness of about 500 to 1000 (λ) is formed on six sides, and then a stow film is formed in a predetermined opening (electrode contact window) 15 by photophosphorography using a mask corresponding to the information. 20 is selectively removed and the reduction information is fixed.

Figure 11 (a), middle), a film (containing an AtC alloy) having a thickness of about 1 [μm] is formed on the substrate by evaporation or sputtering as usual in the 2009 diagnostic method, and then - Pattern ninder is performed using phosphorography technology, etc., and the opening 15 is formed with several rows of At film wiring (word) bridging in the direction perpendicular to the band-shaped p-type head area (bit line) 13, that is, in the X direction. Line) 19 is formed. (Mo
or Mo5il wiring may be used. ) Although not shown, a surface protection insulating film and the like are formed to complete a mask ROM to which the present invention is applied.

FIG. 12 shows impurity +7 [
It shows a profile diagram.

In the structure of the present invention, if it is desired to increase the withstand voltage of the diode, the B+ implantation when forming the band-shaped p-type head region (bit line) is divided into multiple steps, It is sufficient to selectively lower the impurity concentration only in the region where the n medium-sized head is formed and its vicinity. (g) Effects of the invention As explained above, according to the present invention, when forming a BIC memory or mask ROM using an n-type/recon board, for example, the band-shaped p-type head area (bit*) , a plurality of electrode contact windows are formed in alignment with a plurality of rows of first strip-shaped isolation oxide films formed in one direction by a selective oxidation method, and provided in the strip-shaped p-type head clay. A strip-shaped isolation oxide film and a plurality of rows of second isolation oxide films formed by selective oxidation in a direction perpendicular to the first strip-shaped isolation oxide film, for example.
The area is defined by a band-shaped isolation oxide film.

Therefore, even if the width of the band-shaped p-type region becomes fine, the electrode contact window and the island-like n medium-sized thin plate formed in the band-shaped p-type head area in alignment with the electrode contact window will be Since the voltage does not deviate from the range, the electrical performance of the BIC memory or mask ROM is not impaired.

Therefore, the present invention has the effect of enabling high-density and high-integration of FROM, which stores information by utilizing electrostatic breakdown of an insulating film, and mask ROM, which stores information by using a photo mask.

Note that the present invention can also be applied to a p-type semiconductor substrate.

In that case, the bit line is formed with a band-shaped n-type head region, within which the first . An island-like p-type region is formed in alignment with the electrode contact window defined by the second strip-shaped isolation oxide film. Further, in the BIC memory element, the polycrystalline silicon electrode in contact with the island-like p-type head region also becomes p-type.

Furthermore, in the present invention, the band-shaped element isolation region is not limited to the band-shaped isolation oxide film formed by the selective oxidation method shown in the above embodiment, but is formed by forming an isolation trench on the semiconductor substrate surface. An insulating film isolation structure in which an insulating film is buried in the trench may also be used.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of a BIC memory that writes information using electrostatic breakdown of an insulating film. Figure 2 is a schematic top view (A) showing the conventional structure of the BIC memory, and A-AI arrows. Fig. 3 is a schematic top view (a) of an embodiment in which the structure of the present invention is applied to a BIC memory, A-A4' Arrow sectional view (b), B-B
4 to 8 are a cross-sectional view as viewed from the arrow (C), a top view of the process in an embodiment of the BIC memory manufacturing method (A), and A.
-A) A cross-sectional view of the process in the direction of arrows (b), a cross-sectional view of the process in the direction of B-B (c), and FIG. ), A-A cross-sectional view (b), B-B-/arrow cross-sectional view (→, Figures 10 and 11 are process top views in one embodiment of the method for manufacturing the same mask ROM (A), A-A7 arrow view process cross-sectional view (B),
FIG. 12 is a sectional view (c) of the process taken along the line B-f3', and is an impurity concentration profile diagram of the diode formed by the method of this embodiment. In the figure, 11 is an NFF1 silicon substrate, 12 is a first strip-shaped isolation oxide film, 13 is a strip-shaped P sub-region (bit line) 14 is a second strip-shaped isolation oxide film, 15 is a first strip-shaped isolation oxide film, and 15 is a strip-shaped isolation oxide film. An opening defined by the second strip-shaped isolation oxide film, 16 is an island-like n+ type region 1
7 is an n-type polycrystalline silicon electrode pattern, 18 is a polycrystalline silicon oxide film, 19 is an aluminum film wiring, 20 is a silicon dioxide film, OXI is an initial oxide film, B+ is a boron ion, and As'' is an arsenic ion. . −27−・・” くε p − Samurai plan red and blue −

Claims (1)

[Claims] 1. A semiconductor substrate having a first conductivity type, a plurality of rows of l-th strip-shaped isolation insulating films formed in one direction on the surface of the semiconductor substrate, and a plurality of rows of strip-shaped second conductivity type regions defined by the first strip-shaped isolation insulating film and arranged in one direction; a plurality of rows of second strip-shaped isolation insulating films; apertures defined by the first strip-shaped isolation insulating films and the second strip-shaped isolation insulating films; and a second conductivity type strip in contact with the openings. A plurality of island-shaped patterns i4 selectively formed in the area are bridged with the patterned area in a direction crossing the first strip-shaped isolation insulating film over the opening, and It has a plurality of rows of inter-electrode axes in contact with the island-like first conductivity type head region, and a memory element connecting the tlE & wiring and the island-like 14th conductivity type region is disposed in the opening. A semiconductor device characterized by: 2. A first conductive* type polycrystalline silicon pattern individually disposed on the island-like first conductive type hook region where the memory element is exposed in the opening, and an id polycrystalline silicon pattern. A voltage is applied between the wiring corresponding to information and the strip-shaped second conductivity type region, and the oxide film is electrostatically destroyed to store information. 2. The semiconductor device according to claim 1, comprising a writable read-only memory element that performs writing. 3. A 141st island in which the memory element is exposed within the opening.
Claim 1, characterized in that the read-only memory element is comprised of a read-only memory element in which information is fixed by selectively removing an insulating film provided on a type 1 region surface using a mask corresponding to the information. Semiconductor equipment. 4. Forming a plurality of rows of first strip-shaped isolation insulating films aligned in one direction on the surface of the semiconductor substrate on which the first conductivity type gold is layered, and forming a plurality of rows of first strip-shaped isolation insulating films aligned with the first strip-shaped isolation films on the semiconductor substrate. A second conductivity type region is formed, a plurality of rows of second strip-shaped isolation insulating films are formed on the semiconductor substrate surface in a direction intersecting the first strip-shaped isolation film, and Separation insulating film and second
A plurality of island-shaped first conductivity type regions are selectively formed in the strip-shaped second conductivity type region in alignment with the openings defined by the strip-shaped isolation insulating film, and the island-shaped first conductivity type regions are formed over the openings. 1 guide 1! A 14th electric type polycrystalline silicon pattern is formed in contact with each L-type region, an oxide film is entirely formed on the surface of the polycrystalline silicon pattern, and a polycrystalline silicon pattern having the oxide # is formed on the substrate.
A method for manufacturing a first strip-shaped isolation insulating film in contact with a pattern and in contact with the polycrystalline silicon pattern. 5. Forming a plurality of rows of first strip-shaped isolation insulating films arranged in one direction on the surface of a semiconductor substrate having an forming a plurality of rows of second strip-shaped isolation insulating films arranged in a direction intersecting the first strip-shaped isolation insulating films on the surface of the semiconductor substrate; The strip-shaped isolation insulating film and the second
A plurality of island-shaped first conductive regions are selectively formed in the diagonal second conductive region aligned with the aperture defined by the strip-shaped isolation insulating film, and a plurality of island-like first conductive regions are formed in the aperture. An insulating thin film is formed on the island-like 14th electrode type region to be etched, and the insulating thin film inside the opening is selectively etched away using a mask corresponding to the information, and the inside of the opening is etched on the substrate. 1. A method of manufacturing a semiconductor device, comprising the step of forming a plurality of rows of electrode lines that are in contact with the first strip-shaped isolation insulating film and bridge the openings in a direction crossing the first strip-shaped isolation insulating film.