JPS5887876A - Semiconductor device - Google Patents

Abstract

PURPOSE:To minimize the dimensions of a device by making identical the sectional structures of a memory transistor and an address-selecting transistor which are connected in series to each other. CONSTITUTION:Floating gate electrodes 8 and 12 in a memory transistor (M)7 and a selecting transistor (T)11 are patterned into a form 24 indicated by a dotted line, and then are formed finally in a self-alignment manner by using control gate electrode patterns 10 and 14 as masks. Both of these gate electrodes are almost identical in dimentions in the direction of a channel. Moreover, the areas between the floating gate electrodes of the transistors (M) and (T) and a channel region are set to be S1M=25mu<2> and SiT=50mu<2>, while the areas between the floating gate electrodes and the control gate electrodes are set to be S2M= S2T=150mu<2>. The ratio of S2/S1 is S2M/S1M=6 in the transistor (M), and S2T/S1T=3 in the transistor 3, while S2M/S1M:S2T/S1T=2. By setting design parameters to be as mentioned above, electric fields generated in the first gate SiO2 films 7 and 11 of the transistors (M) and (T) can be changed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an improved semiconductor device, particularly an improved fc
The present invention relates to a semiconductor device that has a structure and performs order storage ωj.

Conventionally, this German semiconductor device uses two transistors (memory transistor and blue field selection transistor) per memory bit, and the address selection transistor is an ordinary single-gate MO8 type transistor. was used legally. However, since the memory transistor is a stacked gate type MOS transistor having a floating gate electrode and a limiting J gate electrode, and the landing selection transistor connected in series with this is a single to gate type MOS transistor, Compared to the case where two transistors of the same structure are arranged side by side between the four transistors,
Plus alpha (10α) dimensions, it is essential to protect the equipment.・This was a drawback in Hakumo Note 1 River.

This invention was made in response to the above-mentioned drawbacks of the conventional device, and it eliminates the disadvantages of the conventional device in terms of dimensions, resulting in increased cylindrical structure, higher performance, and higher production speed. LvI's Yorishin Ashioji, the goal is to do something.

A semiconductor device according to the present invention includes a source/train region which is provided in the vicinity of the main surface of a semiconductor substrate with metal layers spaced apart from each other, and has a conductivity type opposite to that of the substrate, and a first region on the main surface of the substrate between these regions. A floating gate electrode consisting of a gate insulating group and a conductive layer on top of this, and a second electrode on top of the floating gate electrode pulsed light, which is insulated from other parts.
A stacked gate Mos-type memory transistor (M) having a control gate electrode (CG) made of a conductive material on top of the gate insulating group is connected in series with the memory transistor. The MOS type transistor (T)' for address selection has a same cross-sectional structure, and the FG and CG of both transistors (M) and (T) are self-aligned on the tiles along the channel direction. At the same time, the source and drain Ii4 regions of both (M) and (T) are also formed in a self-line between FG and CG, and the F of the CG-rr G gap t is determined.
'When the ratio to the G-substrate capacitance is (M), it is better (T
) has been set at 91.5 times greater.

In the device of this invention, since the cross-sectional structures of the memory transistors and the address selection transistors connected in one column of 1fl are exactly the same, the dimensions between these transistors are determined by PR (Photo R) when patterning the control gate electrodes.
As far as e5ist) technology and etching technology are concerned, the minimum dimension of p can be set to fi-1, and there is no need for +α as in the conventional device d. As a result, the size of the device can be minimized, which, as mentioned above, brings significant additional advantages.

Here, an explanation will be added to further clarify the operational aspects of the device of the present invention. Generally speaking, in stacked gate (MOS) transistors, the overlap surface between the floating gate electrode and the substrate is 81 Capacitor tray C8 first gate SiO □
The film thickness is dl, and the overlap between the floating gate electrode and the control gate 'lL is 82%, and each award is C! , second gate 5
If the in2 film thickness is d8, and the Mli1 ratio of 6 is Sin, C,==63. /as, C2=gs2/
It becomes a2. Therefore, a voltage V is applied to the control gate electrode. When sio is applied, the electric field E generated in the first gate sio and the film can be expressed as follows.

Mark = C* VG/d I (Ct +Ct) = VG/
ca, +dt (St/5l)) Therefore, as in the device of the present invention, the memory transistor and the address selection transistor have the same cross-sectional structure (i.e., d, d,
Even if Sz/Sl is the same), it is possible to change the electric field E during the first gate 5iOii conversion by changing Sz/Sl. Therefore, during the convolution/erase operation, the voltage V applied to the control gate 11L pole. Memory transistor It'J, F'owler - Nordh
eim When creating an electric field E that causes charge injection and discharge using a tunnel mechanism etc., the aim is to suppress the field E to 14, so that these dust phenomena do not occur in the address selection transistor at the same time. This is possible by selecting the parameters S2/S1.

Next, in order to make it easier to understand the nature and nature of the present invention, examples will be given and explained in detail with reference to the drawings.

FIG. 1 is a cross-sectional structural model diagram of an embodiment of the semiconductor device of the present invention. FIG. 2 is a plan view of the same device, and FIG. 1 shows a cross section taken along the line AA' shown in this figure.

In Figures 1 and 2, l has a specific grinding resistance of approximately 100-
z PmSi single crystal substrate, 2 the main surface of l having a surface index (100), 3 the field S10. It is a membrane.

6- 4.5.6 is n-type diffusion region and 4 is stacked gate MO
The source region of the 8-type memory transistor, 5 is a common region between the drain of the memory transistor and the source of the MO8-type address selection transistor, and 6 is the drain region of the selection transistor.

7. 11 are the first gate (SiQ) films of the memory transistor (hereinafter referred to as M) and the selection transistor (hereinafter referred to as T, !: abbreviation), which are formed by the thermal printing method in 1, and the thickness of both is 1. It is 150A. 8.12 are M and T respectively
The floating gate 'Fa electrode is made of polycrystalline Si with a thickness of approximately 200 OA and phosphorus, which is an N-type impurity, is cooled. 9
, 13 are each M.

8゜1 in terms of 5in2 second gate with T thickness of about 100OA
2 (D grown by thermal oxidation. 10.14 are respectively M
, T, and is formed of phosphorus-doped polycrystalline Si with a thickness of about 500 OA. 15 is PSG (Phospho-5) with a thickness of about 1μ formed by vapor phase growth method.
ilicate-Glass) gland.

Reference numerals 16 and 17 are contact holes made in 5 of the PSG films on the N-type regions 4 and 6, respectively. 18°19 is At
These lead-out wirings have ohmic contact with the N-type regions 4 and 6 through contact holes 16 and 17, respectively.

20.21 respectively? b A contact hole made in the middle of the PSG film 1 on the control gate electrode 10.14, 22.
21 is the At lead wiring of the open side cable 11.

Here, the floating cages x+13 and 12 in Figure 1 are the second
After patterning into the shape 24 shown with dots in the figure, the control gate polarization pattern 10.14 is used as a whole mask and the HE shape is determined in a self-intuitive manner (i.e., the sub-side 1 gate % polar pattern in plan view). (The floating gate electrode is formed only 1h below), so what are the dimensions of both gates along the channel force direction, that is, the A-A' direction? yo agrees. In addition, the N-type regions 4.5.6 are formed in a misaligned manner by the As ion implantation method using the mutually self-aligned l' and the gates as masks. . In this exemplary device, the areas between the floating gate [4Th and the channel region of the memory transistor (M) and the selection transistor (T) are S, = 25μ, S,: 50μ, respectively.
, floating gate) The areas between the 'III pole and the control gate electrode are both set to St "82 = 150 μ2, and Sz
/S1 ratio is S in the memory transistor (M).

/s1 = 6, S in the selection transistor (T), /
In 51-3, St/S1: St/s, =2. By setting such design parameters, when the same pressure voltage of 1 is applied to the electric bodies 22 and 23, the first gate S10 of the memory transistor (M) and the selection transistor (T). The electric field generated in the antinodes 7 and 11 is approximately 1.87 times stronger in the case of (M) than in the case of (T). In this semiconductor device, a positive voltage is applied to the gate electrode 22 of the memory transistor (M), and the electric field in the first gate 5iO1 film 7 causes a droplet to fall from the substrate 1 to the floating gate electrode 8.
Er-Nordheim (hereinafter abbreviated as F-N) tunnel injection is applied, and electrons are emitted from the floating gate electrode 8 to the substrate 1 through F-N) tunnels. At this time, even if the same positive and negative high voltages are applied to the gates 1M and 23 of the selection transistor (T), the first gate Since the field of Sin and 9- in the film 11 is winged, phenomena such as delayed injection and release do not occur, so the selection transistor ('r) has no memory effect and is just a switch. It can be made to function as a transistor. The memory transistor (M) described above (!: s4t< Blh 57 shi,
The differences in the characteristics of the data (T) are all shown in Figure 3. In this figure, the threshold voltage (-
In 2), the horizontal line 41111 indicates the voltage value (vcG) at the gate electrode, and at the input force 11 between the 10 m5 spaces.

When the real-phase memory transistor (M) has a t-domain, the breakage impairs the characteristics of the selection transistor ('r). As shown in the figure, only the threshold voltage (VTM) of the memory transistor (M) is shifted by using, for example, a positive voltage V and a negative voltage ratio V- for 'writing', 'erasing', and 'operations'. The selection transistor (T
) can be made to taste without any change in its characteristics.

It is clear from the above explanation that the ratio si/st :St
Katsura% by increasing /s+ ``Since the difference in memory window width for CG can be increased, the operation of the device becomes 110- more stable, but for actual use, it is sufficient that the above ratio is 1.5 times or more. It was confirmed that it is stable.

Is the above embodiment simply? It is clear from the above description that the present invention is not limited to this, but is for illustrative purposes only. For example, the conductivity type of the device valley and the manufacturing method can be changed, and there is a degree of freedom in selecting materials and dimensions within a certain range.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional cross-sectional view of an example of the semiconductor device of the present invention, and FIG. 2 is a plan view of the semiconductor device. FIG. 3 is a percentage explanatory diagram.

Claims (1)

[Claims] A pair of source and drain regions having opposite conductivity types to the substrate, which are adjacent to the surface of the required semiconductor substrate and spaced apart from each other; Gate 1111! ! a second gate insulating layer on the electrode, a floating gate made of a metal or semiconductor material on the insulating film and electrically insulated from other parts; 1] A stacked gate MO8 type memory transistor, which is made of a metal-polymerized material on the film, and which is connected to the gate electrode, and the memory provided adjacent to the memory transistor and connected in series on the same substrate. The transistor is equipped with a 1VIO8 type transistor for address selection having a cross-sectional structure of the same weight as the transistor. The shape of each source and drain region is determined to be roughly similar to each other along the two sides, and the respective source and drain regions are also shaped to be roughly similar to each other. and the ratio of the distance between the control gate 1 and the floating gate electrode and the volume between the base and the substrate is 1) when the bu i in the case of j memory transistor is removed. A semiconductor device characterized by being set 15 fingers or more larger than an address selection transistor.