JPS6074649A - Semiconductor ic device - Google Patents

Abstract

PURPOSE:To enable the wiring also of a logic LSI by a method wherein both of the N-layer metallic wiring (N>=2) and the M-layer metallic wiring (M>N) are used for a master. CONSTITUTION:When the wiring region of a master slice system LSI is wired by double-layer metallic wiring, the first layer metallic wiring 2-1 runs over a fixed wiring truck in a vertical direction, and the second metallic wiring 2-2 in a lateral direction. The aperture 2-3 of an insulation film between the wirings 2-1 and 2-2 is used for the electric connection of the wirings 2-1 and 2-2. A master wafer of metallic double-layer wiring and the wiring pattern (macro-cell data) in the logic gate can be used as they are, and the working of new design of the master pattern and the macro-cell library is unnecessary. In the case of the shortage in the wiring truck, another wiring is passed by superposition of a wiring 3-4 on the same truck as that of a wiring 3-1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit (hereinafter abbreviated as LSI), and particularly to a master slice type LSI.

[Technical background of the invention and its problems]

A master slice type LSI is also called a game I array, and a general-purpose cell consisting of a plurality of elements (including active elements such as transistors and passive elements such as resistors) is usually installed in one semiconductor chip in advance. A master wafer in which a large number of cells are formed in a matrix is prepared, and a wiring mask (including a metal wiring mask and an insulating layer opening mask) is prepared according to the product to be developed. A logic cell (gate) having a desired logic function is appropriately realized by combining these elements, and a plurality of these elements are further connected to complete the final LSI. Here, the process of manufacturing the master wafer is called a master process, and is realized using the same mask pattern regardless of the product type developed. However, in response to the diversity in the number of logic gates (scale) of the developed products, we have prepared multiple types of masters with different numbers of general-purpose cells as a master series. In addition, the process of manufacturing final LSI from a master wafer using a wiring mask for each developed product is called the personalization process, which normally includes two layers of metal wiring and a first insulating layer opening (contact) that connects the elements and metal wiring on the master wafer. hole), second insulating layer opening (VI
A hole) etc.

FIG. 1 shows an example of a chip layout of a master slice type LSI. In the figure, 1 "1 is an array of general-purpose cells, 1-
2 is the wiring area, J-s is the input/output cell, and No. 4 is the input/output cell.
Shows output pad.

The wiring area 1-2 is a logic circuit formed on a general-purpose cell (
In this area, the wiring runs on the wiring track in the wiring area 1-2. The number of wiring tracks in one grain distribution area varies depending on the master, and a master with a large number of general-purpose cells requires a large number of tracks. The table below shows the number of general-purpose cells, input/
Examples of combinations of the number of output pads and the number of wiring tracks are shown below, and a series of masters is called a master series.

18 as an example using a master series like this
00. Consider the case of realizing a general-purpose cell logic LSI.

In this case, even though the same 1800 general-purpose cells are used, a logic gate (inverter, two-man NOR) can be realized with fewer general-purpose cells.

Logic gates (flip 70, etc.) that cannot be realized without many general-purpose cells
The situation is quite different depending on the case where there are many shift registers, etc.). In the former case, the number of wiring nodes connecting the input/output terminals of the logic gate increases, and the wiring area becomes crowded. Furthermore, in extreme cases, the lack of wiring tracks may lead to a situation where wiring is impossible. In such a case, the previous layout device and wiring data must be discarded, a new master with one stage more general-purpose cells (therefore, the number of tracks) must be selected, and the layout and wiring must be redone. When realizing a logic LSI that uses 1800 general-purpose cells, in most cases it is sufficient to select the master with 2000 general-purpose cells in the table above, but in the above case, it is necessary to change to the master with 3000 general-purpose cells. It will not happen. In this case, not only will the subsequent design work that was done before switching to the 3000 general-purpose cell be wasted, but the completed LSI will also be approximately 4.
0% of transistors (general-purpose cells) are left unused, and as a result, the yield is reduced due to the increase in chip size, resulting in a very wasteful LSI. Next, in order to prevent stiffness, it is possible to increase the number of wiring tracks for each master in the table above from the beginning, but in most cases, the number of tracks in the current table above will remain the same. Since the wiring can be done using the same number of tracks, the chip size will be increased by the increased number of tracks.

That is, in order to eliminate waste in one logic LSI with a large number of wiring lines, waste is created in most other logic LSIs.

Even if three-layer metal wiring is used for wiring, the same problem will occur as long as the idea in the above table is that the wiring tracks of a master with a certain number of general-purpose cells are determined by the master.

As mentioned above, in the master slice type LSI according to the prior art, that is, in the Toiri type in which the upper limit of the number of general-purpose cells and the number of wiring tracks is fixed by the master,
A dilemma exists in that a large amount of waste occurs when implementing a part of the logic LEII with a large number of circuits, and in order to prevent this, waste occurs in all the other large number of logic LSIs.

[Purpose of the invention]

This invention solves the drawbacks of the master slice type LSI according to the prior art described above.
The purpose of the present invention is to provide a method that enables wiring.

[Summary of the invention]

This invention is realized by using both an N-layer metal wiring (where N≧2) and an M-layer metal wiring (where M)N ) for one master. That is, with the same master shown in Figure 1 and the table above, most logic L
SI is realized by two-layer metal wiring, but only when an LSI with a shortage of wiring tracks occurs, use third-layer metal wiring to make up for the lack of tracks, thereby avoiding the use of an upper master. [Effects of the Invention] According to the present invention, a disadvantage of the conventional method is that a large amount of money is wasted when realizing an LSI with a large number of wires in some parts, and in order to prevent this, it is necessary to LSI
This solves the dilemma that everything is wasted. And, without causing waste in a large number of normal LSIs, even for some LSIs with a large number of wires, almost all of the layout and wiring data before the lack of wiring tracks can be used. , ■ Minimizes the number of unused transistors (general-purpose cells) because the master is not switched to the next higher level, ■ Realizes an LSI with the following characteristics: Since the chip size does not increase, there is no yield loss due to chip size. Can be sewn on.

[Embodiments of the invention]

FIG. 2 shows the master slice method LS according to the present invention.
An example is shown in which wiring is provided in the wiring area I using two-layer metal wiring. 2-1 runs vertically on the wiring track defined by the first N/I metal wiring, and 2-2 runs horizontally on the second layer metal wiring.

Moreover, 2-3 is the above arrangement 1ilj! This layout method of the first layer metal/second layer metal wiring used for electrical connection between 2-1 and 2-2 through the opening in the insulating layer film between 2-1 and 2-2 is as follows: This method is also used in the conventional method using layered wire mesh wiring. That is, in the present invention, the master wafer of the conventional two-layer metal wiring and the wiring pattern in the logic gate (referred to as macrocell data) can be used as is, and new design work for the master pattern and macrocell library is not required. .

If there is a shortage of wiring tracks in the wiring shown in Figure 2, use the 3rd/@ wiring 3-4 as shown in Figure 3 and overlap it on the same track as the first layer metal wiring 3-1. Pass the wire through. In FIG. 3, 3-2 is the second layer metal wiring, 3-3 is the insulating layer opening connecting the first layer metal wiring 3-1 and the second layer metal wiring 3-2, and 3-5 is the second layer metal wiring. This is a second insulating layer opening for connecting layer metal wiring 8-2 and third layer metal wiring 3-4.

By using 3-layer metal in this way, a 3N metal wiring process is added to the personalization process, and 2
It is conceivable that the manufacturing cost will be somewhat higher than that of a logic LSI on the same master that is realized only by layers. However, this method is often more advantageous in consideration of the fact that it does not require redoing the process and the number of chips in the wafer (chip gross).

Furthermore, by using this method: :frfl:.

There is no need for master design work or macro cell design work at all, and once the manufacturing technology for realizing three-layer metal wiring has been established, this method can be applied directly to the master series for two-layer wiring. , it can be used as a master series with great flexibility.

Up to now, for convenience of explanation, examples using two-layer and three-layer metal wiring have been explained, but in general, N (≧2) layers and M
The same can be said of the (M>N) layer metal wiring. In other words, by using an appropriate number of wiring layers between the N-layer metal wiring and the M-layer metal wiring according to the number of wiring required for one master series, and realizing the final LSI, the Less waste.

It becomes possible to create a master series in terms of civility.

[Brief explanation of the drawing]

Figure 1 shows an example of a chip layout of a master slice type LSI, Figure 2 shows an example of a wiring method with two-layer metal wiring, and Figure 3 shows an example of a wiring method with three-layer metal wiring according to the present invention. FIG. 3 is a diagram showing an example of a wiring method. 1-1... General-purpose cell array, 1-2... Play area,
J-3... Input/output cell, 1-4... Input/output pad, 2-1. ．． 9-7...First layer metal wiring, 2-2.
3-2... Second layer metal wiring, 2-3.3-J... Insulating layer opening, 3-4... Third layer metal wiring 1. ,? −
5...Insulating layer opening. Applicant's agent Patent attorney Takehiko Suzue 11- Figure 1

Claims (1)

[Claims] (1) In a master slice type semiconductor integrated circuit device in which general-purpose cells including multiple transistors are integrated on a semiconductor chip in a matrix pattern and a desired logical function is realized by designing the wiring pattern, the wiring pattern is The master slice series realized with N-layer metal wiring (however, N-2) and the wiring pattern are M-layer metal wiring (however, M>
Between the master slice series realized by N),
A semiconductor integrated circuit device characterized by using a common master series.