JPS6074629A - Formation of thin film pattern - Google Patents
Formation of thin film patternInfo
- Publication number
- JPS6074629A JPS6074629A JP18218683A JP18218683A JPS6074629A JP S6074629 A JPS6074629 A JP S6074629A JP 18218683 A JP18218683 A JP 18218683A JP 18218683 A JP18218683 A JP 18218683A JP S6074629 A JPS6074629 A JP S6074629A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- resist
- substrate
- positive resist
- negative resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 230000015572 biosynthetic process Effects 0.000 title 1
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、基板上にポジ形レジストとネガ形レジストを
二重に塗布することＫより、高い歩留シで薄膜のパター
ンを形成する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming thin film patterns with a higher yield than double coating of a positive resist and a negative resist on a substrate.
従来この種のパターン形成方法は、レジストの端面が逆
テーバになっていないため、薄膜を堆積した後、レジス
トを除去して薄、膜をバターニングする際に、基板上に
残す薄膜も同時に除去される可能性が高かった。そのた
め薄膜パターンが設計値よりも小さくなった〕、断切れ
するという欠点があった。Conventionally, in this type of pattern forming method, the end face of the resist is not inverted tapered, so after depositing a thin film, when removing the resist and patterning the film, the thin film left on the substrate is also removed at the same time. There was a high possibility that As a result, the thin film pattern became smaller than the designed value] and had the disadvantage of being cut off.
本発明は、上記のよ５４欠点をなくすためになされたも
のであシ、ポジ形レジストとネガ形レジストを二重に塗
布し、端面を逆テーパ形に形成する工程の彼、薄ｇ’ｅ
堆積し、レンス）１−除去する工程を行うことによって
、歩留り良（薄膜をパターニングすることを目的とした
ものである。The present invention has been made in order to eliminate the above-mentioned 54 drawbacks.The present invention has been made in order to eliminate the above-mentioned 54 drawbacks.
The purpose is to pattern a thin film with a good yield by performing a step of depositing and removing a lens.
以下図面によって本発明の薄膜パターン形成方法の一例
を詳述する。An example of the thin film pattern forming method of the present invention will be explained in detail below with reference to the drawings.
第１図は、基板１の上にポジ形レジスト２を塗布し、続
いてネガ形レジスト３を塗布する工程でおる。基板１の
例としては、シリコン、石英などがあるが、他にも目的
に応じて使用できる。FIG. 1 shows a step in which a positive resist 2 is applied onto a substrate 1, and then a negative resist 3 is applied. Examples of the substrate 1 include silicon and quartz, but other materials can be used depending on the purpose.
ポジ形レジスト２は、い（つか種類があるが、ココでｉ
ｊ、０ＦＰＲ’ｉスピンコーターによシ厚さ０．８μ常
から約１μ常の間で塗布する。ネガ形レジスト３は、ポ
ジ形レジスト２と同様にいくつか種類があるが、ここで
は、’ＯＭＲ−８５をスピンコーターによシ厚さ０．８
μ常から約１μ淋の間で塗布する。There are several types of positive resist 2.
Coat with a spin coater to a thickness of between 0.8μ and about 1μ. Like the positive resist 2, there are several types of negative resist 3, but here we use 'OMR-85 with a spin coater to a thickness of 0.8
Apply between 1μ and 1μ.
第２ 図ｉｔ、 、ネガ形レジスト３をバターニングす
る工程である。ここでは、フォトリソグラフィ技術を使
った実施例について説明する。約９０℃で加分間のプリ
ベークを行なった後、マスクアライナ−で露光した後に
、現像し、バターニングする第３図は、ポジ形レジスト
２をマスクを使用せず全面露光した後、現像してバター
ニングする工程である。約９０℃でｍ分間のプリベーク
を行なった後、了ライナーを使用して、全面を露光する
。この時ネガ形レジスト３の除去された部分のポジ形レ
ジスト２は、十分露光、現像される。このため第３図に
示すように、ポジ形レジスト２の領域は、ネガ形レジス
ト３の領域よりも狭くなシ、逆テーパーの断面構造にな
る。FIG. 2 shows a step of patterning the negative resist 3. As shown in FIG. Here, an example using photolithography technology will be described. After pre-baking at about 90°C for an addition period, it is exposed with a mask aligner, then developed and buttered. Figure 3 shows the positive resist 2 is exposed entirely to light without using a mask, then developed. This is the process of buttering. After prebaking at about 90° C. for m minutes, the entire surface is exposed using a light liner. At this time, the portion of the positive resist 2 from which the negative resist 3 has been removed is sufficiently exposed and developed. Therefore, as shown in FIG. 3, the area of the positive resist 2 has a reverse tapered cross-sectional structure, which is narrower than the area of the negative resist 3.
箇４図は、薄膜４を均一に堆積する工程である。薄膜材
料は多数あるが、例としては、■ＴＯ（工ｎｄｉｗｍ
−Ｔ０ｎ −０ｗ１ｄｅ ） 、 Ａｔ−Ｓ ｉなどを
、スパッタ法により均一に堆積させる方法がある。この
際、薄膜４の膜厚は、ポジ形レジスト２の膜厚よシも薄
くする必要がある。Figure 4 shows the process of uniformly depositing the thin film 4. There are many thin film materials, examples include
-T0n-0w1de), At-Si, etc., can be uniformly deposited by sputtering. At this time, the thickness of the thin film 4 needs to be smaller than that of the positive resist 2.
第５図は、第４図のポジ形レジスト２、ネガ形レジスト
３を除去し、薄膜４を基板１上に残す工程である。たと
えばレジストの除去には、発煙硝酸を使う方法がある。FIG. 5 shows a step in which the positive resist 2 and negative resist 3 shown in FIG. 4 are removed, leaving the thin film 4 on the substrate 1. For example, one method for removing resist is to use fuming nitric acid.
以上実施例を述べてきたが、レジストと薄膜の、膜厚は
設計に応じて変えることができる。Although the embodiments have been described above, the film thicknesses of the resist and thin film can be changed depending on the design.
本発明は、第１図から第５図に示すように、ポジ形レジ
スト２とネガ形レジスト３とを二重に塗布し、逆テーパ
ー構造にするため、以下に述べる効果を有する。As shown in FIGS. 1 to 5, the present invention has the effects described below because the positive resist 2 and the negative resist 3 are coated in double layers to form a reverse tapered structure.
（１） レジストヲ除去した後の薄膜パターンは、途中
で切れたシ、小さくなることがなく、はぼ設計値どおり
のものが形成できるので、薄膜パターン形成の歩留りは
向上する。(1) After the resist is removed, the thin film pattern is not cut midway or becomes small, and can be formed exactly as designed, so the yield of thin film pattern formation is improved.
（２）第５図薄膜４の断面は、テーパー状になっている
ので、さらに他の薄膜を堆積した時に、第５図薄膜４の
ステップでのカバーが良くなる。(2) Since the cross section of the thin film 4 shown in FIG. 5 is tapered, when another thin film is deposited, the step of the thin film 4 shown in FIG. 5 can be covered well.
第１図から第５図までは、本発明の製造方法の工程順を
説明する几めの断面図である。
１゜、基板
２゜、ポジ形レジスト
３０．ネガ形レジスト
４゜、薄膜
以上
出願人 株式会社第二精工舎
代理人 弁理士最上 務
５−1 to 5 are detailed cross-sectional views illustrating the order of steps in the manufacturing method of the present invention. 1°, substrate 2°, positive resist 30. Negative resist 4°, thin film and above Applicant Daini Seikosha Co., Ltd. Agent Patent attorney Mogami Tsutomu 5-
Claims (1)
ストを塗布する工程と、前記ネガ形１ノジストヲ部分的
に露光現像しパターン形成する工程と、全面露光によシ
、前記ネガ形レジストの除去された部分のポジ形しンス
トヲ十分露光現像し、除去することで逆テーバのついた
端面ヲ有するレジストを形成する工程と、全面に薄膜を
堆積した後、前記ポジ形レジストとネガ形レジストとを
除去し、前記薄膜を前記基板上に残す工程とからなる薄
膜のパターン形成方法。A step of applying a positive resist on the substrate and further applying a negative resist, a step of partially exposing and developing the negative resist to form a pattern, and removing the negative resist by full exposure. A step of forming a resist having an inverted tapered end face by sufficiently exposing and developing the positive resist in the exposed portion, and depositing a thin film on the entire surface, and then forming the positive resist and the negative resist. A thin film pattern forming method comprising the steps of removing the thin film and leaving the thin film on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18218683A JPS6074629A (en) | 1983-09-30 | 1983-09-30 | Formation of thin film pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18218683A JPS6074629A (en) | 1983-09-30 | 1983-09-30 | Formation of thin film pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6074629A true JPS6074629A (en) | 1985-04-26 |
Family
ID=16113839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18218683A Pending JPS6074629A (en) | 1983-09-30 | 1983-09-30 | Formation of thin film pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6074629A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459918A (en) * | 1987-08-31 | 1989-03-07 | Nec Corp | Lift-off flattening process |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574127A (en) * | 1980-06-10 | 1982-01-09 | Fujitsu Ltd | Formation of conductor pattern |
-
1983
- 1983-09-30 JP JP18218683A patent/JPS6074629A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574127A (en) * | 1980-06-10 | 1982-01-09 | Fujitsu Ltd | Formation of conductor pattern |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6459918A (en) * | 1987-08-31 | 1989-03-07 | Nec Corp | Lift-off flattening process |
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