JPS6185824A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6185824A
JPS6185824A JP59208612A JP20861284A JPS6185824A JP S6185824 A JPS6185824 A JP S6185824A JP 59208612 A JP59208612 A JP 59208612A JP 20861284 A JP20861284 A JP 20861284A JP S6185824 A JPS6185824 A JP S6185824A
Authority
JP
Japan
Prior art keywords
photoresist
ultraviolet rays
pattern
far ultraviolet
sensitive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59208612A
Other languages
Japanese (ja)
Inventor
Masahide Nakajima
中島 正英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59208612A priority Critical patent/JPS6185824A/en
Publication of JPS6185824A publication Critical patent/JPS6185824A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form a fine pattern on a semiconductor with remarkable step difference part by a method wherein three phase photoresist comprising the first photoresist sensitive to far ultraviolet rays, the second photoresist insensitive to far ultraviolet rays and the third photoresist sensitive to far ultraviolet rays is utilized. CONSTITUTION:A semiconductor substrate 1 with step difference part is coated with the first photoresist 2 sensitive to far ultraviolet rays to flatten the surface thereof selecting the viscosity and coating frequency. After baking process, the photoresist 2 iscoated with the second photoresist 3 insensitive to far ultraviolet rays. After another baking process, the photoresist 3 is further coated with the third photoresist 12 sensitive to far ultraviolet rays. Then the third photorest 12 is exposed meeting the requirement for pattern forming process utilizing a photoresist mask 4 to form the first pattern. Next after exposing overall surface to normal ultraviolet rays, the photoresist 3 is developed to form the second pattern utilizing the first pattern as a mask. Finally after exposing overall surface to far ultraviolet rays, the photoresist 2 may be developed to form the final pattern utilizing the second pattern formed on the photoresist 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関しlに大きな段差を
有する半導体基板に微細パターンを形成する半導体装置
の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a fine pattern is formed on a semiconductor substrate having a large step.

〔従来の技術〕[Conventional technology]

通常のホトエツチング技術では、マスク上のパターンを
フォトレジスト層に転写するとき35’OO〜4500
人の紫外光を照射しているが、この場合の転写パターン
の解像度は使用する波長によシ決るため、工μm以下の
ようにより微細パターンとなると紫外光では転写が不可
能となる。最近では、より微細パターンの転写を行う丸
めに、よシ波長の短い1600〜2600人の遠紫外光
を用いる検討がなされ実用化が進んでいる。
With normal photoetching technology, when the pattern on the mask is transferred to the photoresist layer, the etching time is 35'OO~4500.
Although human ultraviolet light is irradiated, the resolution of the transferred pattern in this case depends on the wavelength used, so it is impossible to transfer finer patterns, such as micrometers or less, with ultraviolet light. Recently, studies have been conducted to use deep ultraviolet light with a shorter wavelength of 1,600 to 2,600 people for rounding to transfer finer patterns, and practical use is progressing.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した遠紫外光を用いてのパターンの転写は実用化が
進んだとは云え大きな段差を有する半導体基板上に遠紫
外at用いて1μm以下の微細パターンを形成しようと
すると、第3図に示すように、段差の下部の段差付近で
はフォトレジスト2が厚くなることと、段差の下部では
フォトマスク4とフォトレジスト20間にすき間が出来
、第4図に示すように所要のパターンを正確に形成する
ことができない。なお両図においてlは段差を有する半
導体基板である。
Although the practical application of pattern transfer using deep ultraviolet light as described above has progressed, when attempting to form a fine pattern of 1 μm or less using deep ultraviolet light on a semiconductor substrate with large steps, the pattern shown in Fig. 3 As shown in FIG. 4, the photoresist 2 becomes thick near the step at the bottom of the step, and a gap is created between the photomask 4 and the photoresist 20 at the bottom of the step, making it possible to accurately form the required pattern as shown in FIG. Can not do it. Note that in both figures, l represents a semiconductor substrate having a step.

フォトレジストの膜厚を充分に厚くすれば、半導体基板
表面の段差をカバーし、フォトレジストの表面を平坦化
することは可能であるが、厚いフすトレジス)l使用し
た場合は、露光量、現像時間を共に大幅に増さなければ
ならず、密着性を初めとするマスクの条件変動が大きく
影響し微細パターンの形成は困難となる。
If the film thickness of the photoresist is made sufficiently thick, it is possible to cover the steps on the surface of the semiconductor substrate and flatten the surface of the photoresist, but if a thick film resist is used, the exposure amount, Both require a significant increase in development time, and variations in mask conditions, including adhesion, have a large effect, making it difficult to form fine patterns.

本発明は上記問題点を解決し、大きな段差を有する半導
体基板に対して遠紫外線露光を用い、1μm以下の微細
パターンを形成する半導体装置の製造方法を提供するこ
とを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device in which a fine pattern of 1 μm or less is formed using deep ultraviolet exposure on a semiconductor substrate having large steps.

〔問題点を解決する丸めの手段〕[Rounding method to solve problems]

本発明の半導体装置の製造方法は、半導体基板表面に遠
紫外線に感光するフォトレジス)1塗布する工程と、該
フォトレジスト上に遠紫外線に感光しないフォトレジス
トtm布する工程と、前記2層フォトレジスト上に遠紫
外線に感光するフォトレジス)1塗布する工程とを含ん
で構成される3層フォトレジスト金使用し微細パターン
金形成することを特徴として構成される。
The method for manufacturing a semiconductor device of the present invention includes a step of coating a photoresist (TM) sensitive to deep ultraviolet rays on the surface of a semiconductor substrate, a step of disposing a photoresist (tm) that is not sensitive to deep ultraviolet rays on the photoresist, and a step of coating the photoresist TM which is not sensitive to deep ultraviolet rays on the surface of a semiconductor substrate. The method is characterized by forming a fine pattern of gold using a three-layer photoresist consisting of a step of coating a photoresist sensitive to deep ultraviolet rays on a resist.

〔実施例〕〔Example〕

以下、本発明の実施例について、図面を参照して説明す
る。第1図は本発明の一実施例全説明するための3層フ
ォトレジストの断面図であり、第2図1al〜taは本
発明の一実施例を説明するためのパターン形成工程を示
す断面図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a three-layer photoresist for explaining an embodiment of the present invention, and FIG. 2 1al to ta are cross-sectional views showing a pattern forming process for explaining an embodiment of the present invention. It is.

第1図に示すとおり、段差を有する半導体基板1上にP
MMA (ポリメチルメタアクリレート)の様な遠紫外
線に感光するフォトレジス)2t−塗布する。この際、
フォトレジスト2の粘度及び塗布回転数を選択し、フォ
トレジスト2の表面が平坦化されるようKする。次に上
層のフォトレジスト3を塗布する際にフォトレジストが
混合しない様に、ベークした後、遠紫外線に感光しない
フォトレジスト3を塗布する。このフォトレジスト3の
塗布膜厚は遠紫外を透過しないだけあればよい(例えば
シブレイ社製のAZ−1350では2000λ以上でよ
い)。次に、ベークした後、遠紫外線に感光するフォト
レジスト121に塗布しベークする。
As shown in FIG. 1, P is placed on a semiconductor substrate 1 having a step.
Apply a deep ultraviolet-sensitive photoresist such as MMA (polymethyl methacrylate) 2t. On this occasion,
The viscosity and coating rotation speed of the photoresist 2 are selected, and K is applied so that the surface of the photoresist 2 is flattened. Next, in order to prevent the photoresists from being mixed when applying the upper layer photoresist 3, after baking, a photoresist 3 that is not sensitive to deep ultraviolet rays is applied. The coating thickness of the photoresist 3 is sufficient as long as it does not transmit deep ultraviolet light (for example, AZ-1350 manufactured by Sibley Co., Ltd. may have a thickness of 2000λ or more). Next, after baking, the photoresist 121 sensitive to deep ultraviolet rays is coated and baked.

この最上層フォトレジスト12の膜厚は工程上の必要に
より自由に選択できるが、微細パターンを形成する場合
は薄い方がよい。次に、フォトレジストマスク4を用い
て最上層フォトレジスト12をパターン形成するに必要
な条件で露光する。
The film thickness of the top layer photoresist 12 can be freely selected depending on process requirements, but when forming a fine pattern, the thinner the film, the better. Next, using the photoresist mask 4, the uppermost photoresist 12 is exposed to light under conditions necessary to form a pattern.

この際フォトレジスト2の表面が平坦化されているため
、フォトレジスト12の表面も平坦になっており、フォ
トマスク4との間にすき間なく密着出来、かつ、フォト
レジスト12の膜厚は均一で充分に薄いため、最適の条
件で露光、現像が出来、1μm以下のパターンも容易に
形成できる。
At this time, since the surface of the photoresist 2 is flattened, the surface of the photoresist 12 is also flattened, so that it can be closely attached to the photomask 4 without any gaps, and the film thickness of the photoresist 12 is uniform. Because it is sufficiently thin, it can be exposed and developed under optimal conditions, and patterns of 1 μm or less can be easily formed.

次に、第2図111に示すように、フォトレジスト12
の現像を行いパターンを形成する。
Next, as shown in FIG. 2 111, the photoresist 12
is developed to form a pattern.

次に、第2図111に示すように、フォトレジスト12
に形成されたパターン金マスクにして、通常の紫外線を
全面露光した後、フォトレジスト3を現像し、パターン
を形成する。
Next, as shown in FIG. 2 111, the photoresist 12
After exposing the entire surface to normal ultraviolet rays using a patterned gold mask, the photoresist 3 is developed to form a pattern.

最後に、第2図111に示すように、フォトレジスト3
に形成されたパターンをマスクにして、遠紫外線を全面
露光した後、フォトレジスト2を現像し、パターンを形
成する。この際最上層フォトレジスト12は現像除去さ
れるが、何ら支障はない。
Finally, as shown in FIG. 2 111, the photoresist 3
Using the pattern formed in 1 as a mask, the entire surface is exposed to deep ultraviolet rays, and then the photoresist 2 is developed to form a pattern. At this time, the top layer photoresist 12 is removed by development, but there is no problem.

またフォトレジスト2の膜厚は非常に厚くなるにもかか
わらずマスクがフォトレジストに密着しているので露光
時のまわり込みがすくなく現像にあたっては露光部分以
外は他のフォトレジストに覆われていることなどから露
光、現像が充分に行なえることから、パターン形成は容
易である。
In addition, even though the film thickness of photoresist 2 is very thick, the mask is in close contact with the photoresist, so there is little wrap-around during exposure, and during development, the exposed area is covered with other photoresist. Pattern formation is easy because exposure and development can be carried out sufficiently.

さらに、フォトレジスト2の現像の際に、現像を過度に
行い、フォトレジスト3のパターンより広がったパター
ンを形成することが出来るという利点を有する。
Furthermore, when developing the photoresist 2, it has the advantage that it is possible to perform excessive development and form a pattern that is wider than the pattern of the photoresist 3.

〔発明の効果〕 以上説明したように、本発明によれば、大きな段差を有
する半導体基板表面に1μm以下の微細パターンを容易
に形成することができる。
[Effects of the Invention] As described above, according to the present invention, a fine pattern of 1 μm or less can be easily formed on the surface of a semiconductor substrate having a large step.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例全説明するための3層フォト
レジストの断面図、第2図1al〜+C1は本発明の一
実施例を説明するためのパターン形成工程を示す断面図
、第3図は従来方法のフr)レジスト露光を説明するた
めの断面図、第4図は従来方法により形成されたパター
ンの一例の平面図である。 1・・・・・・段差を有する半導体基板、  2.12
・・・・・・遠紫外線に感光するフォトレジスト、3・
・・・・・遠紫外線に感光しないフォトレジスト、4・
・・・・・フォトマスク。 代理人 弁理士  内 原   晋、 ;、、−1,l
ゞ・卒10
FIG. 1 is a sectional view of a three-layer photoresist for explaining an embodiment of the present invention, FIG. FIG. 3 is a sectional view for explaining resist exposure using the conventional method, and FIG. 4 is a plan view of an example of a pattern formed by the conventional method. 1... Semiconductor substrate having a step, 2.12
...Photoresist sensitive to far ultraviolet rays, 3.
...Photoresist that is not sensitive to deep ultraviolet rays, 4.
...Photomask. Agent: Susumu Uchihara, patent attorney ;,, -1,l
ゞ・Graduation 10

Claims (1)

【特許請求の範囲】[Claims]  半導体基板表面に遠紫外線に感光するフォトレジスト
を塗布する工程と、該フォトレジスト上に遠紫外線に感
光しないフォトレジストを塗布する工程と、前記2層フ
ォトレジスト上に遠紫外線に感光するフォトレジストを
塗布する工程とを含んで構成される3層フォトレジスト
を使用し微細パターンを形成することを特徴とする半導
体装置の製造方法。
A step of applying a photoresist sensitive to far ultraviolet rays on the surface of the semiconductor substrate, a step of applying a photoresist not sensitive to far ultraviolet rays on the photoresist, and a step of applying a photoresist sensitive to far ultraviolet rays on the two-layer photoresist. 1. A method for manufacturing a semiconductor device, comprising forming a fine pattern using a three-layer photoresist including a step of coating.
JP59208612A 1984-10-04 1984-10-04 Manufacture of semiconductor device Pending JPS6185824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59208612A JPS6185824A (en) 1984-10-04 1984-10-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59208612A JPS6185824A (en) 1984-10-04 1984-10-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6185824A true JPS6185824A (en) 1986-05-01

Family

ID=16559096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59208612A Pending JPS6185824A (en) 1984-10-04 1984-10-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6185824A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0433325A (en) * 1990-05-28 1992-02-04 Samsung Electron Co Ltd Photo etching for forming fine pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0433325A (en) * 1990-05-28 1992-02-04 Samsung Electron Co Ltd Photo etching for forming fine pattern

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