JPS6074564A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS6074564A JPS6074564A JP58180544A JP18054483A JPS6074564A JP S6074564 A JPS6074564 A JP S6074564A JP 58180544 A JP58180544 A JP 58180544A JP 18054483 A JP18054483 A JP 18054483A JP S6074564 A JPS6074564 A JP S6074564A
- Authority
- JP
- Japan
- Prior art keywords
- type
- substrate
- region
- element region
- channel
- Prior art date
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- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 230000000295 complement effect Effects 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体記憶装置に関し、特に周辺回路として相
補型ＭＯ８）ランジスタを用いた半導体記憶装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using complementary MO8 transistors as peripheral circuits.
従来、半導体記憶装置の周辺回路等として用いられる相
補型ＭＯ８）ランジスタ（０ＭＯ８）は第１図に示す構
造のものが知られている。即ち、図中１は例えばｎ型シ
リコン基板であり、この基板１表面にはｐウェル領域２
が選択的に設けられてい、る。前記シリコン基板１表面
にはｐウェル領域２とｐチャンネルトランジスタとなる
領域を分離するためのフィールド酸化膜３が設けられて
いる。なお、前記フィールド酸化膜３と接するｎ型シリ
コン基板１の界面にはｎ−型の反転防止層４が設けられ
ておシ、かつ同酸化膜３と接するｐウェル領域２の界面
にはｐ−型の反転防止層５が設けられている。前記フィ
ールド酸化膜３で分離された島状の基板１領域表面には
互に電気的に分離されたｐ中型のソース、ドレイン領域
６１＋７１が設けられておシ、かつこれら領域６１＋７
１ 間のチャンネル領域を少なくとも含む基板１上には
ダート酸化膜８１を介してダート電極９里が設けられて
いる。こうしたソース、ドレイン領域６１１７１、ダー
ト電極９１等によりｐチャンネルＭＯ８）ランジスタが
構成される。また、前記ｐウェル領域２の表面には互に
電気的に分離されたｎ中型のソース、ドレイン領域６２
＋７寞が設けられておシ、かつこれら領域６２ｒ７２間
のチャンネル領域を少なくとも含むｐウェル領域２上に
はｙ−ト酸化膜８２を介してｒ−）電極９ｚが設けられ
ている。こうしたソース、ドレイン領域６’ｌｌ ＋
７倉、ダート電極９２等によシイチャンネルＭＯ８）ラ
ンジスタが形成される。なお、前記ｐ十型ソース領域６
１は電源端子ｖＤＤに、ｎ生型ソース領域６、は接地端
子ＶＩＢＩＩに、各ゲート電極９１．９２は入力端子Ｖ
ｉｎに、各ドレイン領領７１＋７２は出力端子Ｖｏｕｔ
に、夫々接続されている。2. Description of the Related Art Conventionally, a complementary MO8 transistor (0MO8) used as a peripheral circuit of a semiconductor memory device has a structure shown in FIG. 1. That is, 1 in the figure is, for example, an n-type silicon substrate, and a p-well region 2 is formed on the surface of this substrate 1.
are provided selectively. A field oxide film 3 is provided on the surface of the silicon substrate 1 to separate a p-well region 2 from a region that will become a p-channel transistor. An n-type anti-inversion layer 4 is provided at the interface of the n-type silicon substrate 1 in contact with the field oxide film 3, and a p- type inversion prevention layer 4 is provided at the interface of the p-well region 2 in contact with the field oxide film 3. A mold reversal prevention layer 5 is provided. P medium type source and drain regions 61+71 electrically isolated from each other are provided on the surface of the island-shaped substrate 1 region separated by the field oxide film 3, and these regions 61+7
A dirt electrode 9 is provided on the substrate 1 including at least a channel region between 1 and 2 through a dirt oxide film 81. These source and drain regions 61171, dirt electrode 91, etc. constitute a p-channel MO8) transistor. Further, on the surface of the p-well region 2, there are n medium-sized source and drain regions 62 electrically isolated from each other.
An r-) electrode 9z is provided on the p-well region 2, which includes at least the channel region between these regions 62r72, via the y-toxide film 82. These source and drain regions 6'll +
A channel MO8) transistor is formed by the dirt electrode 92 and the like. Note that the p-type source region 6
1 is connected to the power supply terminal vDD, the n-type source region 6 is connected to the ground terminal VIBII, and each gate electrode 91 and 92 is connected to the input terminal V
In, each drain region 71+72 is an output terminal Vout
are connected to each other.
しかしながら、上述した第１図図示の０ＭＯ８にあって
は、シリコン基板１にウェル領域２やソース、ドレイン
領域６１ ＋ ６２ ＋ ７１ ＋ ｙ＝等の異種導電
型の拡散層が設けられているため、ｎｐｎ 、 ｐｎｐ
形のバイポーラトランジスタが形成され、これが互につ
ながって、ｐｎｐｎ構造を持つ寄生サイリスタを構成す
る。具体的にはｎ型シリコン基板１をコレクタ、ｐウェ
ル領域２をペース、ｎ十型ソース領域６２（又はｎ十型
ドレイン領域７□ ）をエミッタとする縦型ｎｐｎ ）
ランジスタ１０が形成され、０ＭＯ８特有の低濃度のｐ
ウェル領域２（ｆ＝１００−ｃｍ＋ ｘｊ＝１０μｍ）
をベースとするため、大きな電流増幅率（ｈＦド、：２
００）を持ち易く、これが外部からの雑音によってラッ
チアップし易い寄生サイリスタを生みだす主原因とな＃
）０ＭＯ８の誤動作や破壊を引き起こす問題を生じる。However, in the 0MO8 shown in FIG. 1 described above, since the silicon substrate 1 is provided with diffusion layers of different conductivity types such as the well region 2 and the source and drain regions 61 + 62 + 71 + y=, npn, pnp
bipolar transistors are formed, which are interconnected to form a parasitic thyristor with a pnpn structure. Specifically, it is a vertical npn with the n-type silicon substrate 1 as the collector, the p-well region 2 as the base, and the n-type source region 62 (or n-type drain region 7) as the emitter.
A transistor 10 is formed, and a low concentration of p, unique to 0MO8, is formed.
Well region 2 (f = 100-cm + xj = 10 μm)
Because it is based on
00), which is the main cause of parasitic thyristors that tend to latch up due to external noise.
) 0 This will cause problems that may cause malfunction or destruction of the MO8.
このようなことから、本発明者らは第２図に示す構造の
０ＭＯ８を既に提案した。即ち、図中の１１はｎ型シリ
コン基板でアシ、この基板１１上には例えば８１０２か
らなる素子分離領域１２が設けられている。この素子分
離領域１２で分離された２つの島状基板領域にはｎ型単
結晶シリコン層からなるｎ型素子領域１３及びｐ型単結
晶シリコン層からなるｐ型素子領域１４が夫々埋め込ま
れている。また、これら素子領域１３゜１４と基板１１
との界面には薄い酸化層１５１゜１５２が夫々介在され
ている。前記ｎ型素子領域１３の表面には互に電気的に
分離されたｐ十型のソース、ドレイン領域”１ ｒ１７
１が設けられておシ、かつこれら領域１６１ ＋ １７
１間のチャンネル領域を含むｎ型素子領域１３上にはダ
ート酸化膜１８１を介してｆ−）電極１９１が設けられ
ている。こうしたソース、ドレイン領域１６１＊１１１
、？”−ト電極１９１等によりｐチャンネルＭＯ８）ラ
ンジスタが構成される。For this reason, the present inventors have already proposed 0MO8 having the structure shown in FIG. That is, 11 in the figure is an n-type silicon substrate, and on this substrate 11, an element isolation region 12 made of, for example, 8102 is provided. An n-type device region 13 made of an n-type single-crystal silicon layer and a p-type device region 14 made of a p-type single-crystal silicon layer are buried in the two island-like substrate regions separated by the device isolation region 12, respectively. . In addition, these element regions 13° 14 and the substrate 11
Thin oxide layers 151 and 152 are respectively interposed at the interfaces. On the surface of the n-type element region 13, p-type source and drain regions "1 r17 are electrically isolated from each other.
1 is provided, and these areas 161 + 17
An f-) electrode 191 is provided on the n-type element region 13 including the channel region between 1 and 2 with a dirt oxide film 181 interposed therebetween. These source and drain regions 161*111
,? A p-channel MO8) transistor is configured by the negative electrode 191 and the like.
また、前記ｐ型素子領域１４の表面には、互に電気的に
分離されたｎ＋型のソース、ドレイン領域１６２１２７
２が設けられており、かつこれらソース、ドレイン領域
１６２ 、ｌ’ｌ、間のチャンネル領域を含むｐ型素子
領域１４上にはダート酸化膜１８２を介してダート電極
１９２が設けられている。こうしたソース、ドレイン領
域１６２＊１’７２、””−ト電極１９２等によシ５−
ｎチャンネルＭＯ８）ランジスタが構成されている。か
かる構造によれば、ｐチャンネル、ｎチャンネルのＭＯ
Ｓ ）ランジスタが造られるｎ型、ｐ型の素子領域１３
．１４と基板１１の界面には薄い酸化層１５１，１５．
が介在されているため、寄生バイポーラトランジスタの
形成が阻止、され、これによってラッチアップ現象のな
い良好な素子特性を有する０ＭＯ８を得ることができる
。Further, on the surface of the p-type element region 14, n+ type source and drain regions 162127 are electrically isolated from each other.
A dirt electrode 192 is provided via a dirt oxide film 182 on the p-type element region 14 including the channel region between the source and drain regions 162 and l'l. The source and drain regions 162*1'72, the negative electrode 192, etc. constitute an n-channel MO8 transistor. According to this structure, p-channel, n-channel MO
S) N-type and p-type element regions 13 where transistors are made
．． 14 and the substrate 11 are thin oxide layers 151, 15.
is interposed, the formation of a parasitic bipolar transistor is prevented, thereby making it possible to obtain an 0MO8 having good device characteristics without latch-up phenomenon.
しかしながら、前述した第２図図示の０ＭＯ８をそのま
まダイナミックＲＡＭの周辺回路としてメモリセルに併
設すると、次のような問題を生じる。これを第３図を参
照して説明する。第３図中の２０はｐ型素子領域１４に
隣接する島状基板領域に埋込まれたｐ型単結晶シリコン
層からなるｐ型素子領域である。この素子領域２０上の
大部分の領域には薄い酸化膜２１を介してキイ／４’シ
タ電極２２が設けられている。このキヤ・（シタ電極２
２下の素子領域２０表面にはｎ″″型拡散拡散層２３け
られておシ、かつ該拡散層６−
２３から所望距離へだてた同素子領域２０表面には針量
拡散層２４が設けられている。また、図中の２５はトラ
ンスファーゲート電極であシ、このダート電極２５は一
部が前記ｎ−型拡散層２３とｎ生型拡散層２４の間に形
成されたダート酸化膜２６を介して前記素子領域２０表
面上に位置し、他端が酸化膜２７を介して前記キャパシ
タ電極２２上に延出している。こうしたキャパシタ電極
２２、トランスファダート電極２５等によシダイナミッ
クＲＡＭのメモリセルが構成されている。このような構
造において、メモリセルが造られるｐ型素子領域２０に
α線２８が入射されると、同素子領域２０内にエレクト
ロンが発生するが、素子領域２０と基板１ノの界面にも
薄い酸化層１５３が介在されているため、発生したエレ
クトロンの基板１１側への移行が酸化層１５３によシ阻
止される。このため、エレクトロンの大部分はキャパシ
タ電極２２上のｎ−拡散層２３に集まυ、その状態が反
転する等のソフトエラーを誘発する。したがって、α線
に対して極めて弱いという欠点があった。However, if the above-mentioned 0MO8 shown in FIG. 2 is directly attached to a memory cell as a peripheral circuit of a dynamic RAM, the following problem will occur. This will be explained with reference to FIG. Reference numeral 20 in FIG. 3 is a p-type element region made of a p-type single crystal silicon layer buried in an island-like substrate region adjacent to the p-type element region 14. A key/4' gate electrode 22 is provided over most of the element region 20 with a thin oxide film 21 interposed therebetween. This front electrode (bottom electrode 2)
An n'''' type diffusion layer 23 is provided on the surface of the element region 20 below 2, and a stylus diffusion layer 24 is provided on the surface of the element region 20 extending at a desired distance from the diffusion layer 6-23. ing. Further, 25 in the figure is a transfer gate electrode, and a part of this dirt electrode 25 passes through the dirt oxide film 26 formed between the n-type diffusion layer 23 and the n-type diffusion layer 24. It is located on the surface of the element region 20, and the other end extends onto the capacitor electrode 22 via the oxide film 27. The capacitor electrode 22, transfer dart electrode 25, etc. constitute a memory cell of the sidynamic RAM. In such a structure, when α rays 28 are incident on the p-type element region 20 where a memory cell is formed, electrons are generated within the element region 20, but there is also a thin interface between the element region 20 and the substrate 1. Since the oxide layer 153 is provided, the oxide layer 153 prevents the generated electrons from moving toward the substrate 11 side. Therefore, most of the electrons gather in the n-diffusion layer 23 on the capacitor electrode 22, inducing soft errors such as inversion of the state. Therefore, it has the disadvantage of being extremely weak against alpha rays.
本発明はラッチアップ現象の防止と、ソフトエラーの抑
制とを達成した高性能、高信頼性の半導体記憶装置を提
供しようとするものである。The present invention aims to provide a high-performance, highly reliable semiconductor memory device that achieves prevention of latch-up phenomena and suppression of soft errors.
本発明は第１導電型の半導体基板と、この基板上に設け
られた絶縁材料からなる素子分離領域と、この素子分離
領域によシ分離された複数の島状基板領域に夫々埋込ま
れた第１導電型、第２導電型いずれかの単結晶半導体層
からなる素子領域とを具備し、前記素子領域のうちメモ
リセル部となる素子領域を前記基板と直接接するように
設け、かつ前記素子領域のうち周辺回路としての相補型
ＭＯ８）ランジスタを構成する互に導電型の異なる隣シ
合う素子領域の少なくとも一方の基板との界面の一部も
しくは全部に絶縁層を介在させたことを特徴とするもの
である。とうした本発明によれば既述の如くラッチアッ
プ現象の防止と、ソフトエラーの抑制とが図られた高性
能、高信頼性の半導体記憶装置を得ることができる。The present invention includes a semiconductor substrate of a first conductivity type, an element isolation region made of an insulating material provided on this substrate, and a plurality of island-shaped substrate regions separated by this element isolation region. an element region made of a single crystal semiconductor layer of either a first conductivity type or a second conductivity type; an element region of the element region that becomes a memory cell portion is provided in direct contact with the substrate; Complementary type MO as a peripheral circuit in the region 8) An insulating layer is interposed in part or all of the interface with the substrate of at least one of adjacent element regions of mutually different conductivity types constituting a transistor. It is something to do. According to the present invention, as described above, it is possible to obtain a high performance, highly reliable semiconductor memory device in which the latch-up phenomenon is prevented and soft errors are suppressed.
以下、本発明の実施例を第４図を参照して説明する。な
お、前述した第３図と同様な部材は回付号を付して説明
を省略する。Embodiments of the present invention will be described below with reference to FIG. Incidentally, the same members as those shown in FIG. 3 described above are given reference numbers and their explanations are omitted.
本発明のダイナミックメモリは第４図に示す如くメモリ
セルが造られたｐ型素子領域２０をｎ型シリコン基板１
１に直接接するようにし、かつｐチャンネル、ｎチャン
ネルのＭＯＳトランジスタが造られたｎ型、ｐ型の素子
領域１３゜１４と基板１１の界面に薄い酸化層１５１＋
Ｊ５２を夫々設けた構造になっている。In the dynamic memory of the present invention, as shown in FIG.
A thin oxide layer 151+ is formed at the interface between the substrate 11 and the n-type and p-type device regions 13° 14 in which p-channel and n-channel MOS transistors are formed.
It has a structure in which J52 is provided respectively.
このような構成によれば、α線がメモリセル部のｐ型素
子領域２０に入射して、エレクトロンが発生した場合、
前記ｐ型素子領域２０はｎ型シリコン基板１１に直接接
触しているため、発生したエレクトロンはそれらのｐｎ
接合の電位差によｐｎ型シリコン基板１１に吸い込まれ
ソフトエラーが抑制される。また、ｐチャンネル、９−
ｎチャンネルのＭＯＳ ）ランジスタが形成されたｎ型
、ｐ型の素子領域１３．１４とシリコン基板１１の界面
には薄い酸化層１５１ ＋ １５２が介在されているた
め、寄生バイポーラトランジスタの形成が阻止され、こ
れによってラッチアップ現象のない良好な素子特性を有
する０ＭＯ８の周辺回路を得ることができる。According to such a configuration, when α rays are incident on the p-type element region 20 of the memory cell portion and electrons are generated,
Since the p-type element region 20 is in direct contact with the n-type silicon substrate 11, the generated electrons
The potential difference between the junctions causes soft errors to be absorbed into the pn type silicon substrate 11 and suppressed. In addition, since thin oxide layers 151 + 152 are interposed at the interface between the silicon substrate 11 and the n-type and p-type element regions 13 and 14 in which p-channel and 9-n channel MOS transistors are formed, parasitic The formation of bipolar transistors is prevented, thereby making it possible to obtain a 0MO8 peripheral circuit free from latch-up and having good device characteristics.
上記実施例では０ＭＯ８を構成するｎ型、ｐ型の素子領
域とシリコン基板の界面の両方に薄い酸化層を介在させ
た構造にしたが、これに限定されない。例えば第５図に
示す如くｐチャンネルＭＯ８）ランジスタが形成される
ｎ型素子領域１３と基板１１の界面のみに薄い酸化層１
５１を介在する構造にしてもよい。In the above embodiment, the structure is such that a thin oxide layer is interposed between both the n-type and p-type element regions constituting the 0MO8 and the interface between the silicon substrate, but the structure is not limited thereto. For example, as shown in FIG. 5, a thin oxide layer 1 is formed only on the interface between the substrate 11 and the n-type element region 13 where the transistor is formed.
51 may be interposed.
本発明は上記実施例の如くダイナミックＲＡＭに限らず
、スタティックＲＡＭ 、 ＥＰＲＯＭ等の他の半導体
記憶装置にも同様に適用できる。The present invention is not limited to dynamic RAM as in the above embodiment, but can be similarly applied to other semiconductor memory devices such as static RAM and EPROM.
以上詳述した如く、本発明によればメモリセル部でのソ
フトエラーの抑制と、周辺回路とし１０−
ての０ＭＯ８のラッチアップ現象の防止とを達成した高
性能、高信頼性の半導体記憶装置を提供できる。As detailed above, according to the present invention, there is provided a high-performance, highly reliable semiconductor memory device that suppresses soft errors in the memory cell section and prevents latch-up of 10-0 MO8 as a peripheral circuit. can be provided.
第１図は従来の０ＭＯ８を示す断面図、第２図は本出願
人が既に提案した０ＭＯ８を示す断面図、第３図は第２
図図示の０ＭＯ８をそのままダイナミックＲＡＭの周辺
回路としてメモリセルに併設した状態を示す断面図、第
４図は本発明の一実施例を示すダイナミックＲＡＭの断
面図、第５図は本発明の他の実施例を示すダイナミック
ＲＡＭの断面図である。
１１・・・ｎ型シリコン基板、１２・・・素子分離領域
、１３・・・ｎ型素子領域、１４．２０・・・ｐ散票領
域、１５１．１５１・・・薄い酸化層、１６１ 。
１６！・・・ソース領域、１７１，１７１・・・ドレイ
ン領域、１８１．１８２・・・ダート酸化膜、１９１゜
１９、・・・ダート電極、２２・・・キャパシタ電極、
２５・・・トランスファーゲート電極。
１１−Fig. 1 is a sectional view showing the conventional 0MO8, Fig. 2 is a sectional view showing the 0MO8 already proposed by the applicant, and Fig. 3 is a sectional view showing the 0MO8 already proposed by the applicant.
4 is a sectional view of a dynamic RAM showing one embodiment of the present invention, and FIG. 5 is a sectional view of another embodiment of the present invention. 1 is a cross-sectional view of a dynamic RAM showing an example. DESCRIPTION OF SYMBOLS 11... N-type silicon substrate, 12... Element isolation region, 13... N-type element region, 14.20... P scatter region, 151.151... Thin oxide layer, 161. 16! ... Source region, 171,171 ... Drain region, 181.182 ... Dirt oxide film, 191°19, ... Dirt electrode, 22 ... Capacitor electrode,
25...Transfer gate electrode. 11-
Claims (1)
縁材料からなる素子分離領域と、この素子分離領域によ
シ分離された複数の島状基板領域に夫々埋込まれた第１
導電型、第２導電型いずれかの単結晶半導体層からなる
素子領域とを具備し、前記素子領域のうちメモリセル部
となる素子領域を前記基板と直接接するように設け、か
つ前記素子領域のうち周辺回路としての相補型ＭＯ８）
ランジスタを構成する互に導電型の異なる隣シ合う素子
領域め□少なくとも一方の基板との界面の一部もしくは
全部に絶縁層を介在させたことを特徴とする半導体記憶
装置。A semiconductor substrate of a first conductivity type, an element isolation region made of an insulating material provided on this substrate, and a first semiconductor substrate embedded in each of a plurality of island-shaped substrate regions separated by this element isolation region.
an element region made of a single crystal semiconductor layer of either a conductivity type or a second conductivity type; an element region of the element region that becomes a memory cell portion is provided in direct contact with the substrate; Complementary MO8 as a peripheral circuit)
A semiconductor memory device characterized in that an insulating layer is interposed in part or all of the interface between adjacent element regions of different conductivity types constituting a transistor and at least one of the substrates.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58180544A JPS6074564A (en) | 1983-09-30 | 1983-09-30 | Semiconductor memory device |
| EP84108241A EP0134504B1 (en) | 1983-07-15 | 1984-07-13 | A c-mos device and process for manufacturing the same |
| DE8484108241T DE3478170D1 (en) | 1983-07-15 | 1984-07-13 | A c-mos device and process for manufacturing the same |
| US07/478,044 US5079183A (en) | 1983-07-15 | 1989-01-06 | C-mos device and a process for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58180544A JPS6074564A (en) | 1983-09-30 | 1983-09-30 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6074564A true JPS6074564A (en) | 1985-04-26 |
Family
ID=16085128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58180544A Pending JPS6074564A (en) | 1983-07-15 | 1983-09-30 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6074564A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5518005A (en) * | 1978-07-25 | 1980-02-07 | Toshiba Corp | Mos-type dynamic memory |
| JPS5662369A (en) * | 1979-10-26 | 1981-05-28 | Toshiba Corp | Mos semiconductor device |
| JPS57194565A (en) * | 1981-05-25 | 1982-11-30 | Toshiba Corp | Semiconductor memory device |
| JPS5840851A (en) * | 1981-09-03 | 1983-03-09 | Toshiba Corp | Complementary metal oxide semiconductor device and its manufacture |
-
1983
- 1983-09-30 JP JP58180544A patent/JPS6074564A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5518005A (en) * | 1978-07-25 | 1980-02-07 | Toshiba Corp | Mos-type dynamic memory |
| JPS5662369A (en) * | 1979-10-26 | 1981-05-28 | Toshiba Corp | Mos semiconductor device |
| JPS57194565A (en) * | 1981-05-25 | 1982-11-30 | Toshiba Corp | Semiconductor memory device |
| JPS5840851A (en) * | 1981-09-03 | 1983-03-09 | Toshiba Corp | Complementary metal oxide semiconductor device and its manufacture |
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