JPS6074454A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6074454A
JPS6074454A JP18113783A JP18113783A JPS6074454A JP S6074454 A JPS6074454 A JP S6074454A JP 18113783 A JP18113783 A JP 18113783A JP 18113783 A JP18113783 A JP 18113783A JP S6074454 A JPS6074454 A JP S6074454A
Authority
JP
Japan
Prior art keywords
film
region
resist
window
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18113783A
Other languages
Japanese (ja)
Inventor
Shinji Sugaya
慎二 菅谷
Akihiro Nakagawa
中川　明宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18113783A priority Critical patent/JPS6074454A/en
Publication of JPS6074454A publication Critical patent/JPS6074454A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Abstract

PURPOSE:To contrive accomplishment of the state of high density by a method wherein a lithographic process is performed on a field oxide region and a channel stop region using the mask consisting of a single layer. CONSTITUTION:An SiO2 film 22 to be used as a buffer film, an Si3N4 film 23 to be used as an oxidation-resisting mask, and a resist 24 are formed on a P type substrate 21, and a window to be used for formation of a field oxide region is formed on the film 23. Then, a resist 25 is applied thereon. Subsequently, said resists 24 and 25 are removed until the film 22 is exposed. Then, a P<+> type channel stop region 26 is formed by implanting B<+> ions. Then, said resists 24 and 25 are removed, and a field oxidatin is performed on the film 23.

Description

【発明の詳細な説明】 （ａ）１発明の技術分野 本発明は高耐圧、高速のＭＩＳ素子を有する半導体装置
の製造工程におりるフィールド酸化膜とチャンネル・ス
トップ領域の形成に関−セｒ畳）のこある。Detailed Description of the Invention (a) 1 Technical Field of the Invention The present invention relates to the formation of field oxide films and channel stop regions in the manufacturing process of semiconductor devices having high breakdown voltage and high speed MIS elements. There are tatami mats.

（ｈ）、技術の１！ｉ′景 集積回路を構成するＭＩＳ素ヂ間の５３’　Ｆａｌｌ　
６’、二１．Ａ’、　ｊｎ雷フィール１゛酸化膜とチャ
ンネル・スＬ　ｙゾ領１・（が用いられ、いづれも隣接
する素子間（、＝設りイ゛、わている。隣接する２つの
素ｒのソースまたＬ；ｌ：　ｌ’　１イン領域の分離部
分に近い方の領域と分！Ｔｉ１１部５）１を覆う絶縁膜
を介ξ２て導電膜が形成されているソコめ、分冊部分Ｇ
こ寄生のＭＩＳ翠了が構成される。(h), Technology 1! 53' Fall between the MIS elements that constitute the i'view integrated circuit
6', 21. A', jn lightning field 1゛ oxide film and channel layer 1. Source L; l: l' 1 Region near the separation part of the in region! Ti11 part 5) A conductive film is formed through the insulating film ξ2 covering 1, the separate part G
A parasitic MIS Suiryo is constructed.

フィー月利・酸化膜は膜を厚＜シ、こ寄Ｉ：１゛素ｒに
Ｉ）　Ｌ、、きい値電圧を大きくし７て分離部分の導ｊ
１ｎを防＋１・し７、またチャンネル　ストップ領域は
１と板と同型のｆ・鈍物を濃く導入されているため、’
？ｉ’Ｆ’ｌ’卑ｉ′のり一ト下のチャンネル形成をＩ
！Ｉｉ、　、ＩＪ：：　Ｌ、、、（ｊｔっで４月）１１
部５３の導通を防止している。The thickness of the oxide film is less than 1, and the threshold voltage is increased to increase the conductivity of the separated part.
1n is +1・7, and the channel stop area is heavily populated with f・blunt objects of the same type as 1 and the plate, so '
? i'F'l'base i' Channel formation below the glue I
! Ii, , IJ:: L,,, (jtt in April) 11
This prevents the portion 53 from becoming electrically conductive.

一１投メモリのＭＩＳ素子のフィ　ル１ｍ化領ｌ・・（
とチャンネル・ストップ領１戎の配置を１−１，１弓′
ネルＭＯ３素７−にりいて第１図に示１．図は゛１′智
体基板の断面要部を示し、１し１ｐ型シリｌン（憤）基
板で、ｐ＋型　チャンネル・ストップ領域２は不純物と
してポロン・イオン（Ｂ＋）が注入されて、フィールド
酸化領域３の直下に、該領域と同じ面積で形成される。Fill 1m area of MIS element of 11-throw memory...(
and the arrangement of channel stop area 1 1-1, 1 bow'
Figure 1 shows 1. The figure shows the main cross-sectional part of the 1' intelligent body substrate. 1-1 is a p-type silicon substrate, and the p+-type channel stop region 2 is implanted with boron ions (B+) as an impurity and field oxidized. It is formed directly under region 3 and has the same area as the region.

またＭＯ３素子のソースまたはドレイン領域４はフィー
ル１゛酸化膜の境界迄不純物が導入されて形成されるた
め２，４の円領域は相接触し、従ってソースまたはドレ
インの耐圧は低く、接合容量が大きくなり、動作速度を
小さくしている。In addition, the source or drain region 4 of the MO3 element is formed by introducing impurities up to the boundary of the field 1 oxide film, so the circular regions 2 and 4 are in contact with each other, so the withstand voltage of the source or drain is low and the junction capacitance is low. It becomes larger and reduces the operating speed.

ＢＰ’−ＲＯＭ（消去可能なプロゲラ−７プル・リード
・オンリ・メモリ）のように高耐圧、高速動作が要求さ
れる場合はフィールド酸化？Ｉｌ′ｉ域の内側にチャン
ネル・ストップ領域を形成し、該領域と隣接する素子を
分離する必要がある。Field oxidation when high voltage resistance and high speed operation are required, such as BP'-ROM (Erasable Progera-7 Pull Read Only Memory)? It is necessary to form a channel stop region inside the Il'i region to isolate devices adjacent to this region.

（Ｃ）、従来技術の問題点 高耐圧、高速素子のフィールｌ”　ｒ＠化領領域チャン
ネル・ストップ領域を形成のため、従来はフィールド酸
化領域を画定するマスクとチャンネル・ストップ領域を
画定するマスクの２層のマスクを用い、２回のフメト・
プロセスにより円領域を形成し７ている。いま第２図に
よりｎ−チャンネルＮ４０Ｓ素子を例にとり工程順に説
明すで）と第２図（ａｌで１１はｐ型Ｓｉ基板、１２は
緩ｉチｊ膜とし、ての酸化シリコン（ＳｉＯ２）膜、１
３は耐酸化マスク膜としての窒化シリコン（Ｓｉ：＋　
Ｎ＋　）膜で該■１日、ｒフィール１酸化領域を画定す
るマスクを用いて窓あけを行った状態を図示する。つぎ
に第２１ツ１（ｂｌに４ンいてレジスト］４を全面塗布
し、チャンネル　ストップ領域を画定するマスクを用い
て窓ｒｊ）’ｒＪを行い、不純物イオン■３＋を注入し
２こ千トン了ル　ストップ領域１５を形成する。つぎに
第２図（Ｃ１ｔ；Ｉ、Ｌ・ジスＩ・１４を除去ｌ＆耐酸
化マスクＩｌ’ｌ　Ｉ　：３をｌ−４りにしてフィール
ド酸化膜１６を形成し７だ状態をしめず。この場合２回
のフォト・ゾＩロ！スを経過−４るので、工程の安定化
　η：産の高収率化の人うろ、工程の簡略化が要望され
る。またフイ　列用ｍ化Ｎｉ１５とチャンネル　ストッ
プ領域の間Ｆ７Ｍ　Ｌ；ｌ　／ソ、／）工程のパタニン
グ精度で制約をうり、３１ト導体装置の高密度化の面か
ら、該間隔を必要最小限に設定できるような改善がＩビ
・要となる。(C) Problems with the Prior Art High-voltage, high-speed devices Field l''r@-type region To form a channel stop region, conventionally a mask for defining a field oxidation region and a mask for defining a channel stop region are used. Using a 2-layer mask, apply 2 times
A circular area is formed by the process. Now, we will explain the process order by taking an n-channel N40S device as an example with reference to Fig. 2. ,1
3 is silicon nitride (Si:+
The figure shows the state in which a window was opened using a mask to define the r-field 1 oxidation region on day 1 of the N+) film. Next, the 21st part 1 (resist 4 applied to BL) was applied to the entire surface, window rj)'rJ was performed using a mask to define the channel stop region, and impurity ions 3+ were implanted. A stop region 15 is formed. Next, as shown in FIG. 2 (C1t; remove I, L, resist I, 14 and oxidation-resistant mask Il'l I: 3 to l-4 to form field oxide film 16, and leave the state at step 7. In the case of two photo-isolations, it is required to stabilize the process and simplify the process to increase production yield. Due to constraints on the patterning accuracy of the F7M L;l/S,/) process, improvements are needed to set the spacing to the minimum necessary from the perspective of increasing the density of the 31T conductor device. Becomes a key point.

（ｄ）９発明の目的 本発明の目的は従来技術の有する上記の、欠点を除去し
、フィールド酸化領域とチャンネル・ストップ領域の形
成を１層の一マスクを用いて１回のりツクラフイエ程で
行い、かつ従来より高密度化の可能な製造方法を提供す
ることを目的とするものである。(d)9 Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to form a field oxide region and a channel stop region in one lamination process using one layer and one mask. The object of the present invention is to provide a manufacturing method that allows higher density than conventional methods.

（ｅ）１発明の構成 本発明による半導体装置の製造方法は、半導体塞板−１
−に順次緩衝１１ｒＡと１ｌｉｉ４酸化マスク１漢を被
着し、第１のレジストを用いリソグラフィ工程により耐
酸化マスク膜にフィールド醇化領域を画定する窓をあり
る工程と、第１のレジストを除ノモし７ないでその上に
第２のレジストを全面塗布する上程と、随意の開１」部
に所期の厚さの第２のレジストを残して、該窓内の級侑
膜が露出する迄第２乃至第１のレジストを除去する工程
と、該窓内に露出Ｕ７た開口部に不純物を導入し°ζチ
ャンネル・ス１ノブ領域を形成する工程と、該窓内にフ
ィール１−酸化領域を形成する工程を自することを特徴
とするものである。(e) 1 Structure of the Invention The method for manufacturing a semiconductor device according to the present invention includes a semiconductor plug-1
- sequentially applying a buffer 11rA and 1lii4 oxidation mask 1 cylindrical layer, forming a window to define a field enrichment area in the oxidation-resistant mask film by a lithography process using the first resist, and removing the first resist. 7, then apply the second resist over the entire surface, leaving the second resist of the desired thickness in the optional opening 1'' until the grain film in the window is exposed. a step of removing the second or first resist; a step of introducing impurities into the opening exposed in the window to form a °ζ channel snob region; It is characterized in that it includes a step of forming.

本発明によれば１層のマスクを用いて、１回のりソグラ
フィ］−程で、フィールＦ−Ｍ出頭１八と千ｌン不ル・
ストップ領域が形成され、し、７かもすトソネル・スト
ップ領域はレジスト１’Ａ　Ｉ￥の調整と自己位置合わ
せ効果に、１、す、高積度６、二画定ごきイ）。２層の
マスクを使用する従来の方θ、４．二、Ｉ、ると、バ〃
ニング精度は現状のフ」１　プＩＩむ−′、技術ζＩＩ
、１１ｐｍ程度であるが、Ｌ・シストのＩ９９層度（，
１イ、こ」１桁小さくできる。According to the present invention, a single layer of mask is used, a single lithography process is performed, and a field F-M appearance of 18 and 1,000 times is achieved.
A stop area is formed, and the stop area is defined by the adjustment of the resist 1'A I and the self-alignment effect. Conventional method using a two-layer mask θ, 4. 2, I, To, Ba〃
The accuracy of printing is based on the current technology.
, about 11 pm, but the I99 layer thickness of L. cyst (,
1 I, ko” You can make it one digit smaller.

（ｅ）１発明の実施例 本発明の実施例をｎ−チャンネルＭＯ３卑ｉ’６．ニ一
つい“（第３１１＋で１−程力１ｎに従、っ゛ζａダｉ
明′４る。第３図（ａｌにおいて、まづｐ型基板２１の
−１−に、順次緩ｔｒｉ膜としての５ｉ０２膜２２を５
０（）人、耐酸化−ｌスク膜としこの５ｉ３Ｎａ膜２３
を２　＋１　（１０人稈１す被着し、フィールド酸化領
域を画定−・Ｎ′、、−７スイ７を用い、通常のパタニ
ングによりＳｉ：＋　Ｎ４１脱に該領１・・（形成用の
窓をありる。ごごで緩山膜はＳｉ貼（尺と５１３Ｎ４映
の間に介在さ−Ｕスｌ　Ｌ・スの♀’］ＩＩに没〜′ｆ
人：せるものである。２４はパタニングに使用された第
１のレジストを示し、膜厚は１μｍ程度でよい。(e) 1 Embodiment of the Invention An embodiment of the invention is an n-channel MO3 base i'6. Two ``(311+, 1- degree force 1n, ゛ζa da i
It's clear. In FIG. 3 (al), first, a 5i02 film 22 as a slow tri film is sequentially applied to -1- of the p-type substrate 21.
0() person, oxidation resistant-l screen film and this 5i3Na film 23
Deposit 2+1 (10 culms 1) and define a field oxidation region -・N',, using -7 switch 7, and remove the Si:+N41 by normal patterning. There is a window.The loose-mounted film is coated with Si (interposed between the shaku and 513N4 film-UslL・Su's♀') II~'f
Person: It is something that can be done. Reference numeral 24 indicates the first resist used for patterning, and the film thickness may be about 1 μm.

つぎに第３図（ｂｌにおいて、第１のレジスト膜はその
まま残して基板全面にわたって第２のレジスト２５を塗
布する。窓側面のレジスト厚さが０．５〜２ｆｔｍ程度
の範囲で所望の値に選ぶ。つきに第３図ｆｃ］において
、リアクティブ・イオン・エッチ等により異方性エッチ
を行い、第２乃至第１のレジスト除去を５ｉ０２膜が露
出する迄行う。第２のレジスト２５によりＳｉ３　Ｎ４
膜の窓の内側に新しくできた開口部にＢ＋イオンの１１
込みを１にないｐ１型のチャンネル・ストップ領域２６
を形成する。Next, in FIG. 3 (bl), the first resist film is left as is and a second resist 25 is applied over the entire surface of the substrate. 3f], anisotropic etching is performed using reactive ion etching, etc., and the second and first resist removal is performed until the 5i02 film is exposed.The second resist 25 removes the Si3 N4
11 of B+ ions in the newly created opening inside the membrane window.
P1 type channel stop region 26 with no inclusion
form.

つぎに第３図（ｄｌにおいて、レジストを除去り、　Ｓ
　ｉ　３Ｎ４膜をマスクにしてフィールド酸化を行う。Next, in Figure 3 (dl), the resist is removed and S
Field oxidation is performed using the i3N4 film as a mask.

２７は形成されたフィールド酸化膜を示す。27 shows the formed field oxide film.

本発明の実施例はｎ−チャンネルＭＯ５素子について述
べたが基板を他の半導体に、５ｉ０２膜を弛の緩衝膜に
、チャンネル・ストップ領域形成のために導入する不純
物Ｂ＋を他の不純物に変更しても本発明は適用可能であ
る。Although the embodiment of the present invention has been described with respect to an n-channel MO5 device, it is possible to change the substrate to another semiconductor, the 5i02 film to a relaxation buffer film, and the impurity B+ introduced to form the channel stop region to another impurity. However, the present invention is also applicable.

（ｆ）１発明の効果 以上詳細に説明した柱に本発明によれば、二′イールド
酸化領域形成とその内側にチャンネル・ソ、トップ領域
形成を１闇のマスクＬ、Ｚ　、１、す１回４’、Ｉ）す
゛タグラフイ上程で可能となり、１′稈の簡略化がζき
る。また円領域の間隔を従来方法に、ｌ、る１ふ１合、
１、り小さく制御可能となり、半導体装置のｉ？’ｔｉ
τ・１７度化（、二寄与できるようになる。(f) 1. Effects of the Invention According to the present invention, according to the pillars described in detail above, the formation of the 2' yield oxidation region and the formation of the channel, so, and top regions inside the 2' yield oxidation region are performed using the dark masks L, Z, 1, Step 4', I) It becomes possible in the above stage of the graph, and the 1' culm can be simplified. In addition, the intervals of the circular areas are changed to the conventional method, l, ru1fu1go,
1. It is possible to control the i? 'ti
τ・17 degrees (, it becomes possible to make two contributions.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はチャンネル・ストップ領１喫とソー：’、　ｉ
ｔ’たはトレインｆｉ域が接触している場合の１１１１
面図、第２図と第３図は円領域がう）　Ｍｌｔ　Ｌ７こ
い・乙場合で第２図は従来の製造工程を示すｌＪｉ面図
、第３目Ｇ、１／１発明の製造」程を示す断面図ごｉち
る。　ｒＪ１４ｊ、ｌいて、１、ＩＬ２］はＳｉ基板、
１２．２２はＳ　＋　０２脳、＋３．２３はＳｉ３　Ｎ
４膜、１４．２４，２５Ｌ・ジスト１２　、　Ｉ　５　
、２〔ｉ　ｌ、１．’　”ｆ−１ンネル・ス１ノゾ領域
、３．１６，２７ε、１ソイ　ル１１ｊ（出頭Ｊ戊、４
はソースまたはトレーｆン１ｊ１Ｊｅシ全小（ｌ。 壽　１図 洋２図 ５ ＩＳ　／６ 算　３図 β“Figure 1 shows the channel stop area 1 and so:', i
1111 when the t' or train fi regions are in contact
Figure 2 shows the conventional manufacturing process; Figure 3 shows the manufacturing process of the 1/1 invention A cross-sectional view showing the. rJ14j, l, 1, IL2] is a Si substrate,
12.22 is S + 02 brain, +3.23 is Si3 N
4 membranes, 14.24, 25L・Gist 12, I 5
, 2 [i l, 1. ' ``f-1 channel 1 nozo area, 3.16, 27ε, 1 soil 11j (appearance J 戊, 4
is the source or tray fn1j1Jeshizensho (l. Hisashi 1 Figure 2 Figure 5 IS /6 Calculation 3 Figure β"

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に順次暖ｉチｉ膜と耐酸化マスク膜を被着
し、第１のレジストを用いリソグラフィ工程により耐酸
化マスク膜にフィールド酸化領域を画定する窓をありる
に程と、第１のレジス（−を除去しないでその上に第２
のレジストを全面塗布する工程と、随意の開口部に所期
の厚さの第２のレジストを残して、該窓内の緩衝膜が露
出する迄第２乃至第１のレジストを除去する工程と、該
窓内に露出した開ｌ」部に不純物を導入してチャンぶル
・ストップ領域を形成する工程と、該窓内にフィールド
酸化領域を形成する工程を有することを特徴とする半導
体装置の製造方法。A thermal insulation film and an oxidation-resistant mask film are sequentially deposited on a semiconductor substrate, and a window defining a field oxidation region is formed in the oxidation-resistant mask film by a lithography process using a first resist. register (do not remove the - and place the second one on top of it)
and removing the second to first resists until the buffer film within the window is exposed, leaving a second resist of a desired thickness in any opening. , forming a chamber stop region by introducing an impurity into the open portion exposed within the window; and forming a field oxidation region within the window. Production method.
JP18113783A 1983-09-29 1983-09-29 Manufacture of semiconductor device Pending JPS6074454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18113783A JPS6074454A (en) 1983-09-29 1983-09-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18113783A JPS6074454A (en) 1983-09-29 1983-09-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6074454A true JPS6074454A (en) 1985-04-26

Family

ID=16095527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18113783A Pending JPS6074454A (en) 1983-09-29 1983-09-29 Manufacture of semiconductor device

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996029733A1 (en) * 1995-03-21 1996-09-26 Peregrine Semiconductor Corp. Self-aligned edge control in silicon on insulator
JPH09293777A (en) * 1996-04-25 1997-11-11 Nec Corp Semiconductor device and its manufacturing method
KR20220061994A (en) 2019-09-12 2022-05-13 칸토 덴카 코교 가부시키가이샤 A method for purifying a fluoroolefin having a structure of =CF2 or =CHF, and a high-purity fluoroolefin and a method for producing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5863823A (en) * 1993-07-12 1999-01-26 Peregrine Semiconductor Corporation Self-aligned edge control in silicon on insulator
WO1996029733A1 (en) * 1995-03-21 1996-09-26 Peregrine Semiconductor Corp. Self-aligned edge control in silicon on insulator
JPH09293777A (en) * 1996-04-25 1997-11-11 Nec Corp Semiconductor device and its manufacturing method
US6127708A (en) * 1996-04-25 2000-10-03 Nec Corporation Semiconductor device having an intervening region between channel stopper and diffusion region
KR20220061994A (en) 2019-09-12 2022-05-13 칸토 덴카 코교 가부시키가이샤 A method for purifying a fluoroolefin having a structure of =CF2 or =CHF, and a high-purity fluoroolefin and a method for producing the same

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