JPH05136366A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the area of one memory cell occupied on a semiconductor substrate, by forming a transistor on an interlayer insulating layer located right above a capacitor that is electrically connected to the capacitor. CONSTITUTION:A capacitor cell unit is formed in a conventional manufacturing method. In the semiconductor memory, a pass transistor unit is constituted by a polycrystalline silicon layer 21, a source/drain region 22, a third insulating layer 23, and a gate electrode 24 on the capacitor cell unit. Consequently, the area of one memory cell occupied on a semiconductor substrate is reduced so that the integration density can be improved in the semiconductor memory. Since a capacitor and a pass transistor can be separately formed, the thickness of an insulator and an electrode or the materials are selected in a free manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to the structure of a memory cell of a semiconductor memory device for improving the degree of integration used in a dynamic semiconductor memory device or the like.

[0002]

2. Description of the Related Art Conventionally, one memory cell of a dynamic semiconductor memory device has been constructed by arranging a groove type dynamic capacitor cell portion and a MOS transistor cell portion side by side. FIG. 11 shows a sectional view of a main part of a conventional semiconductor memory device. As shown in FIG. 1, 1 is a semiconductor substrate made of a first conductivity type single crystal, 13 is an element isolation layer for separating an element formation region formed on the semiconductor substrate 1, and 2 is formed on the semiconductor substrate 1. It is a groove that is a concave portion. 4 is the first
Insulating film, 5 is a charge storage layer, 6 is a second insulating film, 18 is a second conductivity type impurity layer, 12 is a capacitor electrode, 24
Is a gate electrode, 27 is a source / drain region of a transistor, 32 is an interlayer insulating film for metal wiring, 30 is an opening formed in the interlayer insulating film 32 for metal wiring, 28
Is an impurity layer for metal wiring, and 31 is a metal wiring.

Next, the conventional manufacturing method (US Pat. No. 4,9,9)
No. 18,500). First,
As shown in FIG. 12, a groove 2 which is a recess and an element isolation layer 1
3 and the first conductive type semiconductor substrate 1 on which the first insulating film 4 is formed, the first resist 15 is applied, and the silicon oxide 16 dissolved in an organic solvent is applied thereon and baked. Harden. Then, a second resist 17 is applied on top of it.

Then, the second resist 1 is exposed by the exposure device.
Form 7. The silicon oxide 16 is etched by using the second resist 17 as a mask. Further, using the silicon oxide 16 as a mask, the first resist 15 is anisotropically etched to stop the etching at a desired depth. Then the first
Using the resist 16 as a mask, the upper end of the sidewall of the groove 2 and a part of the first insulating layer 4 on the upper surface of the semiconductor substrate 1 are removed. As shown in FIG. 13, ion implantation is performed using the first resist pattern as a mask to form an impurity layer 18 of the second conductivity type.

Next, after removing the first resist 15 and the silicon oxide 16, as shown in FIG. 14, the second conductivity type silicon polycrystalline layer 7 is formed on the inner peripheral surface of the groove 2 by the CVD method. To the upper surface of the semiconductor substrate 1.

Subsequently, as shown in FIG. 15, the semiconductor substrate 1
Of the polycrystalline silicon 7 located on the upper surface of the first insulating layer 4 and on the bottom surface of the groove 2 in a self-aligned manner by anisotropic etching to form a cylindrical charge storage region 5 along the inner peripheral surface of the first insulating layer 4. To be done.

Next, as shown in FIG. 16, a second insulating layer 6 and a second conductivity type silicon polycrystalline layer 12 are deposited on the charge storage region 5 by the CVD method.

Finally, the second conductivity type silicon polycrystal layer 12 is patterned into a desired shape to form the capacitor electrode 12, and the memory cell portion of the semiconductor memory device having the structure as shown in FIG. 11 is formed. It is formed.

Next, similar to the formation of the capacitor electrode 12, the second conductivity type silicon polycrystalline layer 21 is patterned into a desired shape to form a gate electrode 24. A second conductivity type source / drain region 27, one end of which is electrically connected to the charge storage layer region 18, is formed on the semiconductor substrate 1 along the upper surface thereof by an ion implantation method. Semiconductor substrate 1, source / drain regions 27,
The second insulating layer 6 and the gate electrode 24 form a pass transistor portion of the semiconductor memory device.

Next, an interlayer insulating film 32 for metal wiring is deposited on the capacitor portion and the pass transistor portion, and the opening portion 30 is formed by etching into a desired shape. The second conductivity type impurity layer 28 is formed by being electrically connected to the source / drain regions 27 by the ion implantation method. A metal thin film 31 is formed on the thus formed inter-layer insulating film 32 for metal wiring, and the metal thin film 31 is etched into a desired shape to form the metal wiring 31.

[0011]

Since the conventional semiconductor memory device is constructed as described above, the area of the memory cell is becoming smaller with the integration of the semiconductor memory device. There has been a problem that it has become difficult to improve the area of the memory cell and reduce the area of the memory cell, and to form the capacitor cell portion and the transistor cell portion side by side in the memory cell.

The present invention has been made in order to solve the above problems, and increases the number of memory cells formed per fixed area on one main surface of a semiconductor substrate.
It is another object of the present invention to obtain a highly integrated semiconductor memory device.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a recess formed on one main surface of a semiconductor substrate;
A capacitor formed along the inner surface of the recess, an interlayer insulating layer deposited on the capacitor, and a transistor formed on the interlayer insulating layer directly above the capacitor and electrically connected to the capacitor. Is configured.

A semiconductor memory device according to a second invention is the first memory device.
In the semiconductor device of the present invention, the capacitor formed along the inner surface of the recess on the semiconductor substrate has a conductivity type impurity diffusion layer formed by introducing impurities into the semiconductor substrate on the inner surface of the recess to form a charge storage region. It is characterized by

A semiconductor memory device according to a third invention is the first memory device.
In the semiconductor device of the invention described above, the capacitor formed along the inner surface of the recess on the semiconductor substrate has a first insulating layer formed on one main surface of the semiconductor substrate including the entire inner surface of the recess, and A conductor film uniformly formed on the first insulating layer, a second insulating layer formed on the conductor film, and a capacitor electrode layer formed on the second insulating layer. It is characterized in that the element isolation between the capacitor and the element adjacent thereto is performed by the second insulating layer.

[0016]

According to the semiconductor memory device of the first aspect of the invention, one memory cell is a semiconductor memory device because it is formed on the interlayer insulating layer immediately above the capacitor and is provided with a transistor electrically connected to the capacitor. The area occupied by the substrate surface can be reduced.

Further, in the semiconductor memory device according to the second aspect of the present invention, a capacitor formed along the inner surface of the recess on the semiconductor substrate is of a conductive type formed by introducing impurities into the semiconductor substrate on the inner surface of the recess. By using the impurity diffusion layer as the charge storage region, the manufacturing process can be simplified.

A semiconductor memory device according to a third aspect of the invention includes a second insulating layer formed on a conductor film, and the element isolation between a capacitor and an element adjacent to the capacitor is performed by the second insulating layer. The area occupied by the element isolation layer can be reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. 1 is a sectional view showing the structure of a memory cell of a semiconductor memory device obtained according to the first embodiment of the present invention.

In FIG. 1, 1 is a semiconductor substrate, 13 is an element isolation layer, and 2 is a groove which forms a concave portion formed on one main surface of the semiconductor substrate 1. Reference numeral 4 is a first insulating film formed on the entire inner surface of the groove 2, 5 is a charge storage layer formed on the first insulating film 4 along the inner peripheral surface of the groove 2, and 6 is a charge storage layer 5.
A second insulating film formed on the inner surface of the second insulating film, 18 an impurity layer of the second conductivity type, 12 a capacitor electrode formed on the inner surface of the second insulating film 6, and the first insulating film 4 and The charge storage layer 5, the second insulating film 6 and the capacitor electrode 12 form a capacitor. Reference numeral 19 is an impurity layer for a wiring connecting the capacitor and the pass transistor, 14 is an interlayer insulating film for the pass transistor deposited on the capacitor, and 20 is an interlayer insulating film for the wiring of the pass transistor. An opening, 25 is a wiring connecting the pass transistor and the impurity layer 19, 21 is a thin film of polycrystalline silicon,
Reference numeral 22 is a source / drain region formed in a thin film of polycrystalline silicon connected to the wiring 25, 23 is a third insulating film which is a gate insulating film of a pass transistor, 24 is a gate electrode, and 32 is an interlayer for metal wiring. An insulating film, 30 is an opening formed in the interlayer insulating film 32 for metal wiring, and 31 is a metal wiring.

Due to the structure of the memory cell shown above,
The area occupied by each memory cell can be reduced, the number of memory cells per unit area of the semiconductor substrate can be increased, and the integration degree of the semiconductor memory device can be improved.

Next, a method of manufacturing the capacitor cell portion and the pass transistor cell portion of the memory cell of the semiconductor memory device configured as described above will be described with reference to FIGS.

FIG. 2 shows a capacitor cell portion manufactured by the same process as the conventional example. To form this capacitor cell part, the steps shown in FIGS. 12 to 16 are performed.

Next, as shown in FIG. 3, an opening 20 is formed in the interlayer insulating film 14 for the pass transistor. Then, impurities are ion-implanted to form the impurity layer 19. The second conductive type silicon polycrystal 25 is deposited by the CVD method, and the interlayer insulating film 14 is used as a stopper to perform etching back, whereby the wiring 2 of the pass transistor is formed.
Set to 5. A silicon polycrystal 21 is deposited and patterned into a desired shape to form a thin film transistor substrate.

Subsequently, the third insulating film 23 and the second-conductivity-type silicon polycrystal layer 21 are deposited and patterned into a desired shape to form a gate electrode 24. The source / drain regions 22 of the second conductivity type are formed in a part of the polycrystalline silicon layer 21 by an ion implantation method using the gate electrode 24 as a mask. A silicon polycrystal layer 21 and source / drain regions 22 are formed. Silicon polycrystalline layer 2
1, the source / drain region 22, the third insulating layer 23, and the gate electrode 24 form a pass transistor portion of the semiconductor memory device.

Next, an interlayer insulating film 32 for metal wiring is deposited on the pass transistor portion and etched into a desired shape to form an opening 30. The third insulating layer 23 exposed by forming the opening 30 is removed. A metal thin film 31 is formed on the interlayer insulating film 32 and etched into a desired shape to form the metal wiring 31. As described above, according to the semiconductor memory device of this embodiment, since the capacitor cell portion and the pass transistor cell portion are formed separately, the thickness of the insulating film, the electrodes, the material, etc. can be freely selected. The effect is that you can.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a sectional view of the essential part of the structure of the memory cell of the semiconductor memory device obtained according to the second embodiment of the present invention. In FIG. 4, 1 is a semiconductor substrate, 13 is an element isolation layer, and 2 is a groove which forms a recess formed in one main surface of the semiconductor substrate 1. 3 is an impurity layer formed along the groove 2 in the semiconductor substrate 1, 4 is a first insulating film formed on the entire inner surface of the groove 2 in which the impurity layer 3 is formed, 12
Is a capacitor electrode formed on the inner surface of the first insulating film 4,
Then, the first insulating film 4, the impurity layer 3, and the capacitor electrode 12 form a capacitor. 14 is an interlayer insulating film for the pass transistor deposited on the capacitor, 20 is an opening formed in the interlayer insulating film for the wiring connecting the pass transistor and the impurity layer 3, and 25 is the pass transistor and the impurity layer. A wiring connecting 3; 21 is a polycrystalline silicon thin film; 22 is a source / drain region formed in the polycrystalline silicon thin film connected to the wiring 25;
Is a third insulating film which is a gate insulating film of a pass transistor, 24 is a gate electrode, 32 is an interlayer insulating film for metal wiring, 30 is an opening formed in the interlayer insulating film 32 for metal wiring, 31 Is metal wiring.

A method of manufacturing the capacitor portion and the pass transistor portion of the memory cell of the semiconductor memory device thus configured will be described with reference to FIGS.

First, the groove 2 as a recess and the element isolation layer 13 are formed on one main surface of the first conductivity type semiconductor substrate 1. Next, as shown in FIG. 5, the semiconductor substrate 1 excluding the portion where the element isolation layer 13 is formed is exposed to a high-temperature impurity atmosphere.
An impurity layer 3 of the second conductivity type is formed on the surface of.

Next, as shown in FIG. 6, a first insulating layer 4 is formed on the second conductivity type impurity layer 3 by an existing method. Next, as shown in FIG. 7, on the first insulating layer 4,
The second-conductivity-type silicon polycrystalline layer 12 is deposited by the CVD method. Then, as shown in FIG. 8, the second conductivity type silicon polycrystalline layer 12 is patterned into a desired shape to form the capacitor electrode 12. The capacitor cell portion of the semiconductor memory device is configured by the above procedure.

Then, similarly to the first embodiment, the interlayer insulating film 14 for the pass transistor is deposited, and the opening 20 is further formed. Second conductivity type silicon polycrystalline layer 2
5. The wiring 25 of the pass transistor is formed by depositing by the CVD method and performing etching back using the interlayer insulating film 14 as a stopper. Then, in the same manner as in the first embodiment, the silicon polycrystalline layer 21, the source / drain regions 22, the third insulating layer 23, and the gate electrode 24 are used to pass the semiconductor memory device as shown in FIG. It constitutes a transistor cell section.

As described above, by adopting the structure of the second embodiment, the manufacturing process is simpler than the conventional manufacturing process of the capacitor cell portion in forming the charge storage layer and the connection between the transistor and the capacitor. Therefore, there is an effect that the highly integrated semiconductor memory device according to the present invention can be easily manufactured.

Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 10 is a sectional view of the essential part of the structure of the memory cell of the semiconductor memory device obtained according to the third embodiment of the present invention.

In FIG. 10, reference numeral 1 is a semiconductor substrate, and 2 is a groove forming a concave portion formed on one main surface of the semiconductor substrate 1. Reference numeral 4 is a first insulating film formed on the semiconductor substrate 1 including the entire inner surface of the groove 2, and 5 is a charge storage layer formed by patterning a conductor formed on the first insulating film 4, 6 Is a second insulating film formed on the inner surface of the charge storage layer 5, 12 is a capacitor electrode formed on the inner surface of the second insulation film 6, and the first insulating film 4, the charge storage layer 5, and the first insulating film 4. Two
The insulating film 6 and the capacitor electrode 12 form a capacitor, and the second insulating film 4 separates adjacent capacitors. 14 is an interlayer insulating film for the pass transistor deposited on the capacitor, 20 is an opening opened in the interlayer insulating film for the wiring of the pass transistor, and 25 is a wiring connecting the pass transistor and the charge storage layer 5. , 21 is a polycrystalline silicon thin film, 22 is a source / drain region formed in the polycrystalline silicon thin film connected to the wiring 25,
23 is a third insulating film which is a gate insulating film of a pass transistor, 24 is a gate electrode, 32 is an interlayer insulating film for metal wiring, 30 is an opening formed in the interlayer insulating film 32 for metal wiring, Reference numeral 31 is a metal wiring.

A method of manufacturing the capacitor cell portion and the pass transistor cell portion of the memory cell of the semiconductor memory device thus configured will be described with reference to FIG.

As shown in FIG. 10, a groove 2 which is a recess is formed in a semiconductor substrate 1 of the first conductivity type. Next, the first insulating layer 4 is formed on the entire one main surface of the semiconductor substrate 1 including the inner surface of the groove 2, and the second conductivity type silicon polycrystalline layer is formed on the first insulating layer 4. Is deposited by CVD on the inner surface of the groove 2 to the upper surface of the semiconductor substrate 1 so as to have a uniform film thickness, and patterned into a desired shape to form the charge storage region 5. A second insulating layer 6 and a second conductivity type silicon polycrystalline layer 12 are CVed on the charge storage region 5.
Deposit by the D method. At this time, the second insulating layer 6 separates the adjacent capacitors from each other. Then, the second conductivity type silicon polycrystalline layer 12 is patterned into a desired shape to form the capacitor electrode 12.
The capacitor cell portion of the semiconductor memory device is configured by the above procedure.

Next, similar to the procedure shown in FIG. 9 in the second embodiment, the interlayer insulating film 14 for the pass transistor is formed.
Is deposited, and an opening 20 is formed immediately above the charge storage layer 5. The second conductivity type silicon polycrystalline layer 25 is CV
It is deposited by the D method and is etched back using the interlayer insulating film 14 as a stopper to form the wiring 25 of the pass transistor. Then, in the same manner as in the second embodiment, the silicon polycrystal layer 21 and the source / drain regions 2 are formed.
2, the third insulating layer 23 and the gate electrode 24 form a pass transistor portion of the semiconductor memory device.

As described above, according to the semiconductor memory device of this embodiment, since the capacitor cell portion and the pass transistor cell portion are formed separately, the thickness of the insulating film, the electrodes, the material, etc. are selected. The effect is that you can do it freely.

Further, according to the structure of the memory cell of the third embodiment, the elements are isolated by the second insulating film 6 instead of by the element isolation layer. There is an effect that can improve. Further, in forming the connection between the transistor and the capacitor, the manufacturing process is simplified as compared with the conventional manufacturing process of the capacitor cell portion, and the highly integrated semiconductor memory device according to the present invention can be easily manufactured. effective. Further, since the charge storage layer is also formed on the bottom surface of the recess, there is an effect that the capacitance of the capacitor is increased. Further, since the charge storage region 5 is electrically separated from the semiconductor substrate 1 by the first insulating film 4, the effect such as the soft error caused by the charges generated in the semiconductor substrate 1 due to the α rays or the like can be removed. There is.

In each of the above embodiments, the thin film transistor is used as the transistor formed on the capacitor, but a transistor other than the thin film transistor may be used as the transistor formed on the capacitor. Has the same effect.

[0043]

According to the semiconductor memory device of the first aspect of the present invention, the semiconductor memory device is formed on the interlayer insulating layer immediately above the capacitor, and is configured to include a transistor electrically connected to the capacitor. Since the area occupied by one memory cell on the surface of the semiconductor substrate is reduced, and the degree of integration per fixed area is increased, the degree of integration of the semiconductor memory device can be improved. Further, since the capacitor and the pass transistor are formed separately, there is an effect that the thickness of the insulating film, the electrode, the material, etc. can be freely selected.

Further, according to the semiconductor memory device of the present invention, a capacitor formed along the inner surface of the recess on the semiconductor substrate is formed by introducing impurities into the semiconductor substrate on the inner surface of the recess. By using the conductivity type impurity diffusion layer as the charge storage region, the manufacturing process can be simplified, and the semiconductor memory device according to the present invention can be easily manufactured.

Further, a semiconductor memory device according to a third aspect of the present invention includes a second insulating layer formed on a conductor film, and separates a capacitor and an element adjacent to the capacitor from the second insulating layer. By using the layer, there is an effect that the area occupied by the element isolation layer can be reduced and the integration degree of the semiconductor memory device can be further improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a main part of a memory cell of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a structure of a main part of a memory cell of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing the method of manufacturing the semiconductor memory device according to the third embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a structure of a main part of a memory cell of a conventional semiconductor memory device.

FIG. 12 is a cross-sectional view showing the method of manufacturing the conventional semiconductor memory device.

FIG. 13 is a cross-sectional view showing the method of manufacturing the conventional semiconductor memory device.

FIG. 14 is a cross-sectional view showing the method of manufacturing the conventional semiconductor memory device.

FIG. 15 is a cross-sectional view showing the method of manufacturing the conventional semiconductor memory device.

FIG. 16 is a cross-sectional view showing the method of manufacturing the conventional semiconductor memory device.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Groove 3 Impurity Layer 4 First Insulating Film 5 Charge Storage Layer 6 Second Insulating Film 12 Capacitor Electrode 13 Element Separation Layer 14 Interlayer Insulating Film 15 First Resist 16 Silicon Oxide 17 Second Resist 18th Second conductivity type impurity layer 19 Second conductivity type impurity layer 20 Opening 21 Polycrystalline silicon thin film 22 Source / drain region 23 Third insulating film 24 Gate electrode 25 Wiring 27 Source / drain region 28 Impurity layer 30 Opening 31 Metal wiring 32 Interlayer insulation film

Claims (3)

[Claims] 1. A recess formed on one main surface of a semiconductor substrate, a capacitor formed along the inner surface of the recess, an interlayer insulating layer deposited on the capacitor, and the interlayer insulating layer directly above the capacitor. A semiconductor memory device, comprising: a transistor formed above and electrically connected to the capacitor. 2. The charge accumulation region, wherein the capacitor formed along the inner surface of the recess on the semiconductor substrate has a conductivity type impurity diffusion layer formed by introducing impurities into the semiconductor substrate on the inner surface of the recess. The semiconductor memory device according to claim 1, wherein: 3. The capacitor formed along the inner surface of the recess on the semiconductor substrate, the first insulating layer formed on one main surface of the semiconductor substrate including the entire inner surface of the recess, A conductor film uniformly formed on the first insulating layer, a second insulating layer formed on the conductor film, and a capacitor electrode layer formed on the second insulating layer. 2. The semiconductor memory device according to claim 1, further comprising an element isolation between the capacitor and an element adjacent thereto by the second insulating layer.