JPS6223151A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve electrical characteristics by using a process, in which a gate insulating film is formed, as one part for shaping a gate insulating film for a second MISFET in predetermined thickness. CONSTITUTION:An n<-> type well region 2 is formed in a region, in which a p channel type high withstanding-voltage MISFET is shaped, in a p<-> type semiconductor substrate 1, and field insulating films 3 and p-type channel stopper regions 4 are formed. Insulating films 5 used as first gate insulating films for the MISFET as a memory cell are shaped by oxidizing the main surface of the semiconductor substrate 1, and a resist film 6 is formed so as to coat regions Y and Z. The resist film 6 is employed as a mask for an ion implantation process in which an impurity is introduced into a channel region in the memory cell, and the p-type impurity such as boron is introduced into the channel region in the memory cell through ion implantation. Accordingly, an unnecessary diffusion into the semiconductor substrate and the well region of the impurity is prevented, thus improving electrical characteristics.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit'! The present invention relates to a technology that is effective when applied to a semiconductor memory device equipped with an MISFET.

[Background Art] As an example of a semiconductor memory device, a MISFE with a floating gate electrode and a control gate (distortion) is used.
EPROM (Electrica
lly Programmable Read
0nly Memory) There is a crab. fitlE
PROM writes information by generating hot electrons by applying a high potential of about 12 V to the control gate electrode and drain region of the memory cell.

For this reason, one peripheral circuit is provided with a storage circuit for applying the high potential to the memory cells.

The MISFET that constitutes the write circuit must have a dielectric breakdown voltage higher than the above-mentioned high potential (hereinafter, such a MISFET will be referred to as a high voltage MTS FET).
, Also, the peripheral circuit includes a MISFET (hereinafter referred to as normal voltage !Al5FET) that is driven between 0 and 5 [V].
is provided.

An example of a method for manufacturing such a semiconductor integrated circuit device is described in, for example, Japanese Patent Application No. 55-22760. That is, the gate isolation 80 of the high voltage MISFET constituting the write circuit is replaced with the floating gate ft of the memory cell.
One gate insulating film is provided between one pole and the semiconductor substrate (
It is formed in the step of forming a first gate insulation layer (hereinafter referred to as a first gate insulation layer). Also.

The gate insulating film of the normal voltage MI S FET is formed in the same process as the insulating film provided between the floating gate electrode and the control gate electrode (hereinafter referred to as a second gate insulating film).

Further, it is conceivable that the gate insulation film of the high voltage MI S FET and the gate insulation film of the normal voltage MI S FET are formed in the process of forming the second gate insulation film of the memory cell.

The present inventor;
In the method for manufacturing gate insulating films for I S FETs and normal voltage MI S FETs, we have found a problem in that the electrical characteristics of these MISFETs deteriorate.

In the process of forming the first gate insulating film of the memory cell, the method for forming the gate insulating film of the high voltage MISFET includes
IS FET gate 1! After forming the gate, a second gate dielectric of the memory cell is formed. This thermal oxidation process for forming the second gate insulating film allows high-voltage MIS
Impurities for controlling the threshold voltage of the FET are unnecessarily diffused into the semiconductor substrate. Therefore, high voltage MIS
It becomes extremely difficult to set the threshold voltage of the FET to a predetermined value. Furthermore, when configuring a peripheral circuit in CMrSFI':T, a write circuit is configured. In particular, in a P-channel type high voltage λ4I'5FET, punch-through is likely to occur between the drain paper and the source region.

On the other hand, by using the process of forming the second gate insulating film of the memory cell, normal voltage M I S FET and high voltage M r
In the method of forming the gate insulating film of SFET,
The thickness of the gate insulating film of the 6 normal voltage M r S FET, which reduces the mutual conductance of the normal voltage M I S F E 'r, is similar to that of the high voltage 1,11 S FET. This is because it is formed.

[Object of the Invention] An object of the present invention is to provide a technique that can improve the electrical characteristics of an MI S FET.

Another object of the present invention is to provide a technique that can improve the degree of integration of a semiconductor memory device.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, the step of forming the gate insulating film between the floating gate electrode and the control gate electrode of the first MISFET is used as part of the forming step of forming the gate insulating film of the second MISFET to a predetermined thickness.

Hereinafter, the configuration of the present invention will be explained along with examples.

In addition, in all the episodes for explaining actual jAi examples.

Items that have the same repetition are marked with the same symbol t), and the explanation of the repetition will be omitted.

[Embodiment ■] Figures 1 to 16 show five EPROMs of Example I of the present invention.
1 to 6 are diagrams for explaining the manufacturing method of
8, 10, and 12 are cross-sectional views in each of the 12 manufacturing steps, and in these figures, Gl [X, Y
and Z are a memory cell and a high voltage MISF, respectively.
FIGS. 7, 9, and 11 show cross sections of ET and normal 11-pressure MISFET. FIG. 13 is a plan view of the memory cell in the manufacturing process. FIG.
It is a sectional view taken along the -XIV cutting line. Figure 15 is a cross-sectional view of a high voltage MISFE that constitutes the write circuit, and Figure 16 is a cross-sectional view of a normal voltage MISFE that constitutes the peripheral circuit.
It is a sectional view of T.

Note that the above plan view does not illustrate the insulating film provided between the conductive layers in order to make it easier to see the configuration of the memory cell in the V3 manufacturing process.

As shown in FIG. 1, first, an n-type well region 2 is formed in a region of a P-type semiconductor substrate 1 in which a channel-type cavity 1-pressure MI S FET is accommodated. Next, a field insulating film 3 and a P-type channel stopper region 4 are formed. The channel stopper Cfi<4 is formed on the main surface of the semiconductor substrate 1 under the field isolation B film 3 other than the well region 2. Field insulating film 3 is formed by selectively thermally oxidizing the main surface of semiconductor substrate 1 . The channel stopper region 4 is
A P-type impurity, for example, boron, is introduced into the main surface of the semiconductor substrate 1 by ion implantation to form the main surface of the semiconductor substrate 1. Next, by oxidizing the main surface of the semiconductor substrate 1,
An insulating film 5 used as a first gate insulating film of a MISFET (hereinafter simply referred to as a memory cell) that is a memory cell.
Next, a resist film 6 is formed to cover the peripheral circuit region, that is, the regions Y and Z. This resist film 6 is used as a mask in an ion implantation process for introducing impurities into the channel region of the memory cell.

Next, a p-type impurity 1, for example, boron, is introduced into the channel region of the memory cell by ion implantation.
It is important not to introduce the impurity into the T channel region. This is to prevent unnecessary diffusion of impurities for controlling the threshold voltage of MISFETs constituting one peripheral circuit in the subsequent step of forming the second gate insulating film of the memory cell.

Next, as shown in FIG. 2, a conductive layer 7, which will later become a floating gate electrode (first electrode), and a thermal oxidation mask 8 thereon are formed. First, in order to form the conductive layer 7, a polycrystalline silicon layer is formed over the entire upper surface of the substrate 1, for example, by CVD.

A silicon nitride layer is added to the polycrystalline silicon layer by diffusion of an n-type impurity such as phosphorus to reduce the resistance value of the floating gate electrode. Formed on the top surface of. Then, the unnecessary polycrystalline silicon layer other than the one used as the electrocardiographic arch 7 and the silicone dry pad on the upper part of the unnecessary polycrystalline silicon layer are removed by, for example, dry etching. The mask 8 has the same shape as the conductor W1 layer 7, and the conductor 1! A side wall spacer 9 is formed so as to adhere to and extend on the side of X47. This sidewall spacer 9 is used to prevent unnecessary conductive materials such as polycrystalline silicon layers from remaining between adjacent control gate electrodes in the process of forming control gate electrodes and word lines later. be.

The sidewall spacer 9 is formed by the following method. First, a polycrystalline silicon layer is formed on the substrate 1, covering the conductive layer 7 and the thermal oxidation mask 8, for example by CVD. Then, by reactive ion etching, f
The polycrystalline silicon layer is etched from its upper surface to such an extent that the upper surface of the ill'l mask 8 is exposed. The polycrystalline silicon layer.

Since it is formed particularly thick on the sides of the conductive layer 7, sidewall spacers 9 can be formed on the sides of the conductive layer 7.

Real h? In example A, this is to prevent the thermal oxidation mask 8 and field insulating film 3 from being etched when forming the sidewall spacers 9.

Although not shown, sidewall spacers 9 are formed using the thermal oxidation mask 8 and a polycrystalline silicon layer having an etching rate different from that of the field insulating film 3.
A resist mask is formed in the memory cell formation region, and the insulating film 5 formed in regions Y and 2 is removed by etching. This etching exposes the upper surfaces of semiconductor substrate 1 and well region 2 (regions Y and Z) where MISFETs constituting the peripheral circuit are provided.

Next, as shown in FIG. 3, the semiconductor substrate 1 is thermally oxidized to form an insulating film 10 (SiO2 film) to be used as a gate insulating film of the high 11-voltage MISFET. At this time, the absolute g film 1 is also provided in the region Z where the normal breakdown voltage MISFET is provided.
0 is formed, which will be removed later. Furthermore, since the surface of the sidewall spacer 9 is also oxidized, a silicon oxide film 11 is formed. Note that since the thermal oxidation mask 8 is provided on the conductive layer 7, the upper surface of the conductive ffi layer 7 is not oxidized.

Next, as shown in FIG. 4, a resist film 12 is deposited at a height of 1.
It is formed in the region Y where the pressure MIS FET is provided.

And insulation II of area Z! 1110 is removed by, for example, wet etching. At the same time, the silicon oxide WA11 on the surface of the sidewall spacer 9 in the region X is also removed. As the etching solution, a hydrofluoric acid-based etching solution is used. Furthermore, using the resist film 12 as a mask, the thermal oxidation mask 8 is removed to expose the upper surface of the conductive layer M7. A hot phosphoric acid based etching solution is used as the etching solution for this etching. Of course, the insulation films 8 and 11 and the insulation film 10 in the region where the normal breakdown voltage MISFET is provided may be removed separately using a mask. After this etching step, the resist film 12 is removed.

Next, as shown in FIG. 5, the semiconductor substrate 1 is thermally oxidized and the semiconductor substrate 1 is used as a gate insulating film of a normal voltage MISFET. J (Si○z film) 13 and the second layer of the memory cell
An insulating film (Si02 film) 14 which will become a gate insulating film is formed.

In this step, the region Y where the high breakdown voltage MISFET is provided is thermally oxidized again, so that the thickness of the insulating film 10 increases. That is, the insulation film 10 is formed in the process shown in FIG. 3 and the process shown in FIG.
An insulating film that is thicker than the insulating film 13 of the FET can be formed.

Therefore, in the thermal oxidation step for forming the insulating film 10 in FIG.

After the thermal oxidation process for forming the insulating film 13, the insulating film 10 is formed in advance to be thinner than a predetermined thickness so that the insulating film 10 has a predetermined thickness. The exposed surface of the sidewall spacer 9 is oxidized during the thermal oxidation process for forming the insulating film 13.

An insulating film (Si○z
a) t4 is formed. That is, the second gate insulating film of the memory cell and the gate insulating film of the normal voltage MI S FET are formed in the process shown in FIG. 5 above.

The gate insulating film of the high breakdown voltage MISFET is similar to that shown in FIG. 3 and the second gate insulating film of the memory cell and the normal breakdown voltage MI
This will be formed in the step of forming the SFET gate isolation l# film (FIG. 5).

Next, as shown in FIG. 6, a resist film 15 is formed in the memory cell region Next, we will introduce the high voltage MISFET and normal voltage MISFET that constitute the peripheral circuit.
P-type impurity for controlling the threshold voltage of FET,
For example, boron is introduced by ion implantation. of course.

The introduction of ions that control the threshold voltage mentioned above is a high breakdown voltage MI.
The process may be performed separately for the SFET and the normal voltage MIsFET.

Insulating film 13. Since the P-type impurity was introduced after forming the insulating film 14, the P-type impurity was introduced into the insulating film 13.14.
Unnecessary diffusion can be prevented by the thermal oxidation step for forming the .

Next, the resist film 15 is removed.

Next, as shown in FIGS. 7 and 8, a conductive layer 1B used as a control gate electrode of a memory cell, a word UWL, and a gate electrode of a peripheral circuit is formed. I
'yL First, a conductive layer 17 made of a polycrystalline silicon layer is formed on a substrate l by, for example, CVD. This guide ff
1ff17 contains an n-type impurity to reduce the resistance value,
For example, after introducing phosphorus by diffusion, a photoresist film 16 is formed on the entire surface of regions Y and Z, and
Control gate electrode in region X! Formed in the shape of a pole or word line. Using the resist film 16 as a mask, the conductive layer 17 in the region X is selectively etched, and the 4-electroF! 11B is formed. The conductive layer 18 is a control gate ff1 (second ml@), and also serves as a word line and conducts the sidewall spacer 9. ! By providing it on the side of the i-layer 7, it is possible to prevent unnecessary polycrystalline silicon layers from remaining between the conductive ys17. In addition, guide fl! W118 is a high melting point metal (Mo, W, Ta,
It can also be formed by a two-layer film consisting of a layer (such as Ti), a silicide layer thereof, or a polycrystalline silicon layer and a high melting point metal layer thereon or a silicide layer thereof. However, the insulating film 14 exposed from the conductive layer 18 is removed, and the conductive layer f6. The exposed portion of M7 is removed by etching. After this etching process completes the floating gate electrode made of the conductive layer 7, the resist film 16 is removed.

Note that region X in FIG. 8 is a cross-sectional view taken along the section line -■ in FIG. 7.

Next, as shown in FIGS. 9 and 10, high voltage MISFETs and normal voltage MISFETs constituting one peripheral circuit are
A conductive layer 18 is formed to serve as the gate electrode of the FET. In the step of forming the conductive layer 18, the entire region X where the memory cells are provided is covered with a mask made of resist, and the gates W! , a resist film is formed in the shape of a pole. Using this resist as a mask, conductors 18 in regions Y and Z are formed to form the gate W1 pole.

Conductive Wi layer 7. The exposed surfaces of the conductive M17 and the conductive layer 18 are oxidized to form an insulating film 19 made of a silicon oxide film.
form. In the memory cell, this insulating film 19 is primarily used to improve retention characteristics of minority carriers, which serve as information to be injected into the floating gate electrode.

In the area where the P-channel type MIS FET is provided.

First, a resist film 20 is formed to serve as a mask for the ion implantation process for forming the source region and drain region of the n-channel MIS FET.N-type impurity, For example, phosphorus is introduced into the main surface of the semiconductor substrate l by ion implantation. This impurity implantation may be performed separately for the memory cell and the peripheral circuit portion. After this ion implantation step, the resist film 20 is removed. Note that region V:< in FIG. 10 is a cross section taken along the line XX in FIG. 9.

Next, as shown in FIGS. 11 and 12,
A sidewall insulating film 22 is then formed on the side of the conductive layer 18. This sidewall insulating film 22 is formed by the same method as the sidewall spacer 9 formed previously. By the etching process for forming the sidewall insulating film 22, the unnecessary insulating film 5 exposed from the sidewall insulating film 22 is removed and the upper surface of the semiconductor substrate l is exposed. An n+ type semiconductor region 23 that will become the source region and drain region of the I S FET is formed. This is formed by introducing n-type impurities such as arsenic into the main surface of the semiconductor substrate 1 by ion implantation using the gate electrodes 18 and 7 and the sidewall insulating film 22 as masks. In the ion implantation step.

The region Y where the P-channel type MI S FET is provided is a primary region covered with a mask made of resist.

Source region of P-channel type cavity withstand voltage MIS FET.

The P1 type half region 24 which becomes the drain region is placed in the well f!
It is formed on the main surface of J'tIfi, 2. This is formed by introducing a p-type impurity, such as boron, into the well region 2 by ion implantation using the gate electrode 18 and sidewall insulation B'11A22 as a mask.

During this ion implantation process, the n-channel type MI
The regions X and Z in which the S FETs are provided are covered by a mask made of, for example, resist. Then, the semiconductor substrate 1 is annealed. Note that the area X in Figure 1-2 is
FIG. 12 is a sectional view taken along the xn-x cutting line in FIG. 11;

Next, as shown in FIGS. 13, 14, 15, and 16, an insulating film 25 is formed over the entire surface of the substrate 1. In addition, in FIG. 13, the side wall 9.22, the insulating film 2S
The insulating film 25 (not shown) consists of a silicon oxide film obtained by, for example, CVD, and a phosphor silicate glass film thereon. A conductive layer 27 made of aluminum M is formed by sputtering. This conductive rj
27 in the memory cell array area.

Used as data line DL. After forming the conductive layer 27, a protective film is formed to cover the conductive W1 layer 27.

Note that FIG. 14 is a cross section taken along the line XIV-XrV in FIG. 13.

In this example, the insulation film 10, which becomes the gate insulation film of the high-voltage MISFET, is formed in advance to be thinner than a predetermined film thickness, and then the insulation film 14, which becomes the second gate insulation film of the memory cell, is formed thinner than a predetermined film thickness.
In the step of forming the insulating film 13 which becomes the gate insulating film of the normal voltage MI S FET.

The insulating film 10 is formed to have a predetermined rIA thickness. Further, an impurity is added to the insulating film 14 to adjust the threshold voltage of the high voltage MISFET and the normal voltage MISFET.
It is introduced after forming the This makes it possible to prevent impurities from unnecessarily diffusing during the thermal oxidation process for forming the storage insulating film 14 of the memory cell.

Furthermore, since the thin insulating film 10 corresponding to the difference in thickness between the insulating film 10 and the absolute g film 13 can be formed in advance,
By using the process of forming the insulating film 13, the anti-Japanese film 10 can be formed to have an appropriate thickness. The only thing that is formed in the same thermal oxidation time as the insulating film 13 is the insulating film 14, which is formed by oxidizing the conductive layer 7 whose oxidation rate is different from that of the semiconductor substrate 1. Thereby, by adjusting the oxidation time, the insulating films 13 and 14 can be formed to have appropriate thicknesses.

Note that in this embodiment, the insulating film 10 is formed in advance to be thinner than a predetermined thickness, and then the thickness of the insulating film 10 is reduced to a predetermined thickness by the same process as that of forming the insulating films 13 and 14. The film thickness was increased. However, first, the insulating film 10 is formed as thin as the insulating film 13 in the same process as the insulating film 14 and the insulating film 13, and then the insulating film 11! J
The insulating film 10 can also be formed to a predetermined thickness by selectively oxidizing the upper surface of the semiconductor substrate 1 on which the IO is provided. Insulating film 1 thinner than the predetermined film thickness
In the step of re-oxidizing the upper surface of the semiconductor substrate 1 on which 0 is provided, it is necessary to provide an oxidation mask made of, for example, a silicon nitride film over the insulation film 13 and over the insulating film 14.

[Example II] Example (2) uses the second gate isolated R film of the memory cell.

For example, a silicon oxide film obtained by CVD technology, a silicon nitride film, and a silicon oxide film obtained by oxidizing this silicon nitride film are combined into one
It is something that can be achieved.

No. 172 is a diagram for explaining the method for manufacturing EPR○r of Example 2 of the present invention, and region X is.

A cross-sectional view of the memory cell in the manufacturing process, region Y.

High-voltage MIS that constitutes the write circuit in the manufacturing process
A cross-sectional view of the FET, region Z, is a cross-sectional view of a normal voltage MI S FET that constitutes a peripheral circuit in the manufacturing process.

As shown in FIG. 17, first, the steps up to the steps shown in FIG. 2 of Example I are performed.
The SiO2 film 29 is formed by D or plasma CVD, etc.
Deposit.

In the second gate insulating film formed by oxidizing the conductive layer 7 made of a polycrystalline silicon layer, the film thickness varies depending on the impurity concentration of the conductive N7. However, by using the silicon oxide film 29 formed by CVD as the second gate electrode, the second
The gate insulating film can have a predetermined thickness. next,
A silicon nitride layer 30 is formed on the silicon oxide layer 29 by, for example, CVD. This silicon nitride Pj30 will later be used as an etching mask and as a heat-resistant oxidation mask in a thermal oxidation process for forming a gate insulating film of a normal voltage MISFET. Furthermore, the silicon nitride film 30 is used to constitute the second gate insulating film of the memory cell.

The subsequent manufacturing process is the same as the manufacturing process described using FIG. 3 and subsequent figures of Actual tIi Example I, and will therefore be omitted.

Note that the second gate insulating film can also be composed of the silicon oxide film 29, the silicon nitride film 30, and a silicon oxide film formed by oxidizing the upper surface of the silicon nitride film 30. The silicon oxide film on the top surface of the silicon nitride film 30 is as follows.

It is formed in the thermal oxidation process used to form the insulating films 10 and 13.

Silicon oxide film 29 deposited by CVD etc.
By using the silicon oxide film 29 as the second gate insulating film of the memory cell, the thickness of the silicon oxide film 29 is not affected by the impurity concentration of the conductive layer 7.

Errors in the thickness of the second gate insulating film of the memory cell can be reduced. Therefore, yI of 61 reports of memory cells
The electrical characteristics of writing and reading can be improved.

Note that in this embodiment, the silicon oxide film 29 is formed by CVD.
was used only to form the second gate insulating film of the memory cell, but it is also used for high 1 voltage M I S FET or normal voltage M
It can also be used to constitute a gate insulating film of an ISFET.

[Example ■] Example ■ is an insulating film formed by depositing a second gate insulating film of a memory cell and a gate insulating film of a high-pressure MISFET that constitutes a write circuit, and a polycrystalline silicon layer or It is composed of a silicon oxide film formed by thermally oxidizing a single crystal silicon layer.

Figures 18 to 20 show EPRO? of Example ①. FIG. 4 is a diagram for explaining the manufacturing process of No. 4, and in each time, region X is a cross-sectional view in the manufacturing process of the memory cell, region Y is a cross-sectional view in the manufacturing process of the high-pressure MI S FET that constitutes the write circuit, Region Z is a cross-sectional view in the manufacturing process of a normal voltage MISFET that constitutes a peripheral circuit.

First, the conductor 1'! ! Layer 7 and sidewall spacers 9 on its sides are formed in the same manner as shown in FIG. 2 of Example 1. At this time, in this example, the thermal oxidation mask 8 in Example I is not formed on the conductive layer 7, and after the sidewall spacer 9 is formed, the region Y where the high voltage withstand voltage M5FET and the normal voltage MISFE are provided is The Z insulating film 5 is removed in the same manner as in Example 1.

Next, as shown in FIG.
are sequentially formed over the entire upper surface of the semiconductor substrate 1. Normal pressure resistance M
Silicon oxide formed in ISFET formation region Z [29
And the silicon nitride film 30 is selectively removed by etching. In the etching process, the memory cell formation region and the high voltage MISFET formation region are
A mask made of resist is provided.

Next, as shown in FIG.
6. Next, the silicon nitride film 30 is removed.

Next, as shown in FIG. 20, the entire semiconductor substrate I is oxidized again in an oxidizing atmosphere. In this step, the upper surface of the m-conducting layer 7 is oxidized through the a-oxide silicon film 29.
Guide iT! A silicon oxide film 31 is formed between the silicon oxide film 57 and the silicon oxide film 29 by thermal oxidation. In addition, high withstand voltage M
The main surface of the region Y where the ISFET is provided is also oxidized, and a silicon oxide film 31 is formed. That is, high withstand voltage M r
The gate insulating film of SFET is composed of a silicon oxide film 31 formed by thermal oxidation and the silicon oxide film 29.

Furthermore, the thickness of the insulating film 13 increases due to the oxidation step. Therefore, in the thermal oxidation process for forming the insulating film 13 shown in FIG. 19, after the thermal oxidation process shown in FIG. There is.

The gate insulating film of the high voltage MISFET is composed of an insulating film 1o formed by oxidizing the upper surface of the semiconductor substrate 1, and a silicon oxide film 29 formed thereon by CVD technology, so that high 1j voltage can be achieved. MISFF.

Since dielectric breakdown due to the pinhole in the gate isolation #flQ of T can be prevented, the electrical reliability of the high II voltage MISFET can be improved.

Note that after the silicon oxide film 31 is formed by oxidizing the upper surface of the conductive layer 7 and the main surface of the semiconductor substrate 1 on which the high i1 pressure MISFET is provided, the silicon oxide film 29 obtained by, for example, CvD technology may be formed. can. Further, the silicon oxide 1!129 is formed on the upper part of the conductive layer 7,
It can also be provided either above the region Y where the high breakdown voltage MISFET is provided or above the region Z where the normal breakdown voltage MISFET is provided. Further, the silicon oxide film 2
9 as a conductive layer 7. It can also be provided above each of the regions Y and Z where the high breakdown voltage MI S FET and the normal breakdown voltage M f S FET are provided.

In addition, in the fifth embodiment, a silicon oxide film 2 made of CVO or the like is used.
9 is formed, the silicon oxide film 31 is formed by thermal oxidation.
However, after forming this silicon oxide film 31,
The silicon oxide film 29 can also be formed by CVD or the like.

[effect] According to the novel technology disclosed by this application.

You can obtain the following effects.

(1) Gate insulating film of high voltage MIS FET.

The film is formed thinner than a predetermined thickness in advance, and then the gate insulation film of the high voltage MISFET is formed in the same process as that of forming the second gate insulation film of the memory cell and the gate insulation film of the normal voltage MISFET. Form a film to a predetermined thickness,
Furthermore, after forming the second gate insulating film of the memory cell, the high voltage MISFET and the normal breakdown voltage MISFET are connected.
By introducing the impurity for adjusting the threshold voltage of T, it is possible to prevent the impurity from unnecessarily diffusing into the semiconductor substrate and the well region.

(2) From (1) above, high voltage M that constitutes one peripheral circuit
The threshold voltages of the r S FET and normal voltage MISFET can be set satisfactorily.

(3) According to (1) above, especially P channel type cavity pressure resistance M
Since the depletion layer in the channel region of the I S FET can be prevented from extending deeply into the well region, bunch-through between the source region and the drain region of the high voltage MISFET can be prevented.

(4) According to (1) to (3) above, the electrical characteristics of the MI S FET constituting one peripheral circuit can be improved.

(5) According to (3) above, the channel length of the high voltage MIsFET can be reduced, so the semiconductor memory t! The degree of integration of devices can be improved.

(6) According to (1) above, normal voltage MI S FET
In particular, since the mutual conductance can be improved, the electrical operation speed can be improved.

(7) Gate insulating film of high voltage MIS FET.

In advance, high voltage MISFET and normal resistance 11EMISFET
The gate h6 is thinly formed so as to have a film thickness difference of that of the B film, and then the high voltage is By forming the gate insulating film of the IT pressure MI S FET, the gate insulating film of the high voltage MI S FET can be formed to have an appropriate thickness.

(8) According to (7) above, the gate insulating film of a normal voltage MISFET formed by oxidizing semiconductor substrates with different oxidation rates and the conductive TI! are formed in the same thermal oxidation time. !
Only the second gate insulating film of the memory cell formed by oxidizing (polycrystalline silicon layer) can be used. By this, by controlling the time of the oxidation step,
The gate insulating film B and the second gate insulating film of the normal voltage MISFET can be formed to have appropriate thicknesses.

(9), previous 2 (7) 4: The time required for the dedicated thermal oxidation process for forming the gate insulating film of the high voltage MISFET can be reduced.

(10) By using a silicon oxide film deposited (by CVD, etc.) on the conductive layer that will become the floating gate of the memory cell as the second gate insulating film of the memory cell, the film thickness of the pre-pQ silicon film can be reduced. Since it is not affected by the impurity concentration of the thick conductive layer (polycrystalline silicon M) that becomes the floating gate, it is possible to reduce errors in the thickness of the second gate insulating film.

(1]) According to (10) above, electrical characteristics such as R writing and reading of information in a memory cell can be improved.

(+2), according to (10) above, the second gate insulating film is made of a silicon oxide film, this silicon oxide support and a conductor W1M.
By forming an insulating film (thermal oxidation film) between the first and second electrodes, dielectric breakdown due to pinholes can be prevented.

(13) According to (12) above, the electrical reliability of the EPROM can be improved.

(14), gate isolation B film of high voltage MI S FET.

The structure consists of an insulating film formed by oxidizing the upper surface of the semiconductor substrate or well region, and a silicon oxide film deposited on top of this by CVD technology, etc., which prevents Ma destruction due to pinholes in the gate insulating film. can be prevented.

(] 5) According to the above (14), high voltage MISFET
It is possible to improve the electrical reliability of the

As above, the invention made by the present inventor has been explained in detail based on the embodiments; however, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, the normal voltage MISFET may be a p-channel type, and the high voltage MISFET may be an n-channel type.Furthermore, these and the above embodiments may be formed on one substrate in various combinations.

The present invention can be applied not only to p-type semiconductor substrates but also to semiconductor memory devices using n-type semiconductor substrates and P-type well regions.

Furthermore, it can be applied to semiconductor integrated circuit devices such as DRAMs having two layers of gate electrodes. Furthermore, the present invention is applicable not only to semiconductor memory devices but also to a wide variety of semiconductor integrated circuit devices.

[Brief explanation of drawings]

1 to 16 show an EPROM of embodiment i of the present invention.
1 to 6 are diagrams for explaining the manufacturing method of
8, FIG. 10, and FIG. 12 are cross-sectional views of the memory cell in the manufacturing process. 7, 9, and 13 are plan views of the memory cell manufacturing process. FIG. 14 is a cross section 2 taken along the XI'V-XIV cutting line of section 13. FIG. 15 is a floating circuit. High voltage MISFE that constitutes
A cross-sectional view of the manufacturing process of T. Figure 16 shows the normal withstand voltage MI 5FE that constitutes the peripheral circuit.
It is a sectional view in the manufacturing process of T. PfS17 diagram is an EPROM of the implementation fillf of the present invention.
Figures 18 to 20 are diagrams for explaining the manufacturing method of EPR○ of Example m of the present invention.
! It is a figure for explaining the manufacturing method of -4. 1° Semiconductor substrate, 2 Well region, 3 Field insulating film, 4 Channel stopper region, 5.10
゜Engineering 1.13.14.19.25.29.31...Insulating film, 6.12.15.16.20...Resist Jun,
7.17.18.27.28... conductive layer, 8,30,
・Electrified mask for heat, 9.22 ・Side wall, 2
1.23.24...Semiconductor region, 26...Connection hole.

Claims (1)

[Claims] 1. First M having a first gate electrode and a second gate electrode
ISFET, second MISFET and second MISFE
A method for manufacturing a semiconductor integrated circuit device comprising: a third MISFET having a gate insulating film thinner than a gate insulating film of T; The second MI
A method for manufacturing a semiconductor integrated circuit device, comprising forming a part of a gate insulating film of an SFET. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first gate electrode is a floating gate electrode, and the second gate electrode is a control gate electrode. 3. The semiconductor integrated device according to claim 1 or 2, wherein the gate insulating film between the floating gate electrode and the control gate electrode is formed by oxidizing the upper surface of the floating gate electrode. A method of manufacturing a circuit device. 4. The gate insulating film of the third MISFET is connected to the second MISFET.
3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the method is formed simultaneously with a part of the gate insulating film of the SFET. 5. Before forming the gate insulating film between the first and second gate electrodes, the gate insulating film of the second MISFET is formed to be thinner than a predetermined film thickness. 2. A method for manufacturing a semiconductor integrated circuit device according to item 2. 6. The second and third MISFEs are formed using the step of forming a gate insulating film between the first gate electrode and the second gate electrode.
3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein after forming the gate insulating film of the second MISFET, the gate insulating film of the second MISFET is formed to a predetermined thickness.