JPS607422B2 - Transmission control method in signal transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission control method for a signal transmission system in which information to be transmitted is divided into blocks for transmission and reception, and the divided information is combined to reproduce the original information. The present invention relates to a transmission control method in a signal transmission system that can prevent data from being dropped during playback.

When exchanging continuous signals such as image signals and audio signals sent from a facsimile device, etc., or binary information sent from a data terminal device, etc., these signals are divided into blocks of a predetermined bit length. A transmission frame is formed by dividing each block with flag information, address information, check characters, etc., and the transmission and reception are performed using this transmission frame.

Furthermore, in a transmission system in which signals such as audio signals are transmitted that do not require ensuring so-called time transparency, in which the original signal can be reproduced from the transmission frame without taking the frequency period on the receiving side, each station on the signal transmission path is Each station is not necessarily synchronized with the transmitting station, and data is reproduced by each clock using its own frequency.

However, in this conventional transmission control system, if there is a relay station that exchanges transmission frequencies such as a block switching device between the transmitting station and the receiving station, the clock frequency for data reproduction at each station will not match. This method has the disadvantage that data may be duplicated or dropped at the relay station.

FIG. 1 shows a time chart of a transmission system in which stations are not synchronized.

In the figure, 11 and 12 indicate the information "F'ma flag," B and C indicate the output from each station, respectively. Also, A indicates the information to be transmitted,
D is reproduction information. On the transmitting side, the information to be transmitted is divided into 11 and 12 blocks for each block.
Add the flag F to the beginning of the block, and add the information 11, 1 of each block.
2 is converted into frequency information according to the transmission speed and transmitted.

On the receiving side, the aforementioned predetermined bits of data are sampled at the frequency of an oscillator provided within the receiving side device. At this time, since the signal transmission frequency and this sampling frequency are different, if the sampling frequency is lower than the transmission frequency, "one block of data will be reproduced as a long line as shown by the wavy line C in Figure 1. Therefore, before all of the data in one block has been reproduced, the next block of data is received, resulting in a period (indicated by the shaded area in Figure 1D) during which the data is duplicated.Also, when the sampling frequency is If the transmission frequency is higher than the transmission frequency of the transmitter, a blank period occurs after the -flock length data is reproduced, and the message ``Continuous data cannot be reproduced.''

In other words, a period of data loss occurs. For this reason, the conventional transmission control method has the disadvantage that when a continuous signal such as an audio signal is transmitted, unnecessary noise is generated for each block or the audio is interrupted. SUMMARY OF THE INVENTION An object of the present invention is to provide a transmission control method for a signal transmission system capable of reproducing continuous data by eliminating the above-mentioned drawbacks.

In order to achieve the above object, the present invention writes received block information into a buffer memory, and when reading out the block information, the buffer memory IJI is changed in writing speed according to the number of information to be accumulated, and continuous data is stored. The data is read out without interruption, and will be explained below using an example.

FIG. 2 is a block diagram of a signal and transmission system according to an embodiment of the present invention, FIG. 3 is a block diagram of main parts, and FIG. 4 is a time chart.

In the figure, TI~T3 is the station, MIC is the microphone, AD/AD converter, CLI~2 is the clock generator, CPUI~3 is the control device, MEMI~3 is the memory, TI~3 is the transmission interface section, IFR2 ``IFR3 is a reception interface section, CONT is a control section, and DA is a digital-to-analog converter.

In Fig. 2, for example, when a continuous audio signal is input from the microphone MIC of the station TI, the analog signal is converted into a digital signal based on the clock signal of the clock generator CLI.
Convert with converter ADI.

The audio information converted into a digital signal is sent to the control device CP.
It is stored in the memory M old MI under the control of the UI. The voice information stored in the memory M town MI is divided into blocks by the interface section IFTI, and control signals such as flag information, address information, and check character are added to the block and sent out over the line L'. In the station T2, the signal from the line LI is received by the interface unit IFR2, and is temporarily stored in the memory MEM2. The control device CPU2 identifies whether or not the above-mentioned address information of the accumulated data specifies the own station. supply data. Also, if you do not specify an eye station,
The station T2 outputs this data from the memory M and M2 using the clock of the clock generator CL2, and sends the data across the line at the interface section T2 at a speed corresponding to the speed of the line L2. In station T3, the interface unit bait R3 receives and reproduces the signal in the same way as station T2, and the signal is stored in the memory MEM.
3, and then stored in the memory M under the control of the control unit CONT.
The data is read out while changing in accordance with the number of blocks stored in the old M3, and continuous data is supplied to the DA converter DA.

The output of the DA converter DA is notified to the user of the station T3 as audible audio information via a converter such as a speaker. FIGS. 3 and 4 are block diagrams and time charts for explaining the control unit CONT in detail.

Note that it is clear that the control of this control unit CONT can also be provided within the control device CPU3, which determines, for example, the operation sequence of the device. In the figure, WAC is a write address counter, RAC is a read address counter, Fm0 is a fiber register counter, PC is a phase comparison circuit, SWC is a switch controller, SW is a switch, and OSC is an oscillator. In addition, the phase comparator circuit PC is connected to each counter WAC, R.
By comparing the count value with AC, in this embodiment, if more than 1 block information worth of data remains in the buffer, the output is set to Peru, and the data of 1 block information or less remains in the buffer. When it is on, the output is set to level 0. The memory MEM has a capacity to store block information of three blocks, and writes the write data WD to the address specified by the address counter WAC. The data RD is controlled to be read from the address specified by the address counter RAC. Register F'0 is a so-called first-in, first-out register in which input data is immediately output and stored in the order in which it was input.

In FIG. 4, the highest BI to B13 indicates the unit of each block information, and the delimiter between each BI to B13 indicates the block flag signal position, that is, the timing of the rise of the flag information received at the beginning of each block information. It shows.

WBFBI to WBFB3 indicate the write address of the memory MEM, and RBFBI to RBFB3 indicate the mystery address of the memory M old M, and show the state of writing or disclosure of block information as time passes.

Next, FIG. 3 will be explained with reference to FIG. 4.

When one block of write data WD is input, the write address counter WAC counts the clock signal formed within the device itself or the clock signal formed by the received data and this block signal, and calculates the counted value. is supplied to the memory MEM as the write address WBFBI of the memory M old M.

This address specifies, for example, the block buffer BFBI, and the fourth address is assigned to the block buffer BFBI.
The block information BI shown in the figure is accumulated. Then the second
When block information B2 is input, the address counter WA
C is address WB specifying block buffer BFB2
Count up to FB2.

Further, when the read address counter RAC is driven, the count output of the read address counter RAC is supplied to the memory MEM as the read address RBFBI. At this time, the count value of the issue address counter RAC and the count value of the write address counter WAC are the same as those of the phase comparator circuit RC.
are compared. For example, in the case of the count values of the address counters WAC and RAC shown in FIG. data has been accumulated, and the output of the phase comparator circuit PC becomes zero. The switch controller SWC detects this level 1 signal and sends the lower frequency pulse PI of the output of the oscillator PSC to the lower frequency address counter RA.
Switch SW is switched to supply the signal to C. For this reason, the speed at which data is read from memory M (old M) becomes slow. The extracted data RD is input to the FIFO register, and its output is supplied to the above-mentioned DA converter.

Flock information B3, B4, . . . B5, B6 is also written to the memory MEM in the same manner as described above.

Here, when the phase comparator circuit PC detects that one block information or more block information has been stored in the memory MEM, for example, the write address counter WAC outputs a count value when all block information B7 has been written. , and the issue address counter RAC is block information B5
When outputting the count value after all reading of
Two blocks of block information B6 and B7 are stored in the memory MEM, and when this is detected, the output is set to level 1 and the switch SW is switched via the switch control SWC. Therefore, among the outputs of the oscillator PSC, a high frequency pulse Ph that increases the reading speed is supplied to the read address counter RAC. When the discussion speed becomes faster and the write address counter WAC again outputs a count value indicating the completion of writing of the block information BIO, and the discussion address counter RAC outputs a count value indicating the completion of reading the block information BIO, the phase Comparison circuit PC
detects that only one block of block information is stored in the memory M and switches the switch SW via the switch controller SWC as described above.

Therefore, a low frequency pulse PI is supplied from the oscillator OSC to the read address counter RAC, and the block information BII is read out by slowing down the address designation speed. Therefore, even if each block of information is expanded (or compressed) by a transmission frequency converter or the like, the reading speed of the memory MEM can be changed for each block, and the received data can be read without duplication or omission. be able to.

In addition, the frequencies of the read pulses Ph and PI used in the above embodiment are as follows: fr is the clock frequency of the transmitting station, fh is the high frequency of the receiving side, 8 is the low frequency, and the stability of each oscillator is △ratio, △. f? , if the margin is △, each enemy fT
+△fT+△+△fh n=fT+△fT-(△+△fl).

For example, the normal PCM-CODE in which audio information is transmitted
Considering the case of C (coder, decoder), fT=GoH
Z, assuming that the clock stability △ of each oscillator is the blood of soil 2, and the margin △ and the stability of the oscillator △fT, △fh are equal, then enemy = 8 x 1 p13 x 20XIO - 6 x 8 x 1 P8
000.48 (Sunday 2) 8 = 8xl pi (3 x 20 x 10
-6×8×1pi) 7999.52 (HZ).

As described above, according to the present invention, continuous data stored in the buffer memory and divided into plots is read out by changing the argument speed, so that there is a signal between each received signal. A signal transmission system that can reproduce a signal without causing noise or no-signal state even if there is a period in which there is no signal, or even if subsequent block information is received so that it is overlapped while the previous block information is being reproduced. A transmission control method is realized.

[Brief explanation of drawings]

FIG. 1 is a time chart of a conventional transmission control system, FIGS. 2 and 3 are block diagrams and main part block diagrams of an embodiment of the present invention, and FIG. 4 is a time chart thereof. In the figure, 11, 12, etc. are transmission information, F is a flag, and T
I9 to T3 are stations, MIC is microphones, CPUI to CPU3
is a control device, AD is an AD converter, DA is a DA converter, I
FT1, IFT2, IFR2, IFR3 are interface sections, CL1, CL2 are clock generators, M old MI~
3 is memory. Hair 2, 3, 4

Claims (1)

[Claims] 1 The transmitting side divides the information to be transmitted into predetermined units and sends them out as block information, and the receiving side demodulates the block information using a sample clock signal based on the block information and reproduces it as continuous information. In a transmission control method in a signal transmission system, a buffer memory for storing block information in accordance with the sample clock signal;
A discriminating means for discriminating the number of blocks of block information stored in the buffer memory; and a plurality of successive clock signals having different frequencies and successively outputting at different speeds depending on the number of blocks of block information stored in the buffer memory. 1. A transmission control system for a signal transmission system, characterized in that the plurality of read clock signals are switched and supplied to the buffer memory according to the number of blocks of block information stored in the buffer memory.