JPH0831104A - Digital information recording system and recorder - Google Patents

Abstract

PURPOSE:To obtain a digital information recording system and a recorder capable of holding a synchronous relation between a packet and a block when a digital signal with a packet length different from a recording block length is recorded in the system and the device recording audio and video inputted constituting the packet of a fixed length. CONSTITUTION:When a digital signal 40 inputted constituting the packet 41 with the data of (a) pieces is recorded on a recording medium in block unit, an enlarged packet adding the data of L pieces to the data of (a) pieces included in one packet is constituted. Then, the data included in the enlarged packets of (m) pieces are divided to (n) blocks (where, (a+L)Xm/n is a natural number, (a), L, (m), (n) are natural numbers), and the data of (b) pieces (b is a natural number) adding the data of (j) (j is a natural number) pieces to the data of {(a+L)Xm/n) pieces are recorded in respective blocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information signal recording system, and more particularly to a digital information recording system and recording system suitable for recording audio and video which are input by forming fixed length packets. Regarding the device.

[0002]

2. Description of the Related Art Journal of Television Engineering, Vol. 47, No. 4 (1
993) as described on pages 494 to 497,
A system has been considered in which digital software for audio or video is transmitted via radio waves or cables and recorded at each home.

[0003]

When inputting audio or video digital software according to the above-mentioned prior art, it is possible that the input digital signal has a fixed length packet structure.

For example, as shown in FIG. 3, a video signal 42
And an input digital signal 40 including a voice signal 43 and the like.
In this case, a header-41 may be added to 188 bytes to form one packet. In each packet, the header-41 has a 1-byte sync signal 44,
It consists of 4 bytes of 3 bytes of header-information 45, and the remaining data portion 46 may be the video signal 42 or the audio signal 43, or additional information (not shown).

Further, in a recording apparatus, an input signal is generally divided into blocks of fixed length and recorded on a recording medium.

For example, in a consumer digital VTR, as shown in FIG.
ID signal 51 of 0 and 3 bytes, data 54 of 77 bytes
Alternatively, 90 bytes of the C2 parity 52 for error correction and the C1 parity 53 of 8 bytes for error correction form one block and are recorded.

The digital signal 40 shown in FIG. 3 is converted into a consumer digital VTR having the recording format shown in FIG.
When recording with, the packet length of the input signal is different from the block length of the recording signal.

In the conventional recording apparatus, when recording a signal having a packet length different from the block length of the recording signal, the packet must be divided irregularly, and the synchronous relationship between the packet and the block cannot be maintained. There is a problem that block management becomes impossible and it becomes difficult to determine a variable speed reproduction area at the time of variable speed reproduction.

The object of the present invention is to solve the above problems,
It is an object of the present invention to provide a digital information recording system and a recording device capable of recording a digital signal having a packet length different from the block length of a recording signal by regularly dividing it into the recording signal block length.

[0010]

In order to achieve the above object, in the recording method of recording a digital signal, which is formed by forming packets by a pieces of data and is input, in a recording medium in block units, the one packet Constructs an expanded packet in which L pieces of data are added to a pieces of data included in
The data contained in the m number of the expanded packets is divided into n blocks (where (a + L) × m / n is a natural number, a, L, m,
n is a natural number) and the above {(a + L) × m /
It suffices to record b (b is a natural number) data in which j (j is a natural number) data is added to n} data in each block.

In particular, a = 188, b = 77, L = 2, m
= 2, n = 5, and j = 1, the system can be applied to the system described in the related art.

Further, L pieces of data may be added after k pieces of specific data are deleted from a pieces of packet data. In this case, a = 188, b = 77, k = 1, L =
3, m = 2, n = 5, j = 1.

As the L additional data, a parity for error detection or error correction of the data included in the packet may be used.

[0014]

The data amount ((a + L) m of the expanded packet in which L pieces of data are added to the data of a byte per packet
Number) and the number of data (b) that can be recorded in each block of the recording signal can be expressed by a simple integer ratio (m / n), the data of m packets is completed in n blocks. Then, the blocks of the recording signal for the packet of the input signal can be easily managed.

Further, the data (L
By effectively utilizing the data added to each block (j pieces), the reliability of the data in recording and reproduction can be improved.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a recording format of a digital information recording apparatus according to the present invention. In FIG. 4, 105 to 109 are recording blocks, 50 is a recording synchronization signal, 51 is an ID signal, 102 is a block ID indicating a block number, 103 is data, and 53 is C1 parity. The recording format is the same as that of the recording format. Further, 114 and 115 are headers, 112 and 113 in the packet shown in FIG.
Is additional data consisting of 2 bytes.

Here, the data of 2 packets of the input digital signal 40 having the packet structure shown in FIG. 3 is divided into 5 blocks.

That is, the head of the data portion of each block (77 bytes of the data 54 in FIG. 3) is used as a block ID for identifying 5 blocks and the like, and two packets are stored in the remaining 76-byte portion 103. Place the packet signal of.
The first packet in 36 bytes of the first half 110 of the block 0 (105), the block 1 (106), and the block 2 (107), the 38 bytes of the second half 111 of the block 2 (107), the block 3 (108), and the block 4 2 in (109)
Put a packet eye. Further, by adding 2 bytes each of the additional data 112 after the first packet and the additional data 113 after the second packet, all 5 blocks can be converted into a packet signal of 76 bytes, The recording format can be completed with 2 packets and 5 blocks.

Since the additional data 112 and 113 need only add 2 bytes after each packet signal,
The same operation is performed in each block and can be executed by simple processing.

By the way, in general, adding data and recording has a drawback of increasing redundancy, but addition of several bytes as in the present embodiment does not substantially cause a problem. Rather, the management of the input signal packet and the recording signal block is facilitated, so that an extremely large effect can be obtained when selecting the reproduction area, for example, during variable speed reproduction. . If the present invention is not used, the packet-block synchronization relationship cannot be maintained, and packet-block management becomes virtually impossible.

Furthermore, placing the parity for error correction in the additional data 112 and 113 is effective in improving the reliability of the reproduced signal in recording and reproducing. This parity is a CRC code, a Lead Solomon code, etc.
An error correction code used in ordinary digital transmission may be used. Also, as this correction code block, 1
It may be completed in packets, 5 blocks in 2 packets, or 2 × n packets-5 × n blocks (n is a natural number) blocks.

The additional data 112 and 113 are set to 1
2 blocks 2 (107) as 4 bytes collectively in one place
Position of the center 112 of the, or the last 113 of block 4
However, in this case, since it is necessary to change the processing in the odd number packet and the even number packet, there is a drawback that the processing becomes complicated. Therefore, it is better to use the present invention. .

FIG. 2 shows a recording / reproducing apparatus for a digital information signal having a recording format according to the present invention. In the figure, 300 is a recording processing circuit, 32 is an input terminal for inputting an input packet signal 40, and 20 is a packet header-4.
Header-detection circuit for detecting 1, 114, 115, 21
Is a data adding circuit for adding the additional data 112 and 113, 22 is a memory circuit, 35 is an address generating circuit for controlling the address of the memory circuit 22, and 37 is a block ID 102.
A block number adding circuit for adding a number, 23 an encoding circuit for adding the parities 52 and 53, 24 a modulating circuit,
Reference numeral 25 is a switch, 30 is a rotary head, and 31 is a magnetic tape. Further, 301 is a reproduction processing circuit, 26 is a demodulation circuit, 27 is an error correction circuit, 28 is a block number detection circuit, 29 is a storage circuit, 34 is an address generation circuit for controlling the address of the storage circuit 29, and 33 is a reproduction packet signal. Is an output terminal for outputting.

At the time of recording, the headers 114 and 115 are detected from the packet signal 40 input through the input terminal 32, and the address generation circuit 35 is controlled to store the format shown in FIG. A write address for the circuit 22 is generated. Further, the additional data is written in the positions 112 and 113 by using the data adding circuit 21. This data may be fixed data or error correction parity as described above. When writing parity,
The data addition circuit 21 functions as a parity addition encoding circuit. The block ID 102 is added by the block number adding circuit 37. The signal once stored in the storage circuit 22 is read out again, the C2 parity 52 and the C1 parity 53 are added by the encoding circuit 23, and the recording synchronization signal 50 and the ID signal b51 are further provided by the modulation circuit 24.
And the like, and modulation processing is performed, and the data is recorded on the magnetic tape 31 by the rotary head 30 via the switch 25.

At the time of reproduction, the reproduction signal reproduced by the rotary head 30 is sent to the demodulation circuit 26 via the switch 25, the recording synchronization signal 50 and the like are detected, and the error correction circuit 27 detects the C1 parity 53, The error is corrected by using the C2 parity 52 and written in the storage circuit 29. At that time, the block ID is detected by the block number detection circuit 28.
By detecting 102 and controlling the address generation circuit 34, the writing state of the memory circuit 29 is reproduced in the same state as the recording format of FIG. Under the control of the address generation circuit 34, the signal stored in the storage circuit 29 excluding the additional data 112 and 113 is read, the packet signal 40 is reproduced, and the packet signal 40 is output from the output terminal 33.

Further, as the additional data 112 and 113,
When parity is used, as shown in FIG. 5, the parity detection circuit 36 detects and corrects an error to improve the reliability of the reproduced signal.

Further, in FIG. 3, the synchronization signal 44 in the header 41 consisting of 4 bytes is fixed data which is determined in advance, so it is not always necessary to record it in the tape 31.

The recording format in this case is shown in FIG. The headers-162 and 163 are only 3 bytes of the header-information 45 shown in FIG. 3, and therefore the additional data 16
0 and 161 are 3 bytes. When the additional data is some kind of information such as parity, the amount of information increases, and particularly in the case of parity, it has an effect of improving the detection ability and correction ability in parity detection.

FIG. 7 shows a block diagram of a recording / reproducing apparatus for this format.

At the time of recording, the address generation circuit 35 functions so that the signal excluding the synchronization signal 41 of the input packet signal 40 is stored in the storage circuit 22.

At the time of reproduction, the synchronization signal 41 is added to the signal read from the storage circuit 29 by the synchronization signal addition circuit 38, reproduced in the same packet structure as the packet signal 40, and output from the output terminal 33. .

Further, as described above, the additional data 112, 1
It is conceivable to use 13, 160, and 161 as parity for error detection and correction, but in this case, the larger the number of data, the higher the capability. Therefore, block ID1
By omitting 02, the amount of additional data may be increased.

The recording format in this case is shown in FIG. In the figure, reference numeral 180 is a macro synchronization signal indicating that it is the head of block 0 (105). Further, the headers-162 and 163 are 3 bits in which the synchronization signal 44 is deleted, as in FIG. The additional data 181 and 182 have 5 bits, and when used as parity, their detection capability and correction capability can be improved.

The macro synchronizing signal 180 may be added by either the data adding circuit 21 or the block number adding circuit 37.

In the above description, additional data at the time of recording is added.
Although the addition of the data 112 and 113 is performed at the time of writing to the storage circuit 22 and the deletion of the additional data 112 and 113 at the time of reproduction at the time of reading out the storage circuit 29, the reverse operation may be performed. That is, the additional data 112, 11 at the time of recording
3 may be added when the memory circuit 22 is read, and the additional data 112 and 113 during reproduction may be deleted when the memory circuit 29 is written.

Furthermore, the block ID adding circuit 37 adds the block ID 102 at the time of recording at the time of reading from the memory circuit 22, but it may be added at the time of writing to the memory circuit 22.

Further, it has a block length different from that of FIG.
The present invention can be applied to a recording apparatus having a recording format as shown in FIG. In FIG.
The data section 84 consists of 112 bytes. FIG. 9 shows packet division in this case. In this case, 4 packets-7 blocks are completed. 8 bytes of additional data 215 to 218 are added to each packet. This additional data may be used as parity.

[0039]

According to the present invention, in a recording system and a recording apparatus for recording a digital signal having a fixed length packet structure, a digital signal having a packet length different from the block length of the recording signal is regularly recorded. The signal can be divided into block lengths for recording and the packet-block synchronization relationship can be maintained.

Further, by using the parity for error detection or error correction of the data included in the packet as the added data, there is an effect that the reliability of the data at the time of recording and reproducing is improved.

[0041]

[Brief description of drawings]

FIG. 1 is a format diagram showing an embodiment of a digital information recording system according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a digital information recording device according to the present invention.

FIG. 3 is a diagram showing a packet structure of an input signal.

FIG. 4 is a diagram showing an example of a recording format of the present recording apparatus.

FIG. 5 is a block diagram showing another configuration example of the digital information recording device according to the present invention.

FIG. 6 is a format diagram showing another embodiment of the digital information recording system according to the present invention.

FIG. 7 is a block diagram showing another configuration example of the digital information recording device according to the present invention.

FIG. 8 is a format diagram showing another embodiment of the digital information recording system according to the present invention.

FIG. 9 is a diagram showing another example of the recording format of the present recording apparatus.

FIG. 10 is a format diagram showing another embodiment of the digital information recording system according to the present invention.

[Explanation of symbols]

20 ... Header-detection circuit, 21 ... Data addition circuit, 28
... Block number detection circuit, 35 ... Address generation circuit, 3
6 ... Parity detection circuit, 37 ... Block number addition circuit,
38 ... Sync signal addition circuit, 40 ... Input packet signal, 4
1 ... Header-, 44 ... Sync signal, 50 ... Recording sync signal,
51 ... ID signal, 54 ... Data, 102 ... Block I
D, 103 ... Data, 112, 113 ... Additional data, 1
14, 115 ... Header-, 160, 161 ... Additional data
... 162, 163 ... Header-, 180 ... Macro sync signal, 181, 182 ... Additional data

Front page continuation (72) Inventor Takao Arai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Ltd.

Claims (30)

[Claims] 1. A recording system for recording a digital signal, which is composed of packets of a pieces of data and is inputted in a block unit, in a recording medium. Extended packets to which the data of the above-mentioned number is added, and the data included in the above-mentioned m extended packets are
n blocks (where (a + L) × m / n is a natural number, a,
L, m, and n are natural numbers) and are recorded separately. 2. The recording method according to claim 1, wherein j is a natural number in the {(a + L) × m / n} pieces of data.
B pieces of data (b is a natural number) with each piece of data added,
A digital information recording method characterized by recording in each of the blocks. 3. The recording method according to claim 2, wherein a = 1.
88, b = 77, L = 2, m = 2, n = 5, j = 1. A digital information recording method. 4. A recording system for recording a digital signal, which is composed of packets of a pieces of data and is inputted in a block unit, in a recording medium from k pieces of a pieces of data included in one packet. Data is deleted, L pieces of data are added to form an expanded packet, and the data contained in the m expanded packets is divided into n blocks (however, (a + L
-K) × m / n is a natural number, and a, k, L, m, and n are natural numbers), and recorded. 5. The recording method according to claim 4, wherein j (j is a natural number) pieces of data are added to the {(a + L−k) × m / n} pieces of data. Is a natural number) and the data is recorded in each of the blocks. 6. The recording method according to claim 5, wherein a = 1.
88, b = 77, k = 1, L = 3, m = 2, n = 5, j
= 1. A digital information recording system characterized in that 7. A digital information recording system according to any one of claims 1 to 6, wherein the L pieces of data are predetermined fixed patterns. 8. The recording method according to any one of claims 1 to 6, wherein the L pieces of data are data included in the packet.
A digital information recording method characterized in that it is a parity signal for error detection or error correction of data. 9. Claims 2, 3, 5, and 6
In the recording method described above, the j pieces of data are the n pieces of data.
A digital information recording method characterized by indicating a block number for identifying individual blocks. 10. The recording method according to claim 2, wherein a =
188, b = 112, L = 8, m = 4, n = 7, j = 0
A digital information recording method characterized by: 11. A recording apparatus for recording a digital signal, which constitutes a packet by a pieces of data and is inputted in a block unit, on a recording medium, wherein an input unit for inputting the digital signal and an input unit for inputting the digital signal. A head detection unit that detects the head of the packet from the input signal that has been input, and a included in the one packet by the control of the head detection unit.
First data adding means for adding L data to each piece of data to form an expanded packet, and m expanded packets generated by the first data adding means The recording means divides the data contained in the above into n blocks (where (a + L) × m / n is a natural number and a, L, m, and n are natural numbers) and records the divided data on the recording medium. Characteristic digital information recording device. 12. A recording apparatus according to claim 11, further comprising a second data adding means, wherein the second data adding means comprises {(a + L) × m / n} pieces of data. B (b is a natural number) data obtained by adding j (j is a natural number) data to
A digital information recording apparatus, wherein data is generated and the recording means records the b pieces of data in each of the blocks on the recording medium. 13. The recording apparatus according to claim 12, wherein a
= 188, b = 77, L = 2, m = 2, n = 5, j = 1
A digital information recording apparatus characterized in that 14. A recording apparatus for recording a digital signal, which is formed by forming packets by a pieces of data, into a recording medium on a block-by-block basis, the input means for inputting the digital signal and the input means. A head detecting means for detecting a head signal indicating the head of the packet from the input signal inputted, and k data from the a data contained in the one packet are deleted by the control of the head detecting means. ,
Third data adding means for adding L data to form an expanded packet, and data included in the m expanded packets generated by the third data adding means. N blocks (where (a + L−k) × m / n is a natural number, a,
A digital information recording apparatus comprising recording means for recording on the recording medium by dividing into k, L, m, and n). 15. A recording apparatus according to claim 14, further comprising a fourth data adding means, wherein the fourth data adding means comprises {(a + Lk) × m / n} pieces of data. -B pieces (b is a natural number) obtained by adding j pieces (j is a natural number) to the data
Digital information recording apparatus, wherein the recording means records the b pieces of data in each of the blocks on the recording medium. 16. A recording apparatus according to claim 15, wherein a
= 188, b = 77, k = 1, L = 3, m = 2, n =
5. A digital information recording apparatus characterized in that j = 1. 17. A recording apparatus according to any one of claims 11 to 16, wherein said first data adding means or said third data adding means includes said L predetermined fixed data. A digital information recording device characterized by being added. 18. A recording apparatus according to claim 11, wherein said first data adding means or said third data adding means detects an error in the data included in said packet. Alternatively, the digital information recording device is characterized in that the L number of parity signals for performing error correction are generated. 19. A claim 12, a claim 13, a claim 15,
17. The recording apparatus according to claim 16, wherein the second data adding unit or the fourth data adding unit includes j pieces of data indicating a block number for identifying at least the n pieces of blocks. -A digital information recording device characterized by generating data (per block). 20. The recording apparatus according to claim 12, wherein a
= 188, b = 112, L = 8, m = 4, n = 7, j =
A digital information recording apparatus characterized by being 0. 21. A digital information recording system according to claim 4, 5, or 6, wherein said k pieces of data are synchronization signals indicating the head of said packet. 22. A recording apparatus according to claim 14, 15, or 16, wherein said third data adding means is:
A digital information recording apparatus, characterized in that the head signal of the k packets detected by the head detecting means is deleted. 23. In a recording system for recording a digital signal, which is composed of a pieces of data in a packet and is inputted in a block unit, from a pieces of data included in one packet to k. Data is deleted and L data is deleted.
Data is added to form an expanded packet, and i macro synchronization signals and data contained in the m expanded packets are
n blocks (however, b = {(a + L−k) × m + i}
/ N, a, b, i, k, L, m, n are natural numbers)
A digital information recording system characterized in that the above-mentioned b pieces of data are recorded in each block. 24. The recording system according to claim 23, wherein a
= 188, b = 77, i = 1, k = 1, L = 5, m =
2. A digital information recording method characterized in that n = 5. 25. A recording apparatus for recording a digital signal, which is composed of packets of a pieces of data and is inputted on a recording medium in block units, by an input means for inputting the digital signal and the input means. A head detecting means for detecting a head signal indicating the head of the packet from the input signal inputted, and k data from the a data contained in the one packet are deleted by the control of the head detecting means. ,
Fifth data adding means for adding L data to form an expanded packet, and data included in the m expanded packets generated by the fifth data adding means. And b =
{(A + L−k) × m + i} / n, a, b, i, k,
L, m, and n are natural numbers), and a recording means for recording the b data in each block. 26. The recording apparatus according to claim 25, wherein a
= 188, b = 77, i = 1, k = 1, L = 5, m =
2. A digital information recording apparatus characterized in that n = 5. 27. A digital information recording system according to claim 23, wherein said L pieces of data are predetermined fixed patterns. 28. In the recording system according to any one of claims 23 to 24, the L pieces of data are parity signals for performing error detection or error correction of the data included in the packet. A digital information recording method characterized by. 29. A digital information recording apparatus according to claim 25, wherein said fifth data adding means adds said L predetermined fixed data. apparatus. 30. The recording apparatus according to claim 25, wherein the fifth data adding unit is the L number for performing error detection or error correction of the data included in the packet. A digital information recording device characterized by generating a parity signal of.