JPS60732A - アニ−ル方法 - Google Patents

アニ−ル方法

Info

Publication number
JPS60732A
JPS60732A JP58107843A JP10784383A JPS60732A JP S60732 A JPS60732 A JP S60732A JP 58107843 A JP58107843 A JP 58107843A JP 10784383 A JP10784383 A JP 10784383A JP S60732 A JPS60732 A JP S60732A
Authority
JP
Japan
Prior art keywords
wafer
temperature
semiconductor wafer
lamp
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58107843A
Other languages
English (en)
Japanese (ja)
Other versions
JPH057860B2 (en:Method
Inventor
Tatsumi Hiramoto
立躬 平本
Tetsuharu Arai
荒井　徹治
Yoshiki Mimura
芳樹 三村
Hiroshi Shimizu
洋 清水
Satoru Fukuda
悟 福田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ushio Denki KK
Ushio Inc
Original Assignee
Ushio Denki KK
Ushio Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ushio Denki KK, Ushio Inc filed Critical Ushio Denki KK
Priority to JP58107843A priority Critical patent/JPS60732A/ja
Publication of JPS60732A publication Critical patent/JPS60732A/ja
Publication of JPH057860B2 publication Critical patent/JPH057860B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P34/422—

Landscapes

  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP58107843A 1983-06-17 1983-06-17 アニ−ル方法 Granted JPS60732A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58107843A JPS60732A (ja) 1983-06-17 1983-06-17 アニ−ル方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58107843A JPS60732A (ja) 1983-06-17 1983-06-17 アニ−ル方法

Publications (2)

Publication Number Publication Date
JPS60732A true JPS60732A (ja) 1985-01-05
JPH057860B2 JPH057860B2 (en:Method) 1993-01-29

Family

ID=14469463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58107843A Granted JPS60732A (ja) 1983-06-17 1983-06-17 アニ−ル方法

Country Status (1)

Country Link
JP (1) JPS60732A (en:Method)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468576A (en) * 1981-06-29 1984-08-28 Fujitsu Limited Inverter circuit having transistors operable in a shallow saturation region for avoiding fluctuation of electrical characteristics
JP2002141298A (ja) * 2000-11-02 2002-05-17 Toshiba Corp 半導体装置の製造方法
US7345003B2 (en) 2004-12-24 2008-03-18 Fujitsu Limited Semiconductor device manufacturing method, wafer, and wafer manufacturing method
JP2008277696A (ja) * 2007-05-07 2008-11-13 Toshiba Corp 半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JAPANESE JOURNAL OF APPLIED PHYSICS=1980 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468576A (en) * 1981-06-29 1984-08-28 Fujitsu Limited Inverter circuit having transistors operable in a shallow saturation region for avoiding fluctuation of electrical characteristics
JP2002141298A (ja) * 2000-11-02 2002-05-17 Toshiba Corp 半導体装置の製造方法
US7345003B2 (en) 2004-12-24 2008-03-18 Fujitsu Limited Semiconductor device manufacturing method, wafer, and wafer manufacturing method
US7859088B2 (en) 2004-12-24 2010-12-28 Fujitsu Semiconductor Limited Semiconductor device manufacturing method, wafer, and wafer manufacturing method
JP2008277696A (ja) * 2007-05-07 2008-11-13 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPH057860B2 (en:Method) 1993-01-29

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