JPS607297B2 - Process input/output device failure diagnosis method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure diagnosis method for a process input/output device that is located between a central processing layer (CPU) and a process and controls input and output of process data to the CPU.

Conventionally, diagnosing the failure location of such process input/output devices is
This is generally done by a customer engineer with specialized skills, but in this case there are the following problems.

Until the customer engineer arrives at the site, the system will remain in an abnormal state and will not be able to operate normally. 0} In many cases, the customer engineer has no choice but to stop the system in order to collect the diagnostic data necessary to determine the location of the failure.

Whether or not the system can be restored quickly depends on the experience and technical capabilities of the customer engineer.

From the viewpoint of dealing with the above problems, it is desired to establish a diagnostic method for process input/output devices that enables simple maintenance by on-site personnel and is also effective as a means to assist customer engineers in diagnosis. There is.

This invention was made based on the above-mentioned technical background, and therefore, the purpose of this invention is to enable even field personnel who do not have specialized maintenance skills to perform emergency maintenance. Another object of the present invention is to provide a fault diagnosis method for process input/output devices that enables customer engineers to perform more accurate and prompt diagnosis and maintenance.

The main point of the configuration of this invention is that when diagnosing a process input/output device in which structural units such as cards (printed wiring boards) are arranged and connected in a tree (horizontal branch), each card is The present invention is configured to check whether or not correct predetermined data has been output at the output point, and to comprehensively view the results to determine which card is the faulty card.

Next, the principle of the invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a process input/output device, and is a diagram for explaining the principle of the present invention. Refer to the same figure.

In general, a process input/output device is connected to a CPU via a bus (not shown), and includes an adapter 1 that transmits and receives data to and from the CPU, a device 3 that inputs and outputs process data to and from the process, 3a, 3b, etc., and expanders 2, 2a, etc. that relay between the adapter and the device.Moreover, the adapter 1, expander 2, and device 3 are connected in a tree (gutter branch) shape.
The adapter, expander, and device are each constructed from one or more unit devices such as printed wiring boards. Therefore, when a failure occurs, maintenance is performed by finding out which printed wiring board is at fault and replacing that wiring board with a good one. Accordingly, the process input/output device shown in FIG.
By regarding card C3 as card C3, etc., the whole can be viewed as a tree-like connection of cards. Therefore, fault diagnosis of a process input/output device can be said to consist of finding out which card has a fault among a large number of cards connected in a tree. Now, in FIG. 1, for convenience's sake, attention will be paid to cards C, C2, and C2a.

Now, each output signal of card C,,C2,C father is A,B,B
,. If a failure occurs inside the device made up of these three sets of cards, the output signals of each part of the device will be in an abnormal state, but which output signal will be in the abnormal state differs depending on the location of the failure. For example, if card C fails, its output signal A will become abnormal, and therefore the signals B, B output from cards C2 and C in response to that signal will also become abnormal.

If the card C2 fails, its output signal B becomes abnormal, but the output signal B of the card C2a, which operates in response to the normal signal A from the card C, is normal. A similar result will occur if the card C2a fails. Therefore, in the case of a tree-like configuration as shown in FIG. 1, the location of the fault in the device where the fault has occurred can be determined by monitoring the state of the output signal of each card. however,
In FIG. 1, output signal B of card C2 and card C2
If the output signals B of a are both abnormal, the following two cases can be considered as the failure location. The first case is that cards C2 and C are both normal, but card C has failed and signal A is in an abnormal state, so cards C2 and C in response output an abnormal signal. It is. In the second case, card C is normal, but both cards C2 and C2a have failed, so signals B and B have become abnormal. However, in a device made up of this type of cards, the probability that a plurality of cards will fail at the same time is extremely low, so the diagnostic method according to the present invention regards such probability as zero. That is,
Since it is based on the premise that it is impossible for a plurality of cards to fail at the same time, in the above case, it is determined that card C has caused the failure. Above,
Having explained the principles of the invention, one embodiment of the invention will now be described in detail with reference to the drawings.

5 FIG. 2 is a block diagram showing an embodiment of the present invention.

In the figure, a CPU 13 and a process input/output device 14 are shown.
In addition, there are an operation signal bit pattern generation section 4, an initial signal bit pattern storage section 5, a bit pattern setting section 6, and a bit pattern operation section 7, 7.
A, the abnormal signal bit pattern storage section 8, the status signal bit pattern storage section 9, the faulty card determination section 10, the faulty card display device 11, and the control signal lines 12, 12a are connected as shown. Data is input and output between the CPU 13 and the process 16 via the process input/output device 14, and this input/output device 14 is the target of failure diagnosis.

The initial signal bit pattern storage unit 5 is a memory having a bit capacity equal to the total number of cards (printed wiring boards) arranged in a tree, which constitute the process input/output device 14, and stores the bit positions in the tree. Each card corresponds to each card in a predetermined order according to the form, and a logic 1, for example, is written in every bit position as an initial state.
When the bit pattern setting section 6 receives a diagnosis start command from the CPU 13 through the control signal line 12, the bit pattern setting section 6 transfers the memory contents of the initial signal bit pattern storage section 5 to the abnormal signal bit pattern storage section 8 and the status signal bit pattern storage section 9. is initialized as is. The input/output operation monitoring unit 15 monitors the input/output operation of the process input/output device 14, and detects structural units placed on the flow path of predetermined data input to the input/output device (i.e., detects failures due to data input/output). Since a test is performed for the presence or absence, constituent units (with test operation) and those that are not (with no test operation) are identified, and for the former, it is monitored whether predetermined data is correctly output.

The monitoring result is sent to the operation signal bit pattern generating section 4. The pattern generating section 4 determines which cards are in test operation and which cards are not in test operation, corresponding to each card (configuration unit) that constitutes the process input/output device 14, based on the information given by the monitoring section 15. A bit pattern is generated that indicates whether the card is in a test mode using logic 0s and 1s, and for cards that are in test operation, a bit pattern is also generated that is expressed as logics 1s and 0s depending on whether or not predetermined data has been correctly output.

Note that if the data input to the process input/output device differs, the data flow path will also change, so even if the card has no test operation, the card may change, so it is necessary to test various data many times. By inputting information over the entire range, it is possible to reduce the number of cards that do not perform test operations.
In this way, the operation signal bit pattern generation unit 4 generates, for each card constituting the process input/output device 14, first information indicating whether the card is a card with test operation or without test operation, and If an active card fails, it generates second information indicating whether it outputs correct data.

The first information is sent to the status signal bit pattern storage section 9 via the bit pattern operation section 7a, and among the bit positions in the storage section, the bit positions corresponding to the cards with test operation are changed from logic 1 to logic 1. lj is set to 0, and the bit position corresponding to the card with no test operation remains at logic 1. Note that the logical operation performed by the bit pattern operation section 7a is performed using the bit pattern signal of the first information sent from the operation signal bit pattern generation section 4 as TBP, and the bit pattern signal read from the status signal bit pattern storage section 9. When CBP is set, it can be expressed as follows. To TBP CBP→CBP However, < means logical product.

That is, when the bit signal of the first information sent from the operation signal bit pattern generation section 4 is logic 0 indicating no test operation, the pattern operation section 7a outputs its negation, that is, logic 1, and the pattern The logic product is ANDed with the logical 1 read from the corresponding bit position of the storage section 9, and the logical 1 that is the result is written to the corresponding bit position of the pattern storage section 9 again.

When the bit signal of the first information sent from the pattern generation section 4 is a logic 1 indicating that a test operation is present, its negation becomes a logic 0, and the bit signal is read from the corresponding bit position of the pattern storage section 9. Since the logic type with logic 1 does not hold, logic 1 is not written to the corresponding bit position of the pattern storage unit 9, and therefore the reset state of logic 0 is taken, and the card corresponding to the bit position is in test operation. represents something. The second information generated from the operation signal bit pattern generation section 4 is sent to the abnormal signal bit pattern storage section 8 via the bit pattern operation section 7, and the correct data is selected from among the bit positions in the storage section. Output card'
The corresponding bit position is set from logic 1 to logic 0.

Therefore, among the bit positions of the abnormal signal bit pattern storage unit 8, a bit position that takes logic 1 indicates that the card corresponding to that bit position is a card that does not perform a test operation, or is an erroneous output card that did not output correct data. It means that it is either. The logical operation of the bit pattern operation section 7 is 7.
Since it is the same as that of a, the explanation will be omitted. Now, in the faulty card determination section 10, the control signal line 1 is sent from the CPU 13.
It starts operating upon receiving a diagnostic output command signal via 2a.

That is, the information stored in the abnormal signal bit pattern storage section 8 and the status signal bit pattern storage section 9 is read out, the exclusive OR of both pieces of information is taken, and the result is output. The fact that a logic 1 is set in both the bit position of the storage unit 8 and the corresponding bit position of the storage unit 9 indicates that the card corresponding to the bit position is a card with no test operation. The signals are exclusive-ORed and the corresponding bit position is changed to logic 0. In the faulty card determination unit 10, if there is a bit position where logic 1 is set as a result of performing such logical processing, the card corresponding to the bit position is the card that has generated an intentional output, and therefore It can be determined that the card is malfunctioning. The position of each bit in the bit pattern is determined in a predetermined order corresponding to the tree-like arrangement of each card constituting the process input/output device.
If multiple cards are determined to be faulty, the highest card in the tree-like arrangement is determined to be the true faulty card for the reason explained earlier with reference to Figure 1. do. The result is displayed on the failure card display device 11. As explained above, according to the process input/output device failure diagnosis method of the present invention, the failure location can be automatically diagnosed even by on-site personnel who do not have specialized skills, so simple maintenance is possible. Additionally, customer engineers with specialized skills have the advantage of being able to use the diagnostic results to quickly recover from failures.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a process input/output device, and is a diagram for explaining the principle of the invention, and FIG. 2 is a block diagram showing an embodiment of the invention. In the figure, 1 is an adapter, 2 is an expander, 3 is a device, 4 is an operation signal bit pattern generation section, 5 is an initial signal bit pattern storage section, 6 is a bit pattern setting section, 7 is a bit pattern operation section, and 8 is a bit pattern operation section. Abnormal signal bit pattern storage section, 9, status signal bit pattern storage section, 10
11 is a faulty card determination unit, 11 is a faulty card display device, and 12 is a faulty card determination unit.
13 is a control signal line, 13 is a CPU, 14 is a process input/output device, 15 is an input/output operation monitoring unit, and 16 is a process. Spear' Zusai 2

Claims (1)

[Claims] 1 Process input/output device failure diagnosis to determine which component has failed in a process input/output device that is made up of component units such as printed wiring boards that are arranged and connected in a tree shape to be replaced during maintenance. A system that identifies structural units placed in the flow path of predetermined data input to the input/output device (with test operation) and structural units that are not placed in the flow path (with test operation), and confirms that the input data is correct for the former. A monitoring means for monitoring whether the output is output or not; based on the monitoring result, first information indicating whether a test operation is present or not for each component forming the input/output device; and in the case of a component with a test operation. , a second value indicating whether or not the predetermined data has been correctly output.
information generation means for generating the information; and first storage means for storing the presence or absence of a test operation for each constituent unit in a specific order of constituent units depending on the shape of the tree based on the first information; Based on the second information, the second storage means for storing whether or not predetermined data is output is read out for each constituent unit in the above order, and both the first and second storage means are read, and predetermined data is output with a test operation. A method for diagnosing failures in process input/output devices, comprising: a detecting means for detecting structural units that have failed in the above order; and a means for determining which structural unit has failed based on the detection results.