JPS5812011A - Input and output check system - Google Patents

Abstract

PURPOSE:To detect failure state of input and output sections, by picking up the content stored in an FIFO memory, comparing a reference value with the changing state of each input or output signal, and outputting the detected content if dissident. CONSTITUTION:An input state change detecting circuit 51 detects the change in the state of input signal. An input state storage FIFO61, an output state storage FIFO62 and time interval storages FIFO 63 and 64 are provided. When a study signal is given to a circuit 51, the change state and time interval of the input signals are stored to FIFO memories 61, 62, 63 and 64. When a test signal is given to FIFO memory pickup circuits 71 and 72, the contents stored in the memories 71 and 72 are picked up and input and output signals are compared at each signal by taking an inputted bit pattern signal as a reference value. If they are not coincident with each other even for a prescribed time, the number of the signal is displayed on deficient input and output number displays 91 and 92.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention monitors whether the input/output unit that processes input and output signals of a sequence control device is operating normally, and if there is an abnormality in operation, it will be detected immediately.

An example of a sequence control device related to the method of displaying abnormalities and issuing an alarm is as shown in Figure S.
Generally, it is composed of an input section 10/, a logical layer calculation section/#J, and an output section 10J.

Conventionally, an electromagnetic relay was used for the logical operation section IO, but now a transistor type non-contact relay or the result of logic decoding by a computer is used.

The input section iot and the output section ioy have functions that control input and output of sequence control, respectively, and if these parts do not operate normally, logic decoding will not be performed correctly.

Alternatively, the logical decoding results may not be correctly transmitted to the controlled object, which may result in a serious accident.

The maintenance personnel have an additional responsibility to find the defective parts of the input section 10/ and the output section 10J as soon as possible and restore them to normal operation.

However, conventionally, abnormality detection using K such as parity, zuku, and watchtogetai i- has been performed for the logic operation unit lOJ, but the input Its 10/
, abnormality detection is not performed in the output section 10J.

The present invention has been developed in view of these circumstances. In other words, one object of the present invention is to provide a method that, when such an abnormality occurs, displays numerically which part of the input/output section has become abnormal and issues an alarm to reduce the burden on maintenance personnel. do.

The sJ diagram is a block diagram showing the configuration of an embodiment of the input/output checking method according to the present invention.

Main circuit input/output check ifB 10! It is r.

31 is a state change detection circuit which, when the state of inputs l, ko, . It has the function of storing the input state and sending it to the memory 47 (first-in, first-out), and has an output state change detection circuit! f
This works similarly.

6J and jl are AND (logical product) circuits.

Input state storage FIFO memory 4/ is a state change detection circuit!
Status of input signal sent from l (bit pattern)
This is a table that stores sequentially. The size of the table is determined by the number of input signals, 1, and the number of input signal changes, mK. The output state storage unit 10 also operates in a similar manner with respect to the output signal.

U is an input state detection circuit that stores at 1srlfstl intervals 7170'-E, and detects at what time intervals changes in the input signal state occur. A similar operation is performed regarding the output signal in the review time interval storage 1/10 memory which has the function of monitoring the time at / and storing the time.

RI/ is an aeyo (first in, first out) method extraction circuit,
The input state is stored yxyo by the signal from the comparison circuit t/.
The F-factor has the function of sequentially reading out the input state bit patterns stored earlier from the memory 61 and sending them out to the comparison circuit INK! The pO memory extraction circuit Kuko also operates in a similar manner regarding the output signal.

The comparison circuit 1/ compares the on/off state of the bit pattern sent out from the 1x memory extraction circuit 1/ and the input signal from the input section for every 6 human input signals, and if there is an input signal that does not match, that input signal Any number from / to i is sent to the defective input circuit number display 9/, and at the same time a signal is given to the alarm buzzer 10. Also, when the bit pattern and input signal match, a match signal is generated! , emits F
o Activate the memory extraction circuit I, and the seventh FIIFO
The comparator circuit 1 performs a similar operation on the output signal to extract the next bit pattern from the memory.

1/ is a defective input circuit number indicator serving as a numerical display for displaying the defective number of the input signal issued from the comparator circuit l/. The defective output circuit number display - and - operate in a similar manner regarding the output signal.

The input state change detection circuit 31 and the output state change detection circuit j are operated by a learning signal Xs given from ms. Also, by the test signal X.

F engineering 10 memory extraction circuit/, Kuko, comparison circuit 1/*l
J works.

1041 is an output monitoring input section into which the output signal of the output section ios is input after being branched from the external output.

Next, the present invention will be explained in detail.

First, it is assumed that the test signal x8 is applied from the outside.

At the same time, the logic operation unit 1O starts operation in response to a sequence control suit signal (not shown), and the input signal from the input unit toi and the internal logic signal of the logic operation unit 10 cause @
The 10 science/arithmetic units perform certain automatic operations. Output signals l and c according to a determined order.

...j is emitted from the output section 10J.

Input signal 1. ko,...1 and output signal l, ko,...
. . . j changes its state in various ways as the sequence progresses. However, if the sequence control is operating normally, it is natural that the state of the input and output signals will change, that is, the pit pattern will change.

It has a certain pattern and order.

The bit pattern is detected one by one by the input state detection circuit j/and the output state change detection circuit S.

The input state storage memo IJ4/ and the output state storage 1 FO memory are stored in the changed order.

Next, test signal x4 is applied from outside.

It is assumed that the learning signal /,? J, the comparison circuit that- also starts operating.

That is, the input state is stored in the input state storage memory J&IJ6 and the input state is stored in the output state storage memory 1J4J.

The bit pattern of the output state is 1 yo extraction circuit.

It is read out by Cucco and sent to comparison circuits g/ and fJK.

Comparison circuits gt and g are human input signals using the bit pattern input when the learning signal X is on as a reference value.

Compare the output signals for each signal, and if they do not match even after a certain period of time has elapsed, select the manual signal and display the number of the output signal on the defective input circuit number indicator or defective output circuit number indicator. Displayed by device date.

What is the certain time when alarm buzzer 10 will sound at the same time?

Time interval storage ν This is the time extracted from the IFO memo IJ &3, 41I with a margin added.

If such a function is provided, even if a normal command is issued from the logic operation unit 102 and given to the output unit 10J, if the output unit 10JVca is always present, the output monitoring input unit 1ol
The abnormal signals of the output parts io and y are quickly detected through I, which greatly contributes to shortening the repair time of the output part 10J.In addition, even if an abnormality occurs in the input part 10/K, the contents are immediately detected. Therefore, the functions of the output state change detection circuit l, PIFO memory extraction circuit fuco, and comparison circuit IJ are the same as the input state change detection circuit! / Since the function is the same as that of the F λ power state change detection circuit! / .

Fxshi0 memory extraction circuit? A configuration in which only the / and comparison circuit it is required is also possible.

The crowd checking department shown in this example is even busier.

Input section 10/, logic operation section loJ and output section 10J
No matter what the configuration is or what sequence the control has, it is a single circuit configuration, and the variable is the number of input signals (/.

ko, ... 1), number of output signals (1, ko, ... song j
) and the number of times it changes (1, ko,...4m), (t
, ko, . . . n), it can be prepared as standard. In addition, if the reliability of the input/output section is high.

The present invention can be applied to the abnormal operation of the external EIS in accordance with this embodiment.

Thus, according to the two aspects of the present invention, abnormal states of the input section and the output section can be easily and quickly detected using a standard detection method.

[Brief explanation of the drawing]

FIG. 187 is a schematic diagram of a conventional sequence control device. Figure IJ is a block diagram showing the configuration of an embodiment of the present invention. / 04...Human power department, 101...Logic operation department,
101...Output unit, io-tei...Input unit for output monitoring, 10j...Input/output unit. Tsuk part, 10... Number alarm buzzer, jl... Input state change detection circuit, S co... Output state change detection circuit,! 3,
31...AND circuit, 4/...Input state storage FI
FO memory, 1 piece... Output status storage FO memory,
63. Review... Time interval storage yzyo memory, Kuha 7 pieces... Ae FO mesori extraction circuit, t/, 1 piece... Comparison circuit, ? /...Faulty output circuit number indicator, deco...
- Defective output circuit number indicator.

Claims (1)

[Claims] 1. In the sequence control device #C, an input state change detection circuit detects when a change occurs in the state of an input signal, and an input that stores the change in the input state when the state changes. A state storage 1x memory, a time interval storage yxyo memory that stores the time interval of the change, and 1x of these
It is equipped with a FIFO memory extraction circuit that sequentially extracts stored data from the memory 413, and a comparison circuit that compares the extracted data with an input signal and outputs it when there is a mismatch. 4. Changes in the input signal and time intervals seen in the circuit are stored in the FIFO memory. When a test signal is applied to the yxyo memory extraction circuit, the contents stored in the 1x10 memory are extracted and used as a reference value to compare the changing state of the input signal at that time.If there is a discrepancy, it is detected and the ratio content is output. Input/output Chetuta system. By connecting the output signal to the input section KIi), the input/output state can be processed as an input signal.
An input/output check method according to claim 1, characterized in that an input signal and an output signal are connected to a Kf IL rack. J. Claims characterized by learning the normal operation of external equipment, testing abnormal operation, and detecting defective parts! 81
F! The input/output check method described in section 1 or section 1.