JPS58213264A - Connecting state deciding device of connector - Google Patents

Connecting state deciding device of connector

Info

Publication number
JPS58213264A
JPS58213264A JP57095822A JP9582282A JPS58213264A JP S58213264 A JPS58213264 A JP S58213264A JP 57095822 A JP57095822 A JP 57095822A JP 9582282 A JP9582282 A JP 9582282A JP S58213264 A JPS58213264 A JP S58213264A
Authority
JP
Japan
Prior art keywords
connector
signal
input
level signal
connecting state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57095822A
Other languages
Japanese (ja)
Inventor
Yoshito Kawazoe
川副 義人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP57095822A priority Critical patent/JPS58213264A/en
Publication of JPS58213264A publication Critical patent/JPS58213264A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/68Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
    • G01R31/69Testing of releasable connections, e.g. of terminals mounted on a printed circuit board of terminals at the end of a cable or a wire harness; of plugs; of sockets, e.g. wall sockets or power sockets in appliances

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

PURPOSE:To decide exactly a connecting state of a connector, by deciding a fault whether a test signal sent out through a connector part from an output side is received through the connector part by an input side or not. CONSTITUTION:When a fault, etc. occurs in an apparatus, and it is caused from a connector part, when a start switch is turned on, a ''1'' level signal is outputted to an exclusive output line 51 for checking. This signal is transmitted to a lead wire 63 through a pin 61 and is transmitted to a pin 62 when a connecting state of a connector 60 is normal. This ''1'' level signal is read in a CPU56 through an exclusive input line 52 for checking. The CPU56 decides that the connecting state of the connector 60 is normal, due to a fact that the sent- out ''1'' level signal is returned again. Subsequently, the output line 51 outputs a ''0'' level signal, checks whether it is returned to a CPU1 or not in the same way, and decides it to be normal when said signal is returned. By executing a double check in this way, a decision error is prevented.

Description

【発明の詳細な説明】 本発明は機器に接続するコネクタ類の接続状態を適確に
チェックできるようにしたコネクタの接続状態判定装置
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a connector connection state determining device that can accurately check the connection state of connectors connected to equipment.

従来、電子機器の故障に際して、その故障部位を検出す
るためには、経験に基づいて測定ポイントを決め、この
測定デイントが正常であるか否かをテスター等の試験器
を用いてチェックしていた。このような故障(異常)検
出法はグリント基板等の如くに現象が適確に現われるも
のには比較的確実に検出することができる。
Conventionally, in order to detect the faulty part when an electronic device malfunctions, measurement points are determined based on experience, and a testing device such as a tester is used to check whether the measurement point is normal or not. . Such a failure (abnormality) detection method can relatively reliably detect a phenomenon that appears accurately, such as a glint board.

しか51従来の故障検知手段にあっては、コネクタ類の
故障あるいは異常の検出を目的とした場合、これらが固
有の現象として現われないために、修理員が感や経験を
活用しに<<、コネクタの接触不良(あるいは非接触状
態)の発見に手間どるばかシで無く、機器の奥部に配設
されたコネクタの入れ忘れ等は検出できない恐れがある
However, with conventional failure detection means, when the purpose is to detect failures or abnormalities in connectors, these do not appear as unique phenomena, so repair personnel have to use their intuition and experience. It is unnecessary to take time to discover poor contact (or non-contact state) of connectors, and there is a possibility that forgetting to insert a connector located deep inside the device may not be detected.

本発明は、上記に鑑みてなされたものであシ、コネクタ
類の接続状態を適確に判定するため、出力側よりコネク
タ部を介して送出した試験信号を前記コネクタ部を介し
て入力側で受信したとき正常と判定するようにしたコネ
クタの接続状態判定装置を提供するものである。
The present invention has been made in view of the above, and in order to accurately determine the connection state of connectors, a test signal sent from the output side through the connector part is sent to the input side through the connector part. An object of the present invention is to provide a connector connection state determining device that determines that the connector is normal when it receives the connector.

以下、本発明によるコネクタの接続状態判定装置を詳細
に説明する・ 第1図は本発明の一実施例を示し、中央処理装置(CP
U ) 51を有する回路部(f IJント基板あるい
は単独の装置)50にコネクタ60を介して他の回路部
(あるいは入出力装置)70を接続する構成を例示して
いる。回路部50は、回路部70との間で必要な情報の
授受を行なうだめの複数の入・出力線及び故障チェック
用の専用の出力線51と入力線52が出力インターフェ
ース53および入力インターフェース54より引き出さ
れ、コネクタ60の各接点に指定の配列順番で接続され
ている。出力インターフェース53および入力インター
フェース54は、パス55を介してCPU (中央処理
装置)56、ROM (リードオンリーメモリ)57お
よびRAM(ランダムアクセスメモリ)58の各々に接
続される。CPU 56は、ROM 57に格納された
プログラムに従って入力インターフェース54より情報
、データ等を入力し所定の制御演算処理等を行なってR
AM 58に結果やデータを記憶させると共に、所定時
に本来のプログラム実行を停止して、本発明に係る接続
状態判定処理用のプログラムをランさせる機能を有して
いる。このプログラムの切換えは、回路部50に設けら
れた特定の起動スイッチ(メインテナンスモードスイッ
チ)によシ行なわれる。なお、コネクタ60の故障チェ
ック専用に設けられた出力ビットに対応する接点(ビン
を含む)61と入力ピットに対応する接点(ピンを含む
)62との各々の回路部70 (illのビン同志をリ
ード線63で短絡する。
The connector connection state determining device according to the present invention will be explained in detail below. Figure 1 shows an embodiment of the present invention, and shows a central processing unit (CP)
A configuration is exemplified in which a circuit unit (f IJ component board or a single device) 50 having a U ) 51 is connected to another circuit unit (or an input/output device) 70 via a connector 60 . The circuit section 50 has a plurality of input/output lines for exchanging necessary information with the circuit section 70 and an output line 51 and an input line 52 dedicated for fault checking from an output interface 53 and an input interface 54. They are pulled out and connected to each contact of the connector 60 in a specified arrangement order. The output interface 53 and the input interface 54 are connected to each of a CPU (central processing unit) 56, a ROM (read only memory) 57, and a RAM (random access memory) 58 via a path 55. The CPU 56 inputs information, data, etc. from the input interface 54 according to the program stored in the ROM 57, performs predetermined control calculation processing, etc.
It has a function of storing results and data in the AM 58, stopping the original program execution at a predetermined time, and running a program for connection state determination processing according to the present invention. This program switching is performed by a specific startup switch (maintenance mode switch) provided in the circuit section 50. It should be noted that each circuit section 70 has a contact (including a pin) 61 corresponding to an output bit provided exclusively for failure checking of the connector 60 and a contact (including a pin) 62 corresponding to an input pit. A short circuit is made with the lead wire 63.

以上の構成において、機器に故障等が発生し、その原因
をコネクタ部に求める場合に、起動スイッチをオンにす
ると、チェック専用の出力線52に″′1″レベル信号
を出力する。この信号はコネクタの接続状態が正常であ
れば、−ン61を介してリード線63に伝送され、ピン
62に伝送される。ビン62に伝送された@1”レベル
信号はチェック専用の入力線52を介してCPU 56
に読み込まれる。CPU 56は送り出した@1#レベ
ル信号が再び戻ってきたことをもってコネクタ60の接
続状態が正常であることを判定する。ついで、出力線5
1は″′O#レベル信号を出力し、同様にCPU 51
に戻されるか否かをチェックし、戻された場合に正常と
判定する。このように2重にチェックする仁とによシ誤
判定を防止している。なお、出力線51と入力線52の
信号レベルが異なった場合には、故障検知信号を出力す
る。
In the above configuration, when a failure or the like occurs in the equipment and the cause is to be determined in the connector section, when the start switch is turned on, a ``1'' level signal is output to the output line 52 exclusively for checking. If the connection state of the connector is normal, this signal is transmitted to the lead wire 63 via the pin 61 and then to the pin 62. The @1” level signal transmitted to the bin 62 is sent to the CPU 56 via a check-only input line 52.
is loaded into. The CPU 56 determines that the connection state of the connector 60 is normal when the sent @1# level signal returns again. Then, output line 5
1 outputs the ``'O# level signal, and similarly the CPU 51
Check whether it returns to normal or not, and if it returns, it is determined to be normal. In this way, double checking prevents false judgments. Note that if the signal levels of the output line 51 and the input line 52 are different, a failure detection signal is output.

なお、通常、複雑な制御あるいは処理をする機器は複数
のコネクタを備えておシ、これに対応するためには、第
1図に示したチェック専用線とピン及びビン間短絡用リ
ード線を各コネクタごとに設けると共に、故障コネクタ
を識別するだめにコネクタに固有の番号を予め付してお
き、シーケンシャルにチェックしたのち接続不良等の異
常が検知されたコネクタの番号をメモリ54に格納する
と共に、所定時に表示器(図示せず)に表示する。
Note that equipment that performs complex control or processing is usually equipped with multiple connectors. In addition to providing a unique number for each connector, a unique number is assigned to each connector in advance to identify a faulty connector, and after sequential checking, the number of the connector in which an abnormality such as a connection failure is detected is stored in the memory 54, Displayed on a display (not shown) at a predetermined time.

第2図はを発明を複写機に適用した場合の構成を示し、
第1図におけると同一部分であるものには同一の引用数
字を用いると共に、説明のるだめのテンキー1およびテ
ンキー1による指定内容、動作状態等を表示する表示部
2(コンソール)を接続すると共に、外部機器、付属回
路等を接続するだめのコネクタ60がプリント板上に直
接膜けられ、あるいはケーブルによって接続されている
。回路部10は、テンキー1に接続され、その情報をパ
ス12に流す入力インターフェース11と、各種の制御
を行なうだめのプログラムおよびコネクタの接続状態判
定のためのプログラムを格納するためにノ々ス12に接
続されるROM (リード・オンリー・メモリ)13と
、該ROM 13の内容に基づいて各種の制御および演
算を行なうためにパス12に接続されるCPU 14と
、データおよびCPU 14による演算結果等を一時的
に格納するためにパス12に接続されるRAM (ラン
ダム・アクセス・メモリ)15と、CPU 14によっ
て決定された表示内容を表示部2に表示するための信号
を出力するためにパス12に接続される出力インターフ
ェース16と、コネクタ60を介して他回路(他機器)
とのデータ、情報等の交換および指令の入出力をパス1
2を介して行なう出力インターフェース17と、コネク
タ60よシのチェック用信号を入力しパス12に出力す
る入力インターフェース18と、装置の/4’ワースイ
ッチがオフになっても故障コ・ネクタの番号を記憶し続
ける機能を有し、パスに接続される不揮発性RAM 1
9とよシ構成場れる。なお、ROM 13は本発明に係
るコネクタ接続状態の判定用のプログラムのほか、複写
機を作動させるための各種の制御を実行するプログラム
が格納されている。
Figure 2 shows the configuration when the invention is applied to a copying machine,
The same reference numerals are used for the same parts as in Fig. 1, and the numeric keypad 1 used in the explanation and the display unit 2 (console) that displays the contents specified by the numeric keypad 1, operating status, etc. are connected. A connector 60 for connecting external equipment, auxiliary circuits, etc. is directly mounted on the printed board or connected by cable. The circuit section 10 includes an input interface 11 that is connected to the numeric keypad 1 and sends the information to a path 12, and a nozzle 12 for storing programs for performing various controls and programs for determining the connection state of the connector. A ROM (read only memory) 13 connected to the path 12, a CPU 14 connected to the path 12 for performing various controls and calculations based on the contents of the ROM 13, and data and calculation results by the CPU 14, etc. A RAM (Random Access Memory) 15 connected to the path 12 for temporarily storing the data, and a RAM (Random Access Memory) 15 connected to the path 12 for temporarily storing the display content determined by the CPU 14 and outputting a signal for displaying the display content determined by the CPU 14 on the display unit 2. Output interface 16 connected to and other circuits (other devices) via connector 60
Pass 1 for exchanging data, information, etc. and input/output of commands with
2, an input interface 18 that inputs a check signal from the connector 60 and outputs it to the path 12, and an input interface 18 that inputs a check signal from the connector 60 and outputs it to the path 12. Non-volatile RAM that has the function of continuing to store information and is connected to the path 1
9 Toyoshi composition field is available. The ROM 13 stores programs for determining the connector connection state according to the present invention as well as programs for executing various controls for operating the copying machine.

以上の構成において、故障発生時にテンキーlよυ予め
約束した故障判定用のキーナンバー(例えば、複写枚数
に影響を与えかい数の組合せで、oo、ooo等)をイ
ングツトし、故障判定ルーチンを起動させる。CPU 
14は出力インターフェース17よυ出力線61に11
”レベル信号を出力させ、入力インターフェース18に
コネクタ60を介して前記′″1#1#レベル信号込む
。コネクタ60の接続が完全であれば、入力インターフ
ェース18の入力yl? −トには11#レベル信号が
入力され、入力インターフェース18によってノ々ス1
2にデータが出力され、CPU 14はコネクタ接続が
完全であることを判定する。ついで、CPU 14は“
0#レベル信号t 出力インターフェース17よリコネ
クタ60のビン61に送出し、リード線63および入力
線52を介して入力インターフェース18に送り込む。
In the above configuration, when a failure occurs, a predetermined key number for failure determination (for example, combinations of numbers that affect the number of copies, such as oo, ooo, etc.) is input from the numeric keypad to start the failure determination routine. let CPU
14 is the output interface 17 and υ output line 61 is 11
``level signal is output, and the ``''1#1# level signal is input to the input interface 18 via the connector 60. If the connection of the connector 60 is complete, the input yl? of the input interface 18 is input. The 11# level signal is input to the input interface 18.
2, and the CPU 14 determines that the connector connection is complete. Then, the CPU 14 “
0# level signal t is sent from the output interface 17 to the bin 61 of the reconnector 60 and sent to the input interface 18 via the lead wire 63 and input line 52.

この場合もコネクタ接続が完全であれば10″レベル信
号は入力インターフェース18に取込まれ、パス12に
信号内容に応じたデータが送出され、CPU 14は再
度コネクタ接続が完全であることを判定する。このよう
な判定はコネクタの総てについて順次判定を行ない、そ
の結果を表示部2に表示する。
In this case as well, if the connector connection is complete, the 10'' level signal is taken into the input interface 18, data corresponding to the signal content is sent to the path 12, and the CPU 14 again determines that the connector connection is complete. Such a determination is made sequentially for all connectors, and the results are displayed on the display section 2.

一方、以上のように個々のコネクタについて行なわれる
2回のチェック信号送出に対し、その都度入力インター
フェース18に10”レベル信号が取り込まれた場合に
は、CPU 14はコネクタの接続に異常がある旨を判
定し、そのコネクタの番号を出力インターフェース16
を介して表示部2に表示すると共に、その番号を不揮発
性RAM 19に格納する6 第3図は以上説明した一連の処理のフローチャートを示
す。
On the other hand, if a 10" level signal is received in the input interface 18 each time the check signal is sent for each connector twice as described above, the CPU 14 will notify that there is an abnormality in the connection of the connector. Determine the number of the connector and output the number of that connector to the interface 16
The number is displayed on the display unit 2 via the numeral 2, and the number is stored in the non-volatile RAM 19.6 FIG.

以上説明した通シ、本発明のコネクタの接続状態判定装
置によれば、出力側よシコネクタ部を介して送出した試
験信号を前記コネクタ部を介して入力側で受信されたか
否かをもって故障(異常)を判定するようにしたため、
コネクタの接続状態を適確に判定することができる。
As described above, according to the connector connection state determination device of the present invention, it is determined whether or not a test signal sent through the connector section on the output side is received at the input side via the connector section. ), so
The connection state of the connector can be accurately determined.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例を示す接続図、第2図は本発明
を複写機に適用した例を示すブロック図、第3図は第2
図の実施例の処理内容を示すフローチャートである。 1・・・テンキー、2・・・表示部、10,50゜70
・・・回路部、11,18.54・・・入力インターフ
ェース、12.55・・・ノ々ス、13.57・・・R
OM、14.56・・・CPU、15.58・・・RA
M 。 16.17.53・・・出力インターフェース、19・
・・不揮発性RAM、 51・・・出力線、52・・・
入力線、60・・・コネクタ、61.62・・・接点、
63・・・リード線。 第2図 貨〜 3 図
FIG. 1 is a connection diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example in which the present invention is applied to a copying machine, and FIG.
3 is a flowchart showing the processing contents of the embodiment shown in the figure. 1... Numeric keypad, 2... Display, 10,50°70
...Circuit section, 11,18.54...Input interface, 12.55...Nos, 13.57...R
OM, 14.56...CPU, 15.58...RA
M. 16.17.53...Output interface, 19.
...Nonvolatile RAM, 51...Output line, 52...
Input line, 60...connector, 61.62...contact,
63... Lead wire. 2nd figure ~ 3 figure

Claims (1)

【特許請求の範囲】 各部の動作を指令する指令信号を入力したとき該指令信
号に応じた部位に所定の動作を行わせる制御信号をコネ
クタを介して出力する制御部を備えた電子装置において
、 前記コネクタが、試験信号を入力したとき該試験信号を
出力する試験端子を備え、 前記制御部が、試験モードを指令されたとき前記試験信
号を出力し、前記コネクタの試験端子を介して出力した
該試験信号を入力して該コネクタの接続状態を判定し、
この判定結果を不揮発性メモリにコネクタの識別番号と
ともに記憶させることを特徴とするコネクタの接続状態
判定装置。
[Scope of Claims] An electronic device comprising a control unit that outputs, via a connector, a control signal that causes a part to perform a predetermined operation in accordance with the command signal when a command signal that instructs the operation of each part is input, The connector includes a test terminal that outputs a test signal when the test signal is input, and the control unit outputs the test signal when a test mode is instructed, and outputs the test signal through the test terminal of the connector. inputting the test signal to determine the connection state of the connector;
A connector connection state determining device characterized in that the determination result is stored in a nonvolatile memory together with an identification number of the connector.
JP57095822A 1982-06-04 1982-06-04 Connecting state deciding device of connector Pending JPS58213264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57095822A JPS58213264A (en) 1982-06-04 1982-06-04 Connecting state deciding device of connector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57095822A JPS58213264A (en) 1982-06-04 1982-06-04 Connecting state deciding device of connector

Publications (1)

Publication Number Publication Date
JPS58213264A true JPS58213264A (en) 1983-12-12

Family

ID=14148099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57095822A Pending JPS58213264A (en) 1982-06-04 1982-06-04 Connecting state deciding device of connector

Country Status (1)

Country Link
JP (1) JPS58213264A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005308556A (en) * 2004-04-21 2005-11-04 Sharp Corp Splicing state monitoring device and electronic equipment equipped with the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005308556A (en) * 2004-04-21 2005-11-04 Sharp Corp Splicing state monitoring device and electronic equipment equipped with the same

Similar Documents

Publication Publication Date Title
JPS63277982A (en) Trouble specifying method and normal-operation maintaining method of detachable type electronic type subassembly and circuit assembly
US4847838A (en) Circuit for testing the bus structure of a printed wiring card
JPS5930288B2 (en) Clock signal monitoring method
JPH11502352A (en) Method and apparatus for electronic computing unit monitoring
JPS58213264A (en) Connecting state deciding device of connector
JP4705886B2 (en) Circuit board diagnosis method, circuit board and CPU unit
US6490694B1 (en) Electronic test system for microprocessor based boards
JP2002286781A (en) Wiring abnormality detection method of device and wiring abnormality detection device of device
JPH08278924A (en) Adapter diagnostic system
KR0168539B1 (en) Pin connector connection state inspection apparatus and its method
KR19980051705A (en) Packet Board Test Method of Electronic Switch
JPH04339399A (en) Relief address analyzing circuit for memory tester
JPH045150B2 (en)
JP3482788B2 (en) Failure diagnosis method
JP3028865B2 (en) Inspection equipment for building equipment monitoring equipment
JPS5812011A (en) Input and output check system
JPS5877674A (en) Test pattern generating device
JPS59123056A (en) Automatic switching system of redundant system
KR0161126B1 (en) Apparatus and method for searching the signal line status on the system bus in the computer
HU189017B (en) Method and apparatus for parallel control of digital computers
JPH0611533A (en) Fail-safe circuit of connection of a plurality of electronic circuits
JP2010041788A (en) Testing support device of digital protection control apparatus
JPS607297B2 (en) Process input/output device failure diagnosis method
JPH07253904A (en) Method and device for testing printed board mounting
JPS636471A (en) Logic integrated circuit