JPS5938618B2 - Contact input circuit abnormality inspection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Recent computer applications have been remarkable, but their reliability has also become a problem.

Particularly when applied to sequence control, etc., a signal representing the state of a contact (contact input) is taken in from the process as input (digital input) to a computer, but the state of the contact and the information actually taken into the computer's memory are It is important that they match completely; any discrepancy between them may cause sequence malfunctions, which may result in plant stoppage or damage to the main engine. For this reason, contact input information has conventionally been checked for correctness, and one typical example is shown in FIG. In the figure 3
1 to 3n are contact inputs (digital inputs), and the information is converted by the level conversion circuit 4 to a signal level that matches the computer circuit, and the address circuit 5 transfers the information to the bus 1.
0 and is written to the corresponding address in memory 2.
Based on this information, the central processing unit (CPU) 1
performs a predetermined calculation and outputs a control signal. In this case, the weakest point is the level conversion circuit 4, so normally another level conversion circuit 6 having exactly the same configuration function is provided for error detection, and both level conversion circuits 4, 6
Is the output an abnormality detection circuit? . The alarm is issued or displayed. Such conventional devices have the following drawbacks. (1) The object of failure detection is limited to the level conversion circuit 4, and failures in the address circuit 5, CPUI, memory 2, etc. cannot be detected.

(2) Extra hardware such as the level conversion circuit 6, the abnormality detection circuits T and 8, and the OR circuit 9 is required, and the number of parts increases, making the structure that much more complicated and reducing reliability.

In addition, since each of the above-mentioned devices requires one set for each of the contact inputs 31 to 30, the number of contact inputs may be several hundreds or more.
If the number is several thousand, the cost will rise significantly. (3) Since fault detection is executed by external hardware, the CPU
It is difficult to synchronize with the calculations and control being executed in the memory 2 and the memory 2, and even if an abnormal signal is output from the OR circuit 9, in some cases, this may cause a protective operation or stop of the calculations and control. There is a risk that the process will be controlled due to incorrect signals.

The present invention eliminates the above-mentioned drawbacks and provides a contact input circuit abnormality inspection device that can be carried out inexpensively and reliably.

The present invention will be described in detail below with reference to the drawings. FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 3 is a flowchart of one embodiment of the present invention. As shown in FIG. 2, an acquisition bus 16 and an inspection bus 17 are provided which are connected to the bus 10 and the CPU1 via an acquisition bus circuit 11 and an inspection bus circuit 12, respectively, and the inspection bus 17 is connected to the level conversion circuits 41 to 40.
The input bus 16 is connected to the inputs via diodes D1 to Dn, respectively, and the intake bus 16 is connected to the inputs via a series circuit of contact inputs 31 to 3n and diodes d1 to Dn, respectively. Note that the diodes D1 to Dn and d
1 to DO have the function of preventing each signal on the acquisition bus 16 and inspection bus 17 from interfering with each other. An abnormality inspection operation according to the present invention will be explained.

As shown in the flowchart of FIG. 3, first, the signals on the inspection bus 17 and the intake bus 16 are set to O via the inspection bus circuit 12 and the intake bus circuit 11 (S1), and the level conversion circuit 41 at that time -40 outputs are each taken into the corresponding address (S2). In this case, as is clear from Figure 2,
The input points of the level conversion circuits 41 to 4n are all 0, and naturally the memory contents at the corresponding addresses should also be all 0.
Therefore, the memory contents at this time are checked (S3), and if there is an address whose contents are 1, the related level conversion circuit, diode, contact input circuit such as an address designation circuit, or It is determined that there is an abnormality in the CPU 1 and the memory 2, and at least one of issuing an alarm and locking the control is executed (S4). If there is no abnormality - that is, if the contents of the corresponding address are all 0, change the signal on the inspection bus 17 from O to 1 (S
5) In the same manner as before, the outputs of the level conversion circuits 41 to 4n are taken into the corresponding addresses (S6), and it is checked whether the contents are all 1 (S7). If there is an address whose memory content is 0, it is determined that there is an abnormality in the input of the corresponding level conversion circuit, diode, etc., CPU1, memory 2, etc., and an alarm is issued in the same manner as above.
At least one of locking the control is performed (S8).
. If the contents of the corresponding address are all 1, it is determined to be normal. If it is normal, the signal on the intake bus 16 is set to 1 and the signal on the inspection bus 17 is set to O in the next step S9. At this time, the memory contents of the corresponding address change according to the closed state (open or closed) of each contact input 31 to 30 (SlO). Based on this memory content, various controls are executed according to conventionally known methods (Sll). As described above, according to the present invention, the reading unit is always inspected before taking in information from each contact input, making it possible to take in correct information and easily locking the control if there is an abnormality. Of course, address circuits other than level conversion circuits,
It also becomes possible to check for abnormalities in memory, etc. In addition, the equipment to be attached for inspection (7J11) shall be attached to each contact input.
diodes, a common inspection bus for all contact inputs, an inspection bus circuit, and a take-in bus circuit.Compared to the conventional type shown in Figure 1, the number of parts Hj is greatly reduced, and the structure is simple and reliable. Songs can be made at high prices and at low prices. In the above explanation, an example was given in which the memory contents of the corresponding address are checked in two states: when the signal on the inspection bus 17 is set to 0 and when it is set to 1. For practical purposes, it is sufficient to simply implement the following.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a conventional contact input circuit abnormality inspection device, FIG. 2 is a flowchart of an embodiment of the present invention, and FIG. 3 is a flowchart of an embodiment of the present invention. 1...CPUl2...Memory, 31~
3n...Contact input, 41-40...Level conversion circuit, 11...Intake bus circuit, 12.
...Inspection bus circuit, 16...Intake bus,
17...Inspection bus, D1-Dn, d1-dn・
·····diode.

Claims (1)

[Claims] 1. An acquisition bus, an acquisition bus circuit that outputs a scheduled signal on the acquisition bus at a scheduled timing, and an input end thereof is connected to the acquisition bus through corresponding contacts. An abnormality inspection device for a contact input circuit, comprising a plurality of level conversion circuits, a memory for storing outputs of the level conversion circuits, and means for reading the contents of the memory,
a test bus maintained at a predetermined voltage; means for connecting input ends of each of the level conversion circuits to the test bus; means for preventing mutual interference of signals on the intake bus and the test bus; and a test bus. a check bus circuit that outputs a scheduled signal at a scheduled timing on the bus, and an output of the level conversion circuit stored in the memory while the signal on the take-in bus is 0; An abnormality inspection device for a contact input circuit, comprising means for detecting whether or not the above signals match, and when the signals match, it is determined to be normal, and when they do not match, it is determined to be abnormal. .