JPS6161426B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault diagnosis method for digital electronic circuits. In particular, the present invention relates to a diagnostic method suitable for integrated circuit testing equipment.

Conventionally, fault diagnosis of digital circuits involves checking the voltages at the input and output terminals of the components that make up the digital circuit under test while searching a large-capacity diagnostic dictionary stored on a storage medium such as a paper tape or magnetic storage disk. They were taking measurements and searching for the location of the failure. There are the following two typical conventional methods of searching for failed parts using this diagnostic dictionary.

One method is to add the following to the digital circuit under test:
If an output pattern different from that when there is no fault appears, a new input pattern series is input to the digital circuit under test to further resolve the predicted locations of the multiple fault points pointed out, and the output is repeated. This is a method of observing patterns. Although this method can obtain high resolution of faulty parts, it requires a large capacity diagnostic dictionary containing the input pattern series, output pattern series, or predicted locations of failure points mentioned above, and requires a computer to create the diagnostic dictionary. This increases the operating cost of the dictionary and the equipment cost of the storage device for storing this dictionary. Furthermore, a board tester for diagnosing the digital circuit under test is also required to have a complicated control function for diagnosis, which has the disadvantage of increasing equipment costs.

Another method uses the digital circuit under test to
When an output pattern different from that when there is no failure occurs, a diagnostic dictionary is created that lists the expected locations of multiple failure points that are pointed out, and then a digital circuit is implemented according to this dictionary. This method determines the faulty component by probing the input and output terminal voltages of the circuit components mounted on the board under test. In this method, the capacity of the diagnostic dictionary is smaller than in other methods, but the absolute amount is large. In addition, the operation cost in terms of man-hours due to proving is high, and as a result of handling large-capacity diagnostic dictionaries, equipment costs are also high.

The present invention improves the shortcomings of the above two methods, and automatically diagnoses a faulty part of a digital circuit under test with high resolution for relatively small-scale logic circuits, and The purpose of this invention is to provide a fault diagnosis method for digital circuits that significantly reduces costs and equipment costs.

The present invention includes a board under test on which a digital circuit under test is mounted, means for compressing output information of the board under test into a cyclic code according to a certain rule, and connection information for the digital circuit under test, means for transmitting a pattern to be output when the digital circuit under test operates normally in response to a given input pattern; and means for compressing the output information of this means into a cyclic code in accordance with the above-mentioned certain rules; In a fault diagnosis method for a digital circuit, the method includes a comparison and determination means for comparing and determining output information of the compression means, wherein the board under test and the digital circuit under test send out a normal operation output pattern. and means for creating a list showing the correspondence between failure locations and compressed output patterns. The present invention is characterized in that it includes means for determining a failure location by referring to a list showing the correspondence between output patterns that do not operate normally and failure locations from information obtained by compressing the output information of the board.

Next, embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention. In the figure, a central processing unit 1,
A board under test 2, a board tester 3, a floppy disk 4, a typewriter 5, and a main storage device 6 are connected via a bus 7 to constitute an information processing device 8.

FIG. 2 is an operation chart of the embodiment of the present invention. A digital circuit under test 10 is mounted on a board under test 2 made of a printed circuit board. This output information of the board under test 2 is sent to the board tester 3 via the bus 7. The output of the central processing unit 1 is connected to the board tester 3 via a floppy disk 4. Also, this board tester 3
The output of is connected to a typewriter 5.

Here, the digital circuit under test 10 mounted on the board under test 2 is generally constructed by interconnecting components that have one or more basic logic elements (AND element, OR element, etc.) inside. However, the details are omitted from the diagram. This digital circuit 10 has one or more signal input terminals and one or more signal output terminals. A pattern of signals applied to one or more signal input terminals at the same timing is called an input pattern. At this time, the signal pattern appearing at the one or more signal output terminals is called an output pattern. The input patterns arranged in chronological order are called input pattern series. output pattern,
A pattern sequence arranged in the same time sequence as the input pattern sequence is called an output pattern sequence.

When an input pattern series is input to this digital circuit 10, if there is a stuck-at-one or "0" fixed fault (hereinafter referred to as a "stuck fault") in the component, the output pattern series will be the same as the pattern without the stack fault. It may be different compared to If they are different, it can be identified that there is a stack failure.

The central processing unit 1 also includes a digital circuit under test 10 obtained from a design information database.
The digital circuit 10 is provided with means for transmitting a pattern to be output when the digital circuit under test 10 operates normally in response to a given input pattern. This is created by software (or firmware).

That is, this central processing unit 1 can execute the following two types of programs.

This one program has a first function of automatically generating an input pattern series for detecting stack faults that may occur in the digital circuit 10 from the connection information of the digital circuit 10, and a fault that can be detected by each input pattern. a second function that creates correspondence information between the point and the position of the output terminal of the circuit 10 that detects a fault, and an output pattern series for each fault point from this second function and the output pattern series when there is no fault. It consists of three functions: a third function that calculates the value and compresses it according to certain rules;

This first function can be realized by a conventionally used automatic test pattern generation program for the digital circuit 10. Furthermore, the above second function can also be achieved using the conventionally used digital circuit 10.
This can be realized using a failure simulator.

These first and second functions provide the first information representing the input pattern sequence and the output pattern sequence when there is no failure, and the information that is input when there is a stack failure and outputs a different output pattern than when there is no failure. the input pattern, second information representing the order within the input pattern series, an output pattern that is different from when there is no fault, the position of the output terminal that outputs the different signal, and the stack fault point that can be detected based on the output pattern. The third information representing , and the following three types of information are obtained.

Another program uses a cyclic code as a means of compression, which is the third function, and includes a list that defines the correspondence between the cyclic code and failure points, and a list of input pattern sequences and output patterns when there is no failure. The series is edited and stored in the floppy disk 4, which is an external storage device. The output pattern series when there is no failure is as follows in board tester 3:
It is used for comparison with the output pattern series of the board under test 2.

Furthermore, the board tester 3 has a function that has been used conventionally, that is, it inputs an input pattern series to the board and compares the output pattern series that comes out with the output pattern series when there is no failure. In addition to the function of testing the presence or absence of failure of the test object, the board, it has the following two functions.

One is a function that generates a cyclic code from the output pattern sequence when an input pattern sequence is input to the board under test and an output pattern sequence different from that when no failure occurs. This is the same as the third function of the program of the central processing unit 1 stored on the floppy disk 4.

Another function is to use the cyclic code obtained by executing the above function as a key word to create a floppy disk 4.
This function searches a list of cyclic codes and failure point locations handed over from the computer and displays the corresponding failure location on the typewriter 5.

FIG. 3 shows the third function of the program of the central processing unit 1, and shows the third function of the program of the central processing unit 1.
FIG. 3 is a diagram for obtaining a cyclic code to be compressed from an input pattern sequence according to a certain rule.

In the figure, the floppy disk 4 shown in FIG.
When the input pattern series 11 delivered from the board under test 2 is input to the board under test 2, and the output pattern series 12 different from that when there is no failure in the digital circuit 10 of the board under test 2 comes out from the board under test 2. , this is input to the cyclic code arithmetic circuit 13 and compressed according to certain rules to obtain the cyclic code 14. For example, the number of output terminals of the digital circuit 10 is
If the number of input patterns included in the input pattern series is 200, the data amount of the output pattern series will be 20,000 bits. For example, CCITT
A cyclic code calculation circuit with the recommended 16-bit cyclic code generation polynomial is used to compress the code into a 16-bit cyclic code. The third function of the central processing unit program is to execute such processing for all failure points.

FIG. 4 is a format diagram of a list defining the correspondence between cyclic codes and failure points. In the figure, 14
is a cyclic code, and 15 represents the location of the failure point on the board. The location 15 of the failure point can usually be represented by 30 bits or less of information. The floppy disk 4 shown in FIG. 2 stores a list showing the correspondence between the cyclic code 14 and the location 15 of the fault point on the board, as well as the input pattern series and the output pattern series when there is no fault. It is used to transfer information from board tester 1 to board tester 3.

Next, a specific example of application to a digital circuit will be described. The digital circuit subjected to this test was 1/
4 selectors, 2 4-bit synchronous counters, 9
2 bit parity generation and detection circuits, 2 edge type D flip-flops, 18 tri-state buffers, 50 input terminals, 35 output terminals
It is made up of 73 individual parts. There are 587 representative failure points on the output side of the basic logic elements that make up this digital circuit. Here, the representative failure point refers to a failure point that can be logically distinguished when observed from the output terminal of the circuit. Eighty-six test patterns for this digital circuit are prepared, and each step is applied sequentially. For each test pattern, the central processing unit 1 corresponds to an input pattern sequence and an output pattern sequence when there is no failure.

The resolution of the failed part in this application is:
It is 0.654. Here, the resolution of the failed part is
This is the resolution evaluated for a component (IC, single component) that contains a basic element with a stack failure.
Furthermore, a resolution of 0.654 means that the predicted locations of failed parts are divided into 1.5 parts on average. In this way, the output pattern series that correspond to a specific fault point and are different from those when there is no fault have a significantly high ability to separate one from the other regarding the fault point. That is, the number of failure points that produce the same output pattern series (hereinafter referred to as "synonymous failure points") is significantly reduced. However, the amount of data of the output pattern series is enormous, and the storage capacity required for the storage device and search time are fatal obstacles to practical implementation at low cost.

Even in a medium-sized digital circuit, there are approximately 5,000 possible failure points, and if the amount of data in the output pattern series corresponding to one failure point is 20,000 bits, the total amount of data will be approximately ¹⁰⁸ bits. It can be seen that the amount of data is enormous. However, according to the method of the present invention, since the output pattern sequence for each failure point is compressed using a cyclic code calculation circuit or the like, the occurrence of synonymous failure locations due to compression can be suppressed to a small number. If 16 bits are used to represent the fault location using a 16-bit cyclic code, the total amount of data can be compressed to about 2×10 ⁵ bits in the same digital circuit as above. Compared to the amount of data required for conventional fault diagnosis, a correspondence relationship between a cyclic code and a fault location that is significantly more compact and has higher resolution is required.

Furthermore, mechanizing the process of obtaining and compressing an output pattern series in this manner can be realized inexpensively and easily on a computer or a board tester. Furthermore, since the correspondence between the determined cyclic code and the fault location is compact information,
It can be stored using small capacity and inexpensive media and storage devices such as floppy disks.

In addition, the predicted locations of failed components can be displayed with high resolution on a typewriter, etc., so diagnostic workers can repair the digital circuit by simply replacing the components mounted in a small number of displayed locations with non-defective components. can. Therefore, diagnostic workers are not required to have any special technical ability, and the operating costs and equipment costs associated with diagnosis can be significantly reduced.

As explained above, according to the present invention, an input pattern sequence for detecting a failure in a digital circuit and an output pattern sequence corresponding to a failure point are obtained on a computer, the output pattern sequence is compressed, and the failure point and the compressed result are At the same time, on the board tester, compress the output pattern series when the same input pattern series as above is input to the board under test, and use this as a key word to create a correspondence table with the above failure points. By using a method of searching and finding failure points, it is possible to easily and inexpensively create an automated system that points out failure points with high resolution, either on a computer or on a board tester.

This has the excellent effect of significantly reducing operating costs and equipment costs required for fault diagnosis compared to conventional systems.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an information processing apparatus according to an embodiment of the present invention. FIG. 2 is an operation chart of an embodiment of the present invention. FIG. 3 is a diagram for obtaining a cyclic code from an input pattern sequence in the same board tester. FIG. 4 is a format diagram of a list that defines the waiting relationship between the same cyclic code and a failure point. 1...Central processing unit, 2...Board under test, 3
...Board tester, 4...Flotspid disc, 5
... Typewriter, 6 ... Main memory device, 7 ... Bus, 8 ... Information processing device, 10 ... Digital circuit under test, 11 ... Input pattern series, 12 ... Output pattern series, 13 ... Circulation Sign calculation circuit, 14
...Cyclic code, 15...Location on the board of the failure point.

Claims (1)

[Scope of Claims] 1. A board under test on which a digital circuit under test is mounted, means for compressing output information of the board under test into a cyclic code according to a certain rule, and a means for compressing connection information of the digital circuit under test. A built-in means for transmitting a pattern to be output when the digital circuit under test operates normally in response to a given input pattern, and compressing the output information of this means into a cyclic code according to the above-mentioned certain rules. and a comparison/judgment means for comparing and determining the output information of both of the compressing means, wherein the board under test and the digital circuit under test send out a normal operation output pattern. The means for comparing and determining is provided with means for providing a test input pattern in which the output is uniquely determined in response to the input with the means, and means for creating a list showing the correspondence between the failure location and the compressed output pattern. , a digital circuit comprising means for determining a failure location by referring to a table showing a correspondence relationship between malfunctioning output patterns and failure locations from information obtained by compressing the output information of the board under test. Fault diagnosis method.