JPS6072219A - Fabrication of semiconductor single crystal thin film - Google Patents

Fabrication of semiconductor single crystal thin film

Info

Publication number
JPS6072219A
JPS6072219A JP17813283A JP17813283A JPS6072219A JP S6072219 A JPS6072219 A JP S6072219A JP 17813283 A JP17813283 A JP 17813283A JP 17813283 A JP17813283 A JP 17813283A JP S6072219 A JPS6072219 A JP S6072219A
Authority
JP
Japan
Prior art keywords
substrate
film
sapphire
semiconductor film
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17813283A
Other languages
Japanese (ja)
Inventor
Toshio Yoshii
俊夫 吉井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17813283A priority Critical patent/JPS6072219A/en
Publication of JPS6072219A publication Critical patent/JPS6072219A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)

Abstract

PURPOSE:To obtain the epitaxial layer of excellent crystallizability by a method wherein when a semiconductor film is epitaxially grown on an insulating substrate, the substrate is coated with the first semiconductor film firstly followed by ion implantation after which the first film is removed by etching and the second semiconductor film is newly grown epitaxially on the exposed surface of the substrate. CONSTITUTION:An Si film 2 of about 0.2mum thick is deposited on a sapphire substrate 1 by vapor deposition and Si<+> ions are implanted with acceleration energy of 120keV and doze quantity of 1X10<15>/cm<2>. Thus a projection range at implantation of ions is set near the boundary of Si and sapphire to produce a surface layer having high concentration of a distribution in a depth direction in the surface side on a sapphire side. Next, the film 2 is removed by etching using an HF-HNO3-group solution. The sapphire substrate thus changed its surface condition is put in a CVD oven and while an H2 carrier gas and an SiH4 gas are introduced to make the substrate temperature 950 deg.C and growing speed 2mum/ sec, an Si film 3 of about 0.6mum thick is produced.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は絶縁性m、結晶基板上の半導体単結晶膜の製造
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method for manufacturing a semiconductor single crystal film on an insulating crystal substrate.

〔従来技術とその問題点〕[Prior art and its problems]

絶縁性単結晶基板上の半導体膜を用いた集積回路は、そ
の構造上、高密度化、高速度化の点において、半導体基
板を用いたものよりも有利である。
An integrated circuit using a semiconductor film on an insulating single crystal substrate is advantageous over one using a semiconductor substrate in terms of its structure, high density, and high speed.

反面、単結晶基板上に異種の単結晶膜を結晶させるため
、この単結晶基板上こは高密度の格子欠陥カニ存在し、
それらが素子の電気的特性を劣化させるという欠点をも
つ。例えば、サファイア単結晶基板上のシリコン膜(S
OS)を用いたMOSデノくイスでは、Si単結晶基板
を用いたものと比べ。
On the other hand, since different types of single crystal films are crystallized on a single crystal substrate, a high density of lattice defects exists on this single crystal substrate.
They have the disadvantage of degrading the electrical characteristics of the device. For example, a silicon film (S) on a sapphire single crystal substrate
MOS denomination devices using MOS) compared to those using Si single-crystal substrates.

キャリア移動度が小さいことが知られてGする。It is known that carrier mobility is low.

シリコン膜に生ずる格子欠陥は、基本的には。Basically, lattice defects occur in silicon films.

シリコン膜成長初期におけるその機構に起因する。This is due to the mechanism at the early stage of silicon film growth.

すなわち、サファイア基板上にシリコンが成長する際、
核生成が起こり、その過程におG1てサファイアとシリ
コンとが反応し、その結果、液滴様合体による粒子間方
位の(い違いの是正が防げられるからである。
In other words, when silicon grows on a sapphire substrate,
This is because nucleation occurs, and during this process, sapphire and silicon react in G1, and as a result, correction of the orientation difference between particles due to droplet-like coalescence is prevented.

〔発明の目的〕[Purpose of the invention]

本発明は、上述した事情に鑑みてなされたもので、成長
初期における成長様式をかえることにより結晶性のすぐ
れた半導体薄膜をエピタキシャル成長させる方法を提供
することを目的とする。
The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a method for epitaxially growing a semiconductor thin film with excellent crystallinity by changing the growth mode in the early stage of growth.

〔発明の概要〕[Summary of the invention]

本発明においては、エピタキシャル成長はせる半導体1
1弾(Si)の構成原子(Si)あるいは弗素、不活性
ガス例えばアルゴンをイオン注入法を用いて、絶縁基板
に導入することにより、半導体膜が絶縁基板上に成長時
均−な成長をせしめ、格子欠陥の生成を防止する。
In the present invention, the epitaxially grown semiconductor 1
By introducing the constituent atoms (Si) of the first bullet (Si), fluorine, or an inert gas such as argon into the insulating substrate using the ion implantation method, the semiconductor film is allowed to grow uniformly on the insulating substrate. , preventing the formation of lattice defects.

〔発明の効果〕〔Effect of the invention〕

本発明によって、初期成長過程における格子欠陥生成を
除去でき、電気的特性のすぐれたデバイスを絶縁性基板
上につくることが可能となった。
The present invention has made it possible to eliminate the generation of lattice defects during the initial growth process and to produce devices with excellent electrical characteristics on an insulating substrate.

〔発明の実施例〕[Embodiments of the invention]

以下実施例によりこれを説明する。第1図は本発明の実
施例を示す図である。(1012)サファイア基板(1
)を用意し、その上に蒸着法でシリコン膜(2)を0.
2μmJIJユ積する。次にシリコンイオンを加速エネ
ルギ120KeV、ドーズ看I X 10 ”cm−”
の条件で試料に注入する。この時のイオン注入の射影飛
程は、はぼシリコン−サファイア界面近くにあるため、
サファイア11111#こもシリコンイオンは打ち込ま
れ、かつ、サファイア1(1すでの、シリコンの深さ方
向分布は、表面側での濃度が高い。次に。
This will be explained below using examples. FIG. 1 is a diagram showing an embodiment of the present invention. (1012) Sapphire substrate (1
) is prepared, and a silicon film (2) is deposited on it using a vapor deposition method.
2 μm JIJ product. Next, silicon ions were accelerated at an energy of 120 KeV and a dose of I x 10 ``cm-''.
Inject into the sample under the following conditions. The projected range of ion implantation at this time is near the silicon-sapphire interface, so
Sapphire 11111# is also implanted with silicon ions, and the depth distribution of silicon in Sapphire 1 (1) has a high concentration on the surface side.Next.

シリコン膜をHF−HNo、系溶液でエツチングする。Etch the silicon film with HF-HNo system solution.

サファイア基板は化学的に安定なため1表面21エツチ
ングされることはない。シリコン膜をエツチングしたサ
ファイア基板をCVD炉内に設置し。
Since the sapphire substrate is chemically stable, one surface 21 is not etched. A sapphire substrate with etched silicon film was placed in a CVD furnace.

水素ガスをキャリアガス、S i H4ガスをンースガ
スとして、基板温度950℃、成長速度2μm/秒でシ
リコン膜を0.6μm成長させる。
A silicon film is grown to a thickness of 0.6 μm at a substrate temperature of 950° C. and a growth rate of 2 μm/sec using hydrogen gas as a carrier gas and S i H 4 gas as a base gas.

この試料の格子欠陥密度を選択エツチング法で測定した
ところ2.5 X 10’ /cm’ であり、従来技
術であるサファイア基板1にシリコンを直接エピタキシ
ャル成長させた方法と比較し、2桁減少した。
The lattice defect density of this sample was measured by a selective etching method and was found to be 2.5 x 10'/cm', which was reduced by two orders of magnitude compared to the conventional method in which silicon was epitaxially grown directly on the sapphire substrate 1.

このように格子欠陥密度が減少した理由は次のように考
えられる。すなわち、サファイア基板へ打ち込まれたシ
リコンがエピタキシャル成長特にサファイア表面上で再
配列することによって、エピタキシャル成長時、基板表
面にシリコンが破着しやすくなる。このため、成長初期
に均一な成長が可能となり、格子欠陥の生成も少す(す
る。また、サファイア表面をシリコン11.にでおおっ
た後、イオン注入をするので、サファイア表面ζこ与え
る損傷も小さくでき1表面の結晶性が保持される。
The reason why the lattice defect density decreased in this way is considered to be as follows. That is, silicon implanted into a sapphire substrate is rearranged during epitaxial growth, particularly on the sapphire surface, making it easier for silicon to break and adhere to the substrate surface during epitaxial growth. For this reason, uniform growth is possible in the initial stage of growth, and the generation of lattice defects is minimized.In addition, since the sapphire surface is covered with silicon 11. and then ion implantation is performed, damage to the sapphire surface is minimized. It can be made small and the crystallinity of one surface is maintained.

〔発明の他の実施例〕[Other embodiments of the invention]

なお、基板の種類及び面方位はサファイア(1012)
面に限らIよいことは勿論である。イオン注入条件、シ
リコン膜成長法及び条件もまた実施例ζこ限られるもの
ではない。
The type and orientation of the substrate is sapphire (1012).
Of course, it is only good for the surface. The ion implantation conditions, silicon film growth method and conditions are also not limited to those in the embodiment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(al〜(c)は本発明の一実施例を示す断面図
である。 1・・・サファイア(1012)面、2・・・第1の半
導体膜、3・・・第2の半導体膜。 代理人弁理士 則 近 憲 佑(ほか1名)第1図 (θ、) (b) SL+ CC)
FIGS. 1A to 1C are cross-sectional views showing one embodiment of the present invention. 1... Sapphire (1012) surface, 2... First semiconductor film, 3... Second semiconductor film. Semiconductor film. Patent attorney Noriyuki Chika (and one other person) Figure 1 (θ, ) (b) SL+CC)

Claims (1)

【特許請求の範囲】[Claims] 絶縁性単結晶基板上ζこ第一の半導体膜を被着した鎌、
イオン注入を行う工程と、イオン注入された前記半導体
膜を除去する工程と、前記半導体膜が除去された前記絶
縁性単結晶基板上に第一の半導体膜と同種の第二の半導
体膜をエピタキシャル成長させる工程を含むことを特徴
とする半導体単結晶薄膜の製造方法。
A sickle coated with this first semiconductor film on an insulating single crystal substrate,
A step of performing ion implantation, a step of removing the ion-implanted semiconductor film, and epitaxial growth of a second semiconductor film of the same type as the first semiconductor film on the insulating single crystal substrate from which the semiconductor film has been removed. A method for producing a semiconductor single crystal thin film, the method comprising the step of:
JP17813283A 1983-09-28 1983-09-28 Fabrication of semiconductor single crystal thin film Pending JPS6072219A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17813283A JPS6072219A (en) 1983-09-28 1983-09-28 Fabrication of semiconductor single crystal thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17813283A JPS6072219A (en) 1983-09-28 1983-09-28 Fabrication of semiconductor single crystal thin film

Publications (1)

Publication Number Publication Date
JPS6072219A true JPS6072219A (en) 1985-04-24

Family

ID=16043206

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17813283A Pending JPS6072219A (en) 1983-09-28 1983-09-28 Fabrication of semiconductor single crystal thin film

Country Status (1)

Country Link
JP (1) JPS6072219A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5671953A (en) * 1979-11-19 1981-06-15 Toshiba Corp Formation of semiconductor layer on insulated substrate
JPS56142626A (en) * 1980-04-09 1981-11-07 Toshiba Corp Manufacture of semiconductor single crystal film

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5671953A (en) * 1979-11-19 1981-06-15 Toshiba Corp Formation of semiconductor layer on insulated substrate
JPS56142626A (en) * 1980-04-09 1981-11-07 Toshiba Corp Manufacture of semiconductor single crystal film

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