JPS5982744A - Manufacture of sos substrate - Google Patents

Manufacture of sos substrate

Info

Publication number
JPS5982744A
JPS5982744A JP19317282A JP19317282A JPS5982744A JP S5982744 A JPS5982744 A JP S5982744A JP 19317282 A JP19317282 A JP 19317282A JP 19317282 A JP19317282 A JP 19317282A JP S5982744 A JPS5982744 A JP S5982744A
Authority
JP
Japan
Prior art keywords
silicon film
heat treatment
substrate
thickness
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19317282A
Other languages
Japanese (ja)
Inventor
Koji Egami
江上 浩二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP19317282A priority Critical patent/JPS5982744A/en
Publication of JPS5982744A publication Critical patent/JPS5982744A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain an SOS substrate having superior crystallinity even when a silicon film is thin and having satisfactorily few microtwins by a method wherein the process that the SOS substrate made the single crystal silicon film of the prescribed thickness to grow is heat treated at a temperature higher than the growth temperature and moreover in an oxygen atmosphere, and thus formed oxide film is removed, is repeated up to reach the desired silicon film thickness. CONSTITUTION:A single crystal silicon film 2 is grown epitaxially at film thickness of 1mum or more on a single crystal sphhire substrate 1. As the growth condition, SiH4 gas is used, the growth temperature is made to 950 deg.C, and the growth speed is made to 1mum/min, for example. Then, the heat treatment temperature is selected to 1,100 deg.C as the temperature higher than the growth temperature 950 deg.C, and the heat treatment is performed in an oxigen atmosphere for 1.5hr. An oxide film generated by the heat treatment thereof is etched to be removed by a dilute hydrofluoric acid liquid. The silicon film 2 is thinned as much. The heat treatment and etching thereof are repeated for the 10 cycles in total, and thickness of the silicon film is made to the necessary thickness finally.

Description

【発明の詳細な説明】 本発明はSO8基板の製造法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing an SO8 substrate.

サファイア単結晶基板上にシリコン単結晶膜を形成させ
た5O8(8i1icon On 5apphire 
)は不純物制御によってデバイス素子間を分離しながら
、超LSI等の半導体装置を構成しているバルクシリコ
ンに比べ、シリコン膜を島状に分離して、デバイスを形
成するため、高密度化に適し、また寄生容量が少いため
、高速化が可能であるという利点を有する。SOS、用
いた理想的なデバイスは消費電力の小さい、集積度の密
な高速デバイス用として最適であることは良く知られて
いる。
5O8 (8i1icon on 5apphire) in which a silicon single crystal film is formed on a sapphire single crystal substrate
) is suitable for high density because it separates device elements through impurity control and separates the silicon film into islands, compared to the bulk silicon that makes up semiconductor devices such as VLSI. Also, since the parasitic capacitance is small, it has the advantage of being able to operate at higher speeds. It is well known that the ideal device used in SOS is ideal for low power consumption, high-speed devices with high density integration.

SO8基板はへテロエピタキシャル成長によりサファイ
ア基板の結晶学的方位に従い、シリコン単結晶膜を形成
させたもので、通常、化学気相成長法により形成される
。現有のSO8基板はいくつかの欠点を有するが、現在
の成長技術においては、上記の化学気相成長法により形
成されたものが、他の形成法により得られるものに比べ
、結晶性が良い。しかしながら、デバイス製作者にとっ
て、化学気相成長法で形成されたSO8基板は当初の性
能の高い理想的デバイスを製作するには未だ不十分で、
その結晶性改善が望まれていた。SO8基板を用い所望
の理想的な特性を有するデバイスを製作しようとすると
、SOSのシリコン膜厚は薄い程(例えば0.3〜0.
2μm程度あるいはそれ以下)望ましいが、逆に薄い和
結晶性は悪くなる。
The SO8 substrate has a silicon single crystal film formed by heteroepitaxial growth according to the crystallographic orientation of the sapphire substrate, and is usually formed by chemical vapor deposition. Although existing SO8 substrates have some drawbacks, with current growth techniques, those formed by the chemical vapor deposition method described above have better crystallinity than those obtained by other formation methods. However, for device manufacturers, SO8 substrates formed by chemical vapor deposition are still insufficient to manufacture ideal devices with high initial performance.
Improvement of its crystallinity has been desired. When trying to manufacture a device with desired ideal characteristics using an SO8 substrate, the thinner the SOS silicon film is (for example, 0.3~0.
(about 2 μm or less) is desirable, but on the other hand, thin crystallinity deteriorates.

従来のSO8基板で問題になっていたシリコン膜の結晶
性の膜厚依存性及びマイクロツイン(微小双晶)につい
て説明する。まず、結晶性の膜厚依存性について説明す
る。
The thickness dependence of silicon film crystallinity and microtwins, which have been problems with conventional SO8 substrates, will be explained. First, the dependence of crystallinity on film thickness will be explained.

第1図は従来のSO8基板の一例の断面図である。FIG. 1 is a cross-sectional view of an example of a conventional SO8 substrate.

主表面が(1102)面であるす7アイア基板lの上に
化学気相成長法によ!l) (100)面を有するシリ
コン膜2を成長させる。化学気相成長法はシラン(Si
n、)ガスを用い成長温度950℃で行った。
By chemical vapor deposition on a 7-Aire substrate l whose main surface is the (1102) plane! l) Grow a silicon film 2 having a (100) plane. The chemical vapor deposition method uses silane (Si
The growth temperature was 950° C. using a ) gas.

シリコン膜2の界面3からの距離をtとすると、シリコ
ン膜2の結晶性はtの関数として変化する、即ち、界面
3に近づく程、結晶性が劣化することが知られている。
It is known that when the distance from the interface 3 of the silicon film 2 is t, the crystallinity of the silicon film 2 changes as a function of t, that is, the closer it gets to the interface 3, the more the crystallinity deteriorates.

この様子は膜厚の異なるSO8についてX線ロッキング
カーブを測定することに定性的に調べられており、また
、X線回折法における運動学理部に基づいたX線ロッキ
ングカーブの解析(江土、他:第41回応用物理学会学
術講演会198−N−6(1,980))も行われテい
ル。
This situation has been qualitatively investigated by measuring the X-ray rocking curves of SO8 with different film thicknesses, and an analysis of the X-ray rocking curves based on the kinematics theory of the X-ray diffraction method (Edo, et al. : The 41st Academic Conference of the Japan Society of Applied Physics (198-N-6 (1,980)) was also held.

第2図は結晶の方位分布に対する半値幅を説明する図、
第3図はSO8基板のシリコン膜の界面からの距離と方
位分布の半値幅との関係を示す曲線図である。
Figure 2 is a diagram explaining the half-width with respect to the crystal orientation distribution,
FIG. 3 is a curve diagram showing the relationship between the distance from the interface of the silicon film of the SO8 substrate and the half-width of the orientation distribution.

モザイク結晶の方位分布の広がシ(モザイクネス)の半
値幅をWiで表わすと、半値幅w1が小2 さい和結晶性が良いことケ意味する。
When the half-width of the orientation distribution spread (mosaicness) of a mosaic crystal is expressed as Wi, it means that the sum crystallinity is good when the half-width w1 is small.

第3図に示すように、結晶性は界面が最も悪く、表面に
近づくに従って良くなっている。この傾向は、シリコン
膜厚を変化させても変らない。また、界面3からある距
離だけ離れた場所における半値幅自体もシリコン膜厚に
よって11とんど変化しない。従って、シリコン膜厚の
厚いSOS基板を使えは、表面付近のシリコン膜のモザ
イクネスが良いが、前述のように、特性の良いデバイス
を得るには薄いシリコン膜厚のSO8基板を用いたい。
As shown in FIG. 3, the crystallinity is worst at the interface and improves as it approaches the surface. This tendency does not change even if the silicon film thickness is changed. Furthermore, the half-width itself at a location a certain distance away from the interface 3 does not change at all depending on the silicon film thickness. Therefore, if an SOS substrate with a thick silicon film is used, the mosaicness of the silicon film near the surface is better, but as mentioned above, in order to obtain a device with good characteristics, it is preferable to use an SO8 substrate with a thin silicon film.

所が、シリコン膜厚が薄い場合はモザイクネスが悪く、
デバイスを形成したとき良好な特性が得られないという
欠点があった。
However, if the silicon film is thin, the mosaicness will be poor.
There is a drawback that good characteristics cannot be obtained when a device is formed.

次に、SOS基板のシリコン膜のもう一つの問題点であ
るマイクロツイン(微小双晶)について説明する。マイ
クロツインは第1図のシリコン膜2の界面3付近、に存
在する。従って、シリコン膜厚が厚いときには、製作し
たデバイスの特性には余力影響を与えないが、シリコン
膜が薄くなるとこの影響が出てくる。シリコン膜厚が0
.2μm以下のSO8基板では、モザイクネスの悪さと
マイクロツインの存在によ、asosデバイスは未だ実
現されていない。
Next, microtwins, which are another problem with the silicon film of the SOS substrate, will be explained. The microtwin exists near the interface 3 of the silicon film 2 in FIG. Therefore, when the silicon film is thick, it does not affect the characteristics of the manufactured device, but as the silicon film becomes thinner, this effect appears. Silicon film thickness is 0
.. AsoS devices have not yet been realized using SO8 substrates of 2 μm or less due to poor mosaicness and the presence of microtwins.

本発明者は熱処理によるマイクロツインの変化を調べ、
次のような結果を得た。(1)水素雰囲気の熱処理では
マイク四ツインはあtカ変化しない。
The present inventor investigated changes in microtwins due to heat treatment,
The following results were obtained. (1) Heat treatment in a hydrogen atmosphere does not change the strength of the four microphones.

(2)窒素雰囲気の熱処理ではマイクロツインは一部減
少する0(3)酸素雰囲気の熱処理では厚膜SO8のマ
イクロツインはやや減少し、薄膜SO8のマイクロツイ
ンは十分に減少する。上記のことより、配素雰囲気での
マイクロツインの減少は過剰酸素の効果と考えられる。
(2) In heat treatment in a nitrogen atmosphere, microtwins are partially reduced. (3) In heat treatment in an oxygen atmosphere, microtwins in thick film SO8 are slightly reduced, and microtwins in thin film SO8 are sufficiently reduced. From the above, it is considered that the decrease in microtwins in a chlorinated atmosphere is due to the effect of excess oxygen.

即ち、厚膜SO8ではシリ5− コン膜2が厚いため界面3付近に十分な過剰酸素が供給
されず、マイクロツインは余り減少しないが、シリコン
膜2が薄くなると過剰酸素の供給が十分になるためと考
えられる。
That is, in thick film SO8, since the silicon film 2 is thick, sufficient excess oxygen is not supplied near the interface 3, and the number of microtwins does not decrease much, but as the silicon film 2 becomes thinner, the supply of excess oxygen becomes sufficient. It is thought that this is because of this.

このように、SO8基板のシリコン膜には結晶性とマイ
クロツインの二つの問題があり、シリコン膜が薄いとき
はマイクロツインを酸素雰囲気での熱処理で低減させ得
ることがわかったが、シリコン膜が薄いときには結晶性
が悪いという問題がまだ残っている。
In this way, the silicon film of the SO8 substrate has two problems: crystallinity and microtwins, and it was found that when the silicon film is thin, microtwins can be reduced by heat treatment in an oxygen atmosphere. There still remains the problem of poor crystallinity when thin.

SO8基板のシリコン膜の結晶性を改善する方法として
、ビームアニール法(LQoleckf etal、A
ppl、Phys、Lett、第37巻、No号、 (
1980)919頁)が提案されている。この方法は、
シリコン膜にレーザビームを照射して一旦、融液化した
後、再成長を行う方法である。この方法はシリコンを融
液化するような高温熱処理であるため、サファイアから
のAA等の不純物が拡散するので結晶性は良くなっても
、不純物濃度の変化が起ハデバイス形成には不適当なシ
リコン膜になるとい6一 う欠点がある。
Beam annealing method (LQoleckf etal, A
ppl, Phys, Lett, Volume 37, No.
1980) p. 919) has been proposed. This method is
This is a method in which a silicon film is irradiated with a laser beam to be melted and then regrown. Since this method involves high-temperature heat treatment that melts silicon, impurities such as AA from sapphire diffuse, and even though the crystallinity improves, the change in impurity concentration causes the silicon to become unsuitable for device formation. There are six disadvantages when it comes to membranes.

本発明者は、前述のマイクロツインの低減に有効であっ
た酸素雰囲気での熱処理が、結晶性の改善にも有効であ
るかどうかを調べた。
The present inventor investigated whether the heat treatment in an oxygen atmosphere, which was effective in reducing microtwins, was also effective in improving crystallinity.

第4図はSO8基板のシリコン膜の酸素雰囲気中での熱
処理前稜における結晶性の変化を示す曲線図である。
FIG. 4 is a curve diagram showing the change in crystallinity at the edge of the silicon film of the SO8 substrate before heat treatment in an oxygen atmosphere.

横軸は界面からの距離、縦軸は方位分布の半値幅である
。シリコン膜厚は0.6μm及び1.5μmの2種類と
し、熱処理前のものを実線で、熱処理後のものを小さな
破線(0,68m膜厚品)と大きな破線(1,5μm膜
厚品)で示した。熱処理前では0.68m膜厚品と1.
5μm膜厚品とはほぼ同じであるので、第4図において
は両者を一本の実線で示した。処理温度は1100℃、
300分の条件で行った。半値幅はX線ロッキングカー
ブのカーペチャ解析により行った。
The horizontal axis is the distance from the interface, and the vertical axis is the half-width of the orientation distribution. There are two types of silicon film thickness: 0.6 μm and 1.5 μm. The solid line shows the silicon film before heat treatment, and the small broken line (0.68 m film thickness product) and large broken line (1.5 μm film thickness product) after heat treatment. It was shown in Before heat treatment, 0.68m film thickness product and 1.
Since they are almost the same as the 5 μm film thickness product, both are shown by a single solid line in FIG. The processing temperature is 1100℃,
The test was carried out for 300 minutes. The half width was determined by carpet analysis of the X-ray rocking curve.

この結果から、酸素雰囲気中での熱処理は、クリコン膜
厚の厚い方によシ大きな結晶性の改善があるが、薄い方
では改善効果はそれ程大きくないことがわかった。即ち
、シリコン膜厚の薄いSO8基板は酸素雰囲気中での熱
処理によりマイクロツインを低減できるが、結晶性は希
望する程改善されないという欠点があった。
From this result, it was found that heat treatment in an oxygen atmosphere significantly improves crystallinity in the case of thicker crystallinity films, but the improvement effect is not so great in thinner films. That is, an SO8 substrate with a thin silicon film can be heat-treated in an oxygen atmosphere to reduce microtwins, but the crystallinity is not improved as desired.

本発明の目的は、上記欠点を除去し、シリコン膜が薄く
ても結晶性が優れ、しかもマイクロツインが十分に少な
いSO8基板の製造法を提供することにある。
An object of the present invention is to eliminate the above-mentioned drawbacks and provide a method for manufacturing an SO8 substrate that has excellent crystallinity even if the silicon film is thin and has sufficiently few microtwins.

本発明のSO8基板の製造法は、単結晶のサファイア基
板上に厚さ1μm以上の単結晶シリコン膜をエピタキシ
ャル成長させてSO8基板を製作する工程と、前記シリ
コン膜成長の成長温度よル高い温度で、かつ酸素雰囲気
で前記SO8基板を熱処理する熱処理工程と前記熱処理
工程で形成される前記シリコン膜上の酸化膜をエツチン
グ除去するエツチング工程とを所望のシリコン膜厚にな
るまで繰返す工程とを含んで構成される。
The method for manufacturing an SO8 substrate of the present invention includes a step of manufacturing an SO8 substrate by epitaxially growing a single-crystal silicon film with a thickness of 1 μm or more on a single-crystal sapphire substrate, and a step of manufacturing the SO8 substrate at a temperature higher than the growth temperature for growing the silicon film. and a step of repeating a heat treatment step of heat treating the SO8 substrate in an oxygen atmosphere and an etching step of etching away an oxide film on the silicon film formed in the heat treatment step until a desired silicon film thickness is obtained. configured.

次に、本発明の実施例について図面を用いて説明する。Next, embodiments of the present invention will be described using the drawings.

第1図で説明したSO8基板の製造法と同様にして、主
面が(1102)のサファイア基板1の上に単結晶のシ
リコン膜2を1.1μmの膜厚にエピタキシャル成長さ
せる。成長条件は、SiH,ガスを用い、成長温度95
0℃、成長速度1μm/mlnとした。次に、成長温度
950℃よル高い温度として熱処理温度1100℃を選
び、酸素雰囲気中で1.5時間熱処理を行う。この熱処
理で生じた酸化膜を希7ツ酸液でエツチング除去する。
A single-crystal silicon film 2 is epitaxially grown to a thickness of 1.1 μm on a sapphire substrate 1 having a (1102) main surface in the same manner as the method for manufacturing the SO8 substrate described in FIG. The growth conditions were SiH, gas, and a growth temperature of 95%.
The temperature was 0° C. and the growth rate was 1 μm/ml. Next, a heat treatment temperature of 1100° C. is selected as a temperature higher than the growth temperature of 950° C., and heat treatment is performed for 1.5 hours in an oxygen atmosphere. The oxide film produced by this heat treatment is removed by etching with a dilute dichloromethane solution.

この分だけシリコン膜2は薄くなる。この熱処理とエツ
チングとを合計10サイクル繰返して最終的にシリコン
膜厚を0.37μmとなるようにした。比較のために、
これとは別に、前記成長条件と同じ条件で製作し、シリ
コン膜厚が1.1μmのSO8基板を酸素雰囲気中で1
100℃にて連続15時間熱処理し、生成された酸化膜
をエツチング除去した試料を作成した。
The silicon film 2 becomes thinner by this amount. This heat treatment and etching were repeated for a total of 10 cycles until the final silicon film thickness was 0.37 μm. For comparison,
Separately, an SO8 substrate with a silicon film thickness of 1.1 μm, which was manufactured under the same growth conditions as above, was grown in an oxygen atmosphere.
A sample was prepared by heat-treating at 100° C. for 15 hours continuously and removing the generated oxide film by etching.

この比較試料のシリコン膜厚は0.87μmとなった。The silicon film thickness of this comparative sample was 0.87 μm.

第5図は本発明の熱処理及びエツチングの実施前後にお
けるSO8基板のシリコン膜の界面からの距離に対する
半値幅の変化を示す曲線図である。
FIG. 5 is a curve diagram showing the change in the half-width with respect to the distance from the silicon film interface of the SO8 substrate before and after the heat treatment and etching of the present invention.

実線4は熱処理前、破線5は熱処理及びエッチ9− ング稜のそれぞれの半値幅の変化を示す。破線6は比較
試料の熱処理及びエツチング後の半値幅を示す。比較試
料の熱処理前の半値幅は、実線4と同じである。
The solid line 4 shows the change in half width before heat treatment, and the broken line 5 shows the change in half width of the heat treatment and etching edges. A broken line 6 indicates the half width of the comparative sample after heat treatment and etching. The half width of the comparison sample before heat treatment is the same as solid line 4.

第4図かられかるように、熱処理仮においては熱処理前
のそれに比べて半分以下になっている。
As can be seen from FIG. 4, the heat treatment value is less than half that before the heat treatment.

比較試料の方は熱処理とエツチングと全繰返した試料よ
勺もやや半値幅は高い値を示しているが、結晶性の改善
にはt1蔭同様の効果を不している。
The comparison sample, which was subjected to repeated heat treatment and etching, also showed a slightly higher half-value width, but did not have the same effect on improving crystallinity as t1.

第6図+a) 、 (blは本発明の熱処理及びエツチ
ング実施前後におけるS OS 基板のシリコン膜のX
14チヤートである。
Figure 6+a), (bl is the X of the silicon film of the SOS substrate before and after the heat treatment and etching of the present invention.
It is 14 charts.

第6図(a)Fi本発明の熱処理及びエツチング実施前
、第6図(b)は実施後におけるシリコン膜のX線チャ
ートである。即ち第6図(a)は第5図の実線4に対応
し、第6図(b)は第5図の破線5に対応する。
FIG. 6(a) is an X-ray chart of a silicon film before and after the heat treatment and etching of the present invention is performed, and FIG. 6(b) is an X-ray chart of the silicon film after the heat treatment and etching of the present invention are performed. That is, FIG. 6(a) corresponds to the solid line 4 in FIG. 5, and FIG. 6(b) corresponds to the broken line 5 in FIG.

第6図(atではマイクロツインのピークが見られるが
、第6図(b)では#Iとんど見られない。即ち、本発
明の熱処理とエツチングとを行うことにより、マイクロ
ツインは十分に減少したことを示してい10− る。尚、図示していないが、酸素雰囲気中で連続15時
間熱処理を行った比較試料、のマイクロツインは十分に
減少していなかった。これは酸化膜形成速度が、dを酸
化膜厚、tを熱処理時間、aを速度定数とすると、d=
aJ「の関係にあシ、熱処理時間tをn分割し、1回の
熱処理時間がt/nである熱処理?:n回(合計処理時
間はt)繰シ返して行った場合の酸化膜厚dがd′二〇
・dとなることによるものである。ただし、各々の熱処
理で生じた酸化膜は取りのぞくとする。従って、熱処理
時間15時間当カの7リコン膜の減少は単一処理の場合
は繰フ返し処理に比べ、1んE = 0.316である
から、約70係小さく、界面伺近に存在するマイクロツ
インに与える過剰酸素の効果が弱いことになる。
Although the peak of microtwins is seen in Fig. 6 (at), the peak of #I is hardly seen in Fig. 6(b). That is, by performing the heat treatment and etching of the present invention, the microtwins are sufficiently Although not shown in the figure, microtwins in a comparative sample heat-treated for 15 hours continuously in an oxygen atmosphere were not sufficiently reduced. However, if d is the oxide film thickness, t is the heat treatment time, and a is the rate constant, then d=
According to the relationship aJ, the heat treatment time t is divided into n, and the heat treatment time per time is t/n?: Oxide film thickness when repeated n times (total treatment time is t) This is due to the fact that d becomes d′20・d. However, the oxide film generated in each heat treatment is removed. Therefore, the reduction in 7 recon films for a heat treatment time of 15 hours is due to the single treatment. In this case, compared to the repeated treatment, 1 E = 0.316, which is about 70 times smaller, and the effect of excess oxygen on the microtwins existing near the interface is weaker.

上記実施例においては、主面が(1x02角であるサフ
ァイア基板を用いたが、(0001)面のサファイア基
板を用いて(111)面を有する単結晶シリコン膜を形
成したSO8基板についても本発明は実施でき、同様の
良好な改善結果が得られる。
In the above example, a sapphire substrate whose main surface is a (1x02 angle) was used, but the present invention can also be applied to an SO8 substrate in which a single crystal silicon film having a (111) plane is formed using a sapphire substrate whose main surface is a (0001) plane. can be implemented with similar good improvement results.

以上詳細に説明したように、本発明によれば、シリコン
膜が0.3〜0.2μm程度あるいはそれ以下の薄い膜
厚を有し、しかもシリコン膜の結晶性が優れ、マイクロ
ツインが極めて少ないSO8基板を製造することができ
るのでその効果は大きい。
As explained in detail above, according to the present invention, the silicon film has a thin film thickness of about 0.3 to 0.2 μm or less, and the crystallinity of the silicon film is excellent, and there are extremely few microtwins. The effect is great because SO8 substrates can be manufactured.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のSO8基板の一例の断面図、第2図は結
晶の方位分布に対する半値幅を説明する図、第3図はS
O8基板のシリコン膜の界面からの距離と方位分布の半
値幅との関係を示す曲線図、第4図はSO8基板のシリ
コン膜の酸素雰囲気中での熱処理前接における結晶性の
変化を示す曲線図、第5図は本発明の熱処理及びエツチ
ングの実施前後におけるSO8基板のシリコン膜の界面
からの距離に対する半値幅の変化を示す曲線図、第6図
(al 、 (b)は本発明の熱処理及びエツチング前
後におけるSO8基板のシリコン膜のX線チャートであ
る。 1・・・・・・サファイア基板、2・・・・・・シリコ
ン膜、3・・・・・・界面。 13− 第1国 ノrイ、立−イナー!し 第2国 界面かうの距#t− 第3図 第 ((L) 方イ立fA(0) 6 閉 (b) 方a角(0〕
Figure 1 is a cross-sectional view of an example of a conventional SO8 substrate, Figure 2 is a diagram explaining the half-width with respect to the crystal orientation distribution, and Figure 3 is an S
A curve diagram showing the relationship between the distance from the interface of the silicon film of the O8 substrate and the half width of the orientation distribution. Figure 4 is a curve showing the change in crystallinity of the silicon film of the SO8 substrate before heat treatment in an oxygen atmosphere. Figures 5 and 5 are curve diagrams showing changes in half-width versus distance from the interface of the silicon film of the SO8 substrate before and after the heat treatment and etching of the present invention, and Figures 6 (al) and (b) are curve diagrams showing changes in half-width with respect to the distance from the interface of the silicon film of the SO8 substrate before and after the heat treatment and etching of the present invention. and X-ray charts of the silicon film of the SO8 substrate before and after etching. 1... Sapphire substrate, 2... Silicon film, 3... Interface. 13- First country Nori, standing - Ina! The distance of the second national interface #t- Figure 3 ((L) Direction I standing fA (0) 6 Closed (b) Direction a angle (0)

Claims (1)

【特許請求の範囲】[Claims] 単結晶のサファイア基板上に厚さ1μm以上の単結晶シ
リコン膜をエビタキクヤル成長させてSO8基板を製作
する工程と、前記シリコン膜成長の成長温度よル高い温
度で、かつ酸素雰囲気で前記SO8基板を熱処理する熱
処理工程と前記熱処理工程で形成される前記シリコン膜
上の酸化膜をエツチング除去するエツチング工程とを所
望のシリコン膜厚になるまで繰返す工程とを含むことを
特徴とするSO8基板の製造法。
A step of manufacturing an SO8 substrate by growing a single crystal silicon film with a thickness of 1 μm or more on a single crystal sapphire substrate, and growing the SO8 substrate at a temperature higher than the growth temperature of the silicon film and in an oxygen atmosphere. A method for manufacturing an SO8 substrate, comprising a step of repeating a heat treatment step and an etching step of etching away an oxide film formed on the silicon film formed in the heat treatment step until a desired silicon film thickness is obtained. .
JP19317282A 1982-11-02 1982-11-02 Manufacture of sos substrate Pending JPS5982744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19317282A JPS5982744A (en) 1982-11-02 1982-11-02 Manufacture of sos substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19317282A JPS5982744A (en) 1982-11-02 1982-11-02 Manufacture of sos substrate

Publications (1)

Publication Number Publication Date
JPS5982744A true JPS5982744A (en) 1984-05-12

Family

ID=16303490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19317282A Pending JPS5982744A (en) 1982-11-02 1982-11-02 Manufacture of sos substrate

Country Status (1)

Country Link
JP (1) JPS5982744A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5123975A (en) * 1989-03-28 1992-06-23 Ricoh Company, Ltd. Single crystal silicon substrate
WO1998058408A1 (en) * 1997-06-19 1998-12-23 Asahi Kasei Kogyo Kabushiki Kaisha Soi substrate and process for preparing the same, and semiconductor device and process for preparing the same
WO2000019500A1 (en) * 1998-09-25 2000-04-06 Asahi Kasei Kabushiki Kaisha Semiconductor substrate and its production method, semiconductor device comprising the same and its production method
JP2008192907A (en) * 2007-02-06 2008-08-21 Oki Electric Ind Co Ltd Forming method of sos substrate having silicon epitaxial film

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5123975A (en) * 1989-03-28 1992-06-23 Ricoh Company, Ltd. Single crystal silicon substrate
WO1998058408A1 (en) * 1997-06-19 1998-12-23 Asahi Kasei Kogyo Kabushiki Kaisha Soi substrate and process for preparing the same, and semiconductor device and process for preparing the same
EP1037272A1 (en) * 1997-06-19 2000-09-20 Asahi Kasei Kogyo Kabushiki Kaisha Soi substrate and process for preparing the same, and semiconductor device and process for preparing the same
US6528387B1 (en) 1997-06-19 2003-03-04 Asahi Kasei Kabushiki Kaisha SOI substrate and process for preparing the same, and semiconductor device and process for preparing the same
EP1037272A4 (en) * 1997-06-19 2004-07-28 Asahi Chemical Ind Soi substrate and process for preparing the same, and semiconductor device and process for preparing the same
WO2000019500A1 (en) * 1998-09-25 2000-04-06 Asahi Kasei Kabushiki Kaisha Semiconductor substrate and its production method, semiconductor device comprising the same and its production method
US6768175B1 (en) 1998-09-25 2004-07-27 Asahi Kasei Kabushiki Kaisha Semiconductor substrate and its production method, semiconductor device comprising the same and its production method
JP2008192907A (en) * 2007-02-06 2008-08-21 Oki Electric Ind Co Ltd Forming method of sos substrate having silicon epitaxial film

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