JPS6072059A - デ−タ転送制御方式 - Google Patents

デ−タ転送制御方式

Info

Publication number
JPS6072059A
JPS6072059A JP58180005A JP18000583A JPS6072059A JP S6072059 A JPS6072059 A JP S6072059A JP 58180005 A JP58180005 A JP 58180005A JP 18000583 A JP18000583 A JP 18000583A JP S6072059 A JPS6072059 A JP S6072059A
Authority
JP
Japan
Prior art keywords
data
transfer
command
processing device
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58180005A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6356574B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Noboru Yamamoto
昇 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58180005A priority Critical patent/JPS6072059A/ja
Publication of JPS6072059A publication Critical patent/JPS6072059A/ja
Publication of JPS6356574B2 publication Critical patent/JPS6356574B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/17Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP58180005A 1983-09-28 1983-09-28 デ−タ転送制御方式 Granted JPS6072059A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58180005A JPS6072059A (ja) 1983-09-28 1983-09-28 デ−タ転送制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58180005A JPS6072059A (ja) 1983-09-28 1983-09-28 デ−タ転送制御方式

Publications (2)

Publication Number Publication Date
JPS6072059A true JPS6072059A (ja) 1985-04-24
JPS6356574B2 JPS6356574B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-11-08

Family

ID=16075786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58180005A Granted JPS6072059A (ja) 1983-09-28 1983-09-28 デ−タ転送制御方式

Country Status (1)

Country Link
JP (1) JPS6072059A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Also Published As

Publication number Publication date
JPS6356574B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1988-11-08

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