JPS607170A - Complementary type semiconductor device - Google Patents

Abstract

PURPOSE:To implement high integration, by forming the second channel region in the region of the first channel, and extracting a gate electrode from a vertical opening part, which is communicated to both regions. CONSTITUTION:On the surface of a P type semiconductor substrate 20, an N type growing layer 21 is formed. A P type separating layer 22 is formed in the N type growing layer 21, and an N-channel region 21a is formed. At the central surface part of the region 21a, a P type diffused layer 23 is formed and made to be a P-channel region. In the regions 21a and 23, a circular longitudinal P<+> type diffused layer and an N type diffused layer 25 are formed, respectively. A P type ion implanting layer 26 and an N type ion implantin layer 27 are formed so that the circular lower end parts of the diffused layers are connected. A vertical type opening part 29, which is communicated with the regions 21a and 23, is formed. A gate oxide film 30 is formed on the side wall of the opening part. A common gate electrode for the N channel and the P-channel is formed on the gate oxide film 30.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a complementary semiconductor such as a complementary MO8 type FET transistor formed by combining a P-channel MO8 type transistor and an N-channel MO8 type transistor. Regarding equipment.

[Technical background of the invention]

For example, for low power consumption devices such as electronic desk calculators and Keigin, C (complementary) MO8 as shown in Figure 1 is used.
type transistors are used. This CMOS) transistor is formed by combining a P-channel transistor and an N-channel transistor, as shown by broken lines a and b. That is, one N-channel transistor is mounted on a P-type semiconductor substrate II, for example. A diffusion layer 12B is formed, and two N-type diffusion layers 13B are further formed for this P-type diffusion layer 128.

Form I3b. Then, these two N type diffusion layers 73
On the surface of 8.13b, an N-channel source voltage is formed using a metal such as aluminum! 8N and drain electrode DN, these two electrodes &SN,
]) A gate oxide film 14a is formed between N channels to lead out an N channel gate electrode GN. Also, the other P
The channel transistor has the same N-type semiconductor base as above and two additional P-type diffusion layers.

15b, and these two diffusion layers 15a,
A P-channel source electrode Sp and drain tiDp are formed on the surface of the electrode 15b, respectively. Then, a gate oxide film 14b is formed between these two electrodes Sp, 1)p, and a P-channel gate electrode Gp is derived.

In other words, this CMOS transistor has a P-channel transistor and a H-channel transistor formed separately in planar form on the same conductor base, and the gates of the respective channels. The electrode [with] and GN are connected and used as a common gate electrode.

[Problems in the Background Art] However, in the CM, O8) transistor configured in this way, the P-channel transistor and the N-channel transistor are formed separately in a planar shape on the semiconductor substrate 11 surface. 1 For example, this CMOS
) When using a transistor as part of an integrated logic circuit such as a large-scale integrated circuit (LSI), the semiconductor substrate 11
It occupies a wide area of the surface; it behaves like a dog, making it difficult to obtain a high degree of integration.

[Purpose of the invention]

This invention was made in view of the problems mentioned above.
For example, a complementary semiconductor device that allows a highly integrated integrated logic circuit to be obtained without occupying a wide area on a semiconductor substrate even when it is incorporated as part of an integrated logic circuit such as an LSI. The purpose is to provide

[Summary of the invention]

That is, in the complementary semiconductor device according to the present invention, a second channel region is formed within the first channel region on the semiconductor substrate surface, and the second channel region is communicated with the first channel region. This is an example in which the gate electrodes of the respective channels are commonly led out from an N-type opening.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows its structure, and this complementary semiconductor device also forms, for example, a P-type semiconductor substrate 2o. First, an N-type growth layer 21 is formed on the surface of this P-type substrate 2o,
A P amount separation layer 22 is formed on this N-type growth layer 21 so as to surround a certain region 21a. This P amount separation layer 22 is
A P-type diffusion layer 23 is formed in the central surface portion of the N-type region 21a surrounded by the separation layer 22, which serves as an insulating separation layer for the N-type growth layer 21 outside the fixed region 21a. Here, for example, the N-type constant region 21a of the N-type growth layer 21 is
, and the P-type diffusion layer 23 is used as a second channel region.

Next, this first N-type channel region 21a and the second
For example, a circumferentially elongated P-type diffusion layer 2.4 and an Nfi diffusion layer 26 are respectively formed in the P-type channel region 23 of the P-type channel region 23.
form. In the N type channel region 21a where the P" type diffusion layer 24 is formed, a P type ion implantation layer 26 is formed so as to intersect with the circumferential lower end of the P type diffusion layer 24. In the P type channel region 23 where the type diffusion layer 25 is formed, an N type ion implantation layer 22 is formed so as to connect the circumferential lower end of the N type diffusion layer 25.Here,
The P-type ion implantation layer 26 and the N-type ion implantation layer 2
7 are the first and second ion-implanted layers, respectively. On the surface of the N-type channel region 21B, 1 is further provided with an N-type diffusion layer 28E on both sides of the P-type diffusion lumen 24.
I, 2Bb is formed.

Then, a vertical opening 29 communicating with the N-type channel region 21'a and the P-type channel region 23 is formed by, for example, electron beam etching. in this case,
The P-type first ion implantation layer 26 and the N-type second ion implantation layer 2 are formed on the N-type channel region 21a surface and the P-type channel region 23 surface, which are the side surfaces of the opening 29, respectively.
7 is exposed and formed, and a gate oxide film 30 is formed on the entire inside of this opening 29, and the semiconductor substrate 200 is
A low-temperature oxide film 31 is formed over the entire surface. Finally, a contact hole is formed in this low-temperature oxide film 31, and a metal wiring layer 32 made of aluminum or the like is formed.

In this case, the metal wiring layer 32 corresponding to the two N diffusion layers 29a and 28b formed in the N-channel region 27a is used as the N-channel source electrode SN and drain electrode DN, respectively, and the wiring corresponding to the P-type diffusion layer 24 is layer 32
is an N-channel back gate electrode GNb. Further, a wiring layer 3 formed corresponding to the P-type channel region 23
2 are the source electrode Sp and drain electrode Dp of the P channel, respectively, and the Nff1 diffusion layer 2 in this region 23 is
The wiring layer 32 formed corresponding to No. 5 is used as a P-channel back gate electrode Gpb.

That is, each back gate electrode axis and G
The P diffusion layer 24 and the N diffusion layer 25 corresponding to pb are
and P, and these respective gate layer regions 24 and 25 are as follows:
The first and second ion-implanted layers 26 and 27 of P and Nu are connected to the lower ends of the ion-implanted layers 26 and 27, respectively, so that they are commonly led out to the opening 29.

In other words, the wiring layer 32 formed on the chemical film 30 in the opening 29 becomes the gate electrode GNp common to the N channel and the P channel.

That is, in the semiconductor device configured in this manner, a P channel region 23 is further formed within the N channel region 21a, and a vertical type with a polar GNp common to each channel is formed in the center thereof. opening 2
9, the area occupied by the semiconductor substrate 20 can be significantly reduced. This results in
For example, even when this semiconductor device is incorporated as part of an integrated logic circuit such as an LSI.

There is no possibility that a wide area of the semiconductor substrate 20 surface on which the circuit network is formed will be occupied. Therefore, according to this semiconductor device, it is possible to further increase the degree of integration of an integrated logic circuit such as an LSI.

〔Effect of the invention〕

As described above, according to the present invention, the N channel region and the P
Since the channel region and the channel region can be formed concentratedly within one channel region instead of being formed at separate locations on the semiconductor substrate surface as in the conventional method, it is possible to form the channel region in a concentrated manner within one channel region, for example, in integrated logic circuits that require a high degree of integration. Even when the integrated circuit is incorporated into a circuit board, a sufficiently highly integrated integrated circuit can be obtained without occupying a wide area on a circuit board.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional configuration diagram showing a conventional CMO8 type transistor, and FIG. 2 is a cross-sectional configuration diagram showing a complementary semiconductor device according to an embodiment of the present invention. 20... Semiconductor substrate b 21m... N channel region, 23... P channel region, 24... N channel gate layer, 25... P channel gate layer, 26
. . . N channel ion implantation layer, 27 . . P channel ion implantation layer, 29 . . . Vertical opening, 30 .
Gate oxide film/

Claims (1)

Claims: A first channel region formed on a main surface of a semiconductor substrate, and a second channel region formed on a surface portion of the first channel region. a vertical opening communicating with the second channel region and the first channel region; and a vertical opening communicating with the first channel region; and a vertical opening communicating with the first channel region; a gate oxide film formed entirely inside the exposed opening of the first and second ion implantation layers; A complementary semiconductor device characterized by: