JPS6068659U - hybrid integrated circuit - Google Patents
hybrid integrated circuitInfo
- Publication number
- JPS6068659U JPS6068659U JP16115983U JP16115983U JPS6068659U JP S6068659 U JPS6068659 U JP S6068659U JP 16115983 U JP16115983 U JP 16115983U JP 16115983 U JP16115983 U JP 16115983U JP S6068659 U JPS6068659 U JP S6068659U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- substrates
- bonding
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は、別々の基板に実装した混成集積回路を説明す
るためのaは基板の斜視図、bは側面図、第2図は1枚
の基板の表裏両面に実装した混成集積回路を説明するた
めのaは基板の斜視図、bは側面図、第3図は、本考案
に係る混成集積回路の一実施例を説明するためのaは実
装部品を搭載した2枚の基板を貼合わせた斜視図、bは
側面図である。
図において、1は基板、2は実装部品、3は端 ′
−子、4は半田、5はシールドケース、6はプリント板
、7はアース層、8は導電性接着剤をそれぞれ示す。Figure 1 shows a hybrid integrated circuit mounted on separate boards; a is a perspective view of the board, b is a side view, and Figure 2 shows a hybrid integrated circuit mounted on both the front and back sides of a single board. 3 is a perspective view of the board, b is a side view, and FIG. 3 is a diagram showing an embodiment of the hybrid integrated circuit according to the present invention. 1 is a perspective view, and b is a side view. In the figure, 1 is the board, 2 is the mounted component, and 3 is the end.
4 indicates solder, 5 indicates a shield case, 6 indicates a printed board, 7 indicates a ground layer, and 8 indicates a conductive adhesive.
Claims (1)
記基板相互の貼合わせ面にアース層を印刷により形成し
、前記基板を互いに若干ずらした状態で前記アニス層を
導電性接着剤で貼合わせたことを特徴とする混成集積回
路。In a hybrid integrated circuit formed by bonding two substrates together, a ground layer is formed by printing on the bonding surfaces of the substrates, and the anis layer is bonded with a conductive adhesive while the substrates are slightly shifted from each other. A hybrid integrated circuit characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16115983U JPS6068659U (en) | 1983-10-17 | 1983-10-17 | hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16115983U JPS6068659U (en) | 1983-10-17 | 1983-10-17 | hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6068659U true JPS6068659U (en) | 1985-05-15 |
Family
ID=30354262
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16115983U Pending JPS6068659U (en) | 1983-10-17 | 1983-10-17 | hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6068659U (en) |
-
1983
- 1983-10-17 JP JP16115983U patent/JPS6068659U/en active Pending
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