JPS6068659U - hybrid integrated circuit - Google Patents

hybrid integrated circuit

Info

Publication number
JPS6068659U
JPS6068659U JP16115983U JP16115983U JPS6068659U JP S6068659 U JPS6068659 U JP S6068659U JP 16115983 U JP16115983 U JP 16115983U JP 16115983 U JP16115983 U JP 16115983U JP S6068659 U JPS6068659 U JP S6068659U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
substrates
bonding
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16115983U
Other languages
Japanese (ja)
Inventor
久徳　照義
杉木　広安
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP16115983U priority Critical patent/JPS6068659U/en
Publication of JPS6068659U publication Critical patent/JPS6068659U/en
Pending legal-status Critical Current

Links

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structure Of Printed Boards (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、別々の基板に実装した混成集積回路を説明す
るためのａは基板の斜視図、ｂは側面図、第２図は１枚
の基板の表裏両面に実装した混成集積回路を説明するた
めのａは基板の斜視図、ｂは側面図、第３図は、本考案
に係る混成集積回路の一実施例を説明するためのａは実
装部品を搭載した２枚の基板を貼合わせた斜視図、ｂは
側面図である。 図において、１は基板、２は実装部品、３は端　　′　
−子、４は半田、５はシールドケース、６はプリント板
、７はアース層、８は導電性接着剤をそれぞれ示す。Figure 1 shows a hybrid integrated circuit mounted on separate boards; a is a perspective view of the board, b is a side view, and Figure 2 shows a hybrid integrated circuit mounted on both the front and back sides of a single board. 3 is a perspective view of the board, b is a side view, and FIG. 3 is a diagram showing an embodiment of the hybrid integrated circuit according to the present invention. 1 is a perspective view, and b is a side view. In the figure, 1 is the board, 2 is the mounted component, and 3 is the end.
4 indicates solder, 5 indicates a shield case, 6 indicates a printed board, 7 indicates a ground layer, and 8 indicates a conductive adhesive.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ２枚の基板を貼合わせてなる混成集積回路においてこ前
記基板相互の貼合わせ面にアース層を印刷により形成し
、前記基板を互いに若干ずらした状態で前記アニス層を
導電性接着剤で貼合わせたことを特徴とする混成集積回
路。In a hybrid integrated circuit formed by bonding two substrates together, a ground layer is formed by printing on the bonding surfaces of the substrates, and the anis layer is bonded with a conductive adhesive while the substrates are slightly shifted from each other. A hybrid integrated circuit characterized by:
JP16115983U 1983-10-17 1983-10-17 hybrid integrated circuit Pending JPS6068659U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16115983U JPS6068659U (en) 1983-10-17 1983-10-17 hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16115983U JPS6068659U (en) 1983-10-17 1983-10-17 hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS6068659U true JPS6068659U (en) 1985-05-15

Family

ID=30354262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16115983U Pending JPS6068659U (en) 1983-10-17 1983-10-17 hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS6068659U (en)

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