JPS6068648U - Carrier for semiconductor wafer - Google Patents
Carrier for semiconductor waferInfo
- Publication number
- JPS6068648U JPS6068648U JP16073583U JP16073583U JPS6068648U JP S6068648 U JPS6068648 U JP S6068648U JP 16073583 U JP16073583 U JP 16073583U JP 16073583 U JP16073583 U JP 16073583U JP S6068648 U JPS6068648 U JP S6068648U
- Authority
- JP
- Japan
- Prior art keywords
- carrier
- semiconductor wafer
- grooves
- pairs
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Warehouses Or Storage Devices (AREA)
- Sheets, Magazines, And Separation Thereof (AREA)
- Packaging Frangible Articles (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図ａは従来の半導体ウェーハ用キャリアと収納ウェ
ーハを示す斜視図、同図すは同図ａのキャリヤのみの平
面図である。第２図ａは本考案の一実施例の平面図、同
図すは同図ａによる半導体ウェーハの等間隔溝キャリヤ
における配列を示す平面図、第３ａは違った溝配列の他
の例の平面図、同図すは同図ａによる等間隔溝キャリヤ
におけるウェーハ配列を示す平面図、第４図ａはさらに
違った溝配列のキャリヤの例の平面図、同図すは同図ａ
による等間隔溝キャリヤにおけるウェーハ配列を示す平
面図である。
１・・・・・・キャリヤ本体、２・・・・・・半導体ウ
ェーハ収納用溝、３・・・・・・ガイドピン、４・・・
・・・ガイド穴、５・・・・・・半導体ウェーハ、２０
・・・・・・等間隔溝のキャリヤ、２１，３１，４１・
・・・・・広間隔溝をもつ本考案実施例キャリヤ。FIG. 1a is a perspective view showing a conventional carrier for semiconductor wafers and wafer storage, and a plan view of only the carrier shown in FIG. 1a. FIG. 2a is a plan view of an embodiment of the present invention; FIG. FIG. 4A is a plan view showing a wafer arrangement in a carrier with equally spaced grooves according to FIG. 4a, and FIG.
FIG. 2 is a plan view showing a wafer arrangement in an equally spaced groove carrier according to FIG. 1...Carrier body, 2...Semiconductor wafer storage groove, 3...Guide pin, 4...
... Guide hole, 5 ... Semiconductor wafer, 20
・・・・・・Carrier with equally spaced grooves, 21, 31, 41・
...A carrier according to an embodiment of the present invention having widely spaced grooves.
Claims (1)
向する側壁の内面に互いに対向して形成された複数対の
溝を有する半導体ウェーハ用キャリヤに対し、前記複数
対の溝のうちの１対または数対の溝がない状態とされて
いることを特徴とする半導体ウェーハ用キャリヤ。For a semiconductor wafer carrier having a plurality of pairs of grooves formed opposite to each other on the inner surfaces of opposing side walls in order to store a plurality of semiconductor wafers in parallel and at regular intervals, one pair of the plurality of grooves is formed. Or a carrier for a semiconductor wafer, characterized in that it is free of several pairs of grooves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16073583U JPS6068648U (en) | 1983-10-18 | 1983-10-18 | Carrier for semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16073583U JPS6068648U (en) | 1983-10-18 | 1983-10-18 | Carrier for semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6068648U true JPS6068648U (en) | 1985-05-15 |
Family
ID=30353450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16073583U Pending JPS6068648U (en) | 1983-10-18 | 1983-10-18 | Carrier for semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6068648U (en) |
-
1983
- 1983-10-18 JP JP16073583U patent/JPS6068648U/en active Pending
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