JPS6068449A - Control system of transfer of data - Google Patents

Abstract

PURPOSE:To reduce the load of a CPU by providing a confirmation/answer signal for partial use of a data bus in addition to another confirmation/answer signal for normal transfer of data, and identifying the partial using condition by the answer signal sent from a device that received the confirmation signal. CONSTITUTION:A CPU1 puts all and addresses of four bytes on a data bus 8 and an address bus 7 as shown in this example since which transfer destination mode is suitable for supporting an I/O in the data transfer destination is not known at first. Then lines SRVI-1, SRVI-2 and SRVI-4 are added on a control bus 6. While an I/O3 for 1-byte transfer receives just the upper 1-byte data and also sends back only the SRVO-1. Receiving the SRVO-1, the CPU1 confirms the 1-byte transfer I/O3 and is controlled hereafter to transfer the remaining 3-byte data in a 1-byte transfer mode.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data transfer control system in a common bus having a plurality of hide width data buses.

fb) Technical background The performance of recent micropro sensors has improved significantly.

General data processing devices need to extract and process data from input/output devices, and input/output devices that are compatible with the high-performance microprocessors mentioned above are becoming necessary, and high-speed input/output devices ( For example, high-speed disk drives (4.1 devices, etc.) are becoming increasingly connected.

For this reason, for example, it has become necessary to introduce a common data bus having a 4-hide width data bus in place of the conventional common data bus having a 2-hide width data bus.

On the other hand, conventional low-speed input/output devices (1-hide transfer).

2-byte transfer) must also be connected, and a data transfer control method that can efficiently use parts of the data bus, such as 1-byte and 2-byte, is required in a common data bus that has multiple hide-width data buses. It had been.

(c+ Prior Art and Problems Currently, a common bus with a 16-bit wide data bus is the mainstream, but it is difficult to connect an input/output control device that uses only a conventional 8-bit wide data bus to that data bus. However, it is well done.

For this reason, a bit is provided to specify 1-byte or 2-byte transfer, and when accessing an input/output control device that uses only 1-byte width, software uses a 1-byte transfer instruction to control the specified bit. was used to control data transfer.

Considering that a common bus having a 32-bit width data bus will be required in the future, the above-mentioned technology for partial use of the data bus will become increasingly necessary.

However, in the conventional method, the software
Determine whether to use 2/4 byte transfer,
It was necessary to use a dedicated transfer instruction for each.

Also, at the 1-hide transfer instruction and 2-byte transfer instruction level,
-There was a problem in which it was not possible to transfer many bytes with an instruction.

(dl) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional technology, the present invention provides a method for controlling software that uses only a part of the data bus in a data transfer control system using a common bus that has multiple hide-width data buses. The purpose of this is to provide a method that can be realized using only hardware without having to do so.

+e) Structure and object of the invention: According to the invention, in a common bus having data buses of multiple hide widths, in addition to acknowledgment/response signals for normal data transfer, only a portion of said data buses Provide confirmation/response signals for data transfer using
This was achieved by providing a method that allows partial use of a single data bus, and the software does not need to be aware of how many data transfers to perform (this means that the conventional 4-byte data transfer was replaced by 4 data transfers). Data transfer can now be performed with a single 4-hyde transfer command instead of the 1-high, 1- transfer command, which has the advantage of reducing the load on the microprocessor sensor.

(f) Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an example of a common bus system to which the present invention is applied;
2. Main storage device (hereinafter referred to as MEi),
3, 4.5 transfer 1 byte each.

2-byte transfer, 4-byte transfer input/output device (hereinafter referred to as 110)
), 6 is a control bus, 7 is an address bus 18 is a data bus, and these 6, 7, and 8 constitute a common bus.

When a transfer command is executed in the microprocessor sensor 1, the control bus 6 is first checked to see if the common bus is free and whether a data transfer request has been issued from another input/output device. When it is determined that the bus is available, the common bus is seized and occupied, a busy indication is displayed on the control bus 6, and data transfer begins.

The data transfer is performed from MEM to M depending on the value of the address.
Data transfer is performed between MEMi10 and I1O-110.

When actually transferring data, a service in (SR) is sent from the microprocessor sensor 1 to the control bus 6.
VI) At the same time, it sends the address and data to the address bus 7 and data bus 8, respectively, and sends the address and data to the control bus 6.
This is done in such a way that a service out (SRVO) signal is received from M) (ie, an acknowledgment/response method) and one data transfer is performed.

Next, in order to clarify the difference from the present invention, a conventional data transfer method in a common lotus will be explained.

FIGS. 2 and 3 are diagrams showing conventional examples of using a portion of a 2-byte bus, where ADR5 is an address signal on address bus 7, I) IITA is a data signal on data bus 8, and SR 'VI' is a service-in signal for control lotus 6, and BYTE is a mode designation bit that identifies whether the control lotus 6 is in 1-hide transfer mode or 2-hide transfer mode.

FIG. 2 shows a transfer method using only one hide out of a two-hyde transfer lot. In the conventional example, the mode designation bit 1-rBYTEJ is provided on the control bus 6, and when this bit is "L", only the upper 1 high 1- on the 2-byte data bus is used. Data transfer is performed.

When a 1-hide transfer command is used to transfer 2-hide data, as is clear from this figure, 1-hide transfer is performed twice.

FIG. 3 is a diagram showing a method for transferring 2 bytes of data using a 2-byte data transfer instruction using the entire 2-byte data bus. In this case, the above mode specification rBYTEj
is set to "0" (indicated by a dotted line) and data transfer is performed.

Whether C, PI 1 sets the signal of the mode designation bit rBYTEj to "0" or "1" is controlled so as to be determined depending on whether the instruction to be executed is a 1-hide transfer instruction or a 2-byte transfer instruction. Ru.

Next, the present invention will be explained in detail with reference to FIGS. 4 to 6.

The main focus of the present invention is on the control path 6, for 1 byte transfer (7) SRVI-1, 5RVO-1 line, for 2 byte transfer 17) SRVI-2, 5RVO-2 line, for 4 byte transfer It is located where the SRVI-4, 5RVO-4 lines are installed.

CPU 1 controls all these control lines, and on the I10 side, if 1 hide transfer I10, 5RVI-1, 5RVO-
If only 1 line is 2 high 1-transfer I10, then 5RVI-
It operates to control only the 2°SRν0-2 line, and in the case of 4-hide transfer I10, only the 5RVl-4 and 5RVO-4 lines.

Figure 4 shows the sequence when transferring 4-byte data to 1 high I/transfer I10. Since we do not know whether the
and on the address bus 7, and on the control bus 6 (7) SRVI
-1,5RVI-2,5RVI-4 wires are energized.

The 1-hide transfer 110 receives only binary 1-hide data among the above data, and operates to return only 5RVO-1.

When the CPU 1 receives the 5RVO-1, it recognizes that it is a 1-hide transfer I10, and is thereafter controlled to transfer the remaining 3-hide data in the 1-hide transfer mode.

At this time, control path 6 upper no SRt/I-2, 5IIVI-
Since the 4 wires are not used, they may be controlled so that they are not energized by 4=J, or they may be energized as shown in this figure.

Figure 5 shows the sequence of data transfer for 4-byte data to 2-byte data transfer ■10.CPU 1 first checks which transfer mode is supported by 110, which is the data transfer destination. Since we do not know, all 4 bytes of data and address are placed on the data bus 8 and address bus 7, respectively, and on the control bus 6 (7) SRVI-
Energize the 1, 5RVI-2, 5RVI-4 lines.

The 2-hide transfer I10 operates to receive only the upper 2 bytes of the data and to return only 5flVO-2.

When the CPU 1 receives the 5IIVO-2, it recognizes that it is a 2-byte transfer I10, and is thereafter controlled to transfer the remaining 2 bytes of data in the 2-byte transfer mode.

At this time, the 5RVI-1 and 5RVI-4 lines on the control bus 6 are not used, so they may be controlled so that they are not energized by (-1), or they may be controlled so that they are energized as shown in this figure. You may do so.

Figure 6 shows the sequence for transferring 4-byte data to 4-byte data ■/○, in which CPU i first determines which transfer mode the data transfer destination Ilo is in Since we do not know if the data and address are in total 4 bytes, we put them on the data bus 8 and the address bus 7, respectively, and send them to the S1 pin Vl on the control bus 6.
-1,5IIVI-2,5RVI-4 wires are energized.

The 4-byte transfer I10 operates to receive all of the above data and return only 5IIVO-4.

When the CPU 1 receives the 5RVO-4, it recognizes that it is a 4-hide transfer I10, and knows that the data transfer has been completed.

FIG. 7 is a time chart explaining the difference between the conventional example and the present invention when transferring 4-byte data, where (b) shows the conventional example and (a) shows the difference between the conventional example and the present invention. This shows a case where the present invention is implemented. In the present invention, a 4-byte transfer command is issued once and a 1-byte transfer is performed four times to complete a 4-byte data transfer.

However, in the conventional example, a 4-byte data transfer is completed by fetching a 1-byte transfer instruction and performing 1-byte transfer four times.

As is clear from this time chart, the total transfer time when implementing the present invention is shorter than that of the conventional method.

+g+ Effects of the Invention As explained in detail above, the data transfer control method of the present invention provides, in addition to confirmation/response signals for normal data transfer, in a common bus having a multi-byte wide data bus.
A confirmation/response signal is provided for data transfer using only a part of the data bus, and the micropro sensor receives the response signal from the input/output device and recognizes the data transfer mode of the input/output device; From then on, data transfer is controlled to match the data transfer mode, so the software does not need to be aware of how many bytes to transfer, and conventional 4-byte data transfers can be performed using 4-byte transfer instructions. Data can now be transferred, reducing the load on the Micro Pro Sensor. Furthermore, regarding hardware, if only low-speed input/output devices are connected, 1
For economical purposes, configure only with a byte-wide data bus, and when connecting high-speed input/output devices, configure with a 4-byte wide data bus to enable high-speed data transfer. This has the effect of making it possible to construct a data bus with high performance.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a common lotus system to which the present invention is applied, FIGS. FIG. 6 is a diagram for explaining one embodiment of the present invention, and FIG. 7 is a diagram for explaining the difference between the conventional example and the present invention when transferring 4 bytes of data in terms of a time chart. In the drawing, ■ indicates a microprocessor (CPU),
2 is the main memory (MUM >, 3 to 5 are each 1
Input/output device (Ilo) for byte transfer, 2 byte transfer, 4 byte transfer, 6 is control bus, 7 is address bus, 8 is data bus, 5RVI is service in signal, 5RVO
indicate service out signals, respectively.稟 Iの阜 2 類岑 3 t”2J

Claims (1)

[Claims] In a common bus having a multi-byte wide data bus, in addition to the acknowledgment/response signal for normal data transfer, an acknowledgment/response signal for data transfer using only a part of the data bus is provided, When performing data transfer, all confirmation signals are sent onto a common bus, and the partial usage conditions of the data bus are identified based on the response signal from the device that received the confirmation signal, and data transfer on the data bus is performed. A data transfer control method characterized by controlling.