JPH04315244A - Bus connector - Google Patents

Abstract

PURPOSE:To easily perform access between devices respectively connected to the two buses of various architectures without loading much burden to the devices. CONSTITUTION:When a command showing 'access request to a device B2 at a bus B' is applied from a device A1 connected to a bus A to a bus connector (this device) 10, a CPU part 11 in this device 10 possesses the bus B by a bus control signal interface 13B, confirms that the device B2 can be accessed and informs it of the device A1. Afterwards, the access to the device B2 can be alternated by this device 10 by issuing the access command to the device B2 from the device A1 to this device 10. In this case, data to be transferred between the buses A and B are transformed so as to be matched to the architecture of the counter bus by a data processing part 14 in this device 10.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus connection device suitable for connecting two buses having different architectures.

0002

2. Description of the Related Art In general, in order to allow a device connected to one of two buses with different architectures to access a device connected to the other, a bus connection device that connects both buses is generally used. It becomes necessary. Conventionally, this bus connection device has been configured with a hardware mechanism that takes into account the architecture of the two buses connected by the device, and transfers data and control signals on one bus to data and control signals on the other bus. It was a dedicated conversion interface for converting signals.

Now, with the above-mentioned bus connection device, two
In a system in which two buses are connected, the following procedure is required for a device on one bus to access a device on the other bus.

[0004] First, the access request source device (host CPU)
obtains the bus to which it is connected (request source bus). Next, the request source device issues a bus acquisition request signal for acquiring the bus to which the request destination device is connected (request destination bus). This request signal is guided to the bus connection device via the request source bus, converted by the same device into a request signal compatible with the architecture of the request destination bus, and sent to the request destination bus. When the request is accepted by the bus arbitration circuit that arbitrates the request destination bus, the acceptance signal (approval signal) is returned to the request source bus through signal conversion by the bus connection device.

[0005] When the requesting device acquires the requesting bus, it sends an access request command (read or write command) to the requesting device to the requesting bus. This command is converted by the bus connection device into a command compatible with the architecture of the requesting side bus, and sent to the requesting side bus. Upon receiving the access request command on the bus, the request destination device performs the requested command processing. If it is a read command, the request destination device is
Acquire the two buses using the same procedure as when the request source device acquires the bus described above, and then read the read data.
The data is converted by the bus connected device and then transferred to the requesting device.

[0006]

[Problems to be Solved by the Invention] As mentioned above, conventional bus connection devices convert the data and control signals sent back and forth between two buses connected by the same device so that they are compatible with the architecture of the other bus. It was a dedicated conversion interface. For this reason, there has been a problem in the past that the method can only be applied to connections between buses that have relatively similar bus architectures.

Furthermore, in order to send commands, data, etc. to a device on the bus side to which it is not connected, it is necessary to acquire two buses, which places a heavy load on the device. Even if it was possible, if the other party's bus could not be acquired, it would be a problem.

The present invention was made in view of the above circumstances, and its purpose is to provide a bus connection that allows easy access between devices connected to two buses with different architectures without placing a large burden on the devices. The goal is to provide equipment. Another object of the present invention is to provide a bus connection device that can connect buses of arbitrary architectures.

[0009]

[Means for Solving the Problems] The present invention provides a first bus of a first architecture and a second bus of a second architecture.
A first bus connection device for identifying the bus connection device on the first and second buses respectively.
and identification information setting means for setting second identification information; data processing means for converting data transferred between the first and second buses to match the architecture of the other bus; An access request from a device connected to one of the two buses to a device connected to the other bus connects the bus by specifying the identification information corresponding to the one of the first and second identification information. a control means for accessing the requested device via the other bus on behalf of the requesting device and controlling the data processing means; and under the control of the control means; The present invention is characterized in that it includes bus control signal processing means for controlling the first and second buses, respectively.

0010

[Operation] According to the above configuration, an access request from a device connected to one of the first and second buses (request source device) to a device connected to the other (request destination device)
When the identification information corresponding to one of the buses among the first and second identification information is given to the device of the present invention, the control means controls the bus control signal processing means to control the other bus. and access the requested device on behalf of the requesting device. At this time, the data transferred between the two buses is converted by the data processing means so as to be compatible with the architecture of the other bus. Therefore, the requesting device
The requested device can be accessed as if it were directly connected to one of the buses.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of a computer system in which two buses are connected by a bus connection device of the present invention. In the figure, A and B are buses with different architectures, and A1 to A3 are buses A
B1 to B3 are devices connected to bus B. Devices A1 and B1 are host CPUs, and devices A2 and A3 and devices B2 and B3 are input/output devices such as magnetic disk drives that can be accessed from devices A1 and B1.

Reference numeral 10 denotes a bus connection device for connecting bus A and bus B. The bus connection device 10 includes buses A, B
C that controls the bus control signal interfaces 13A, 13B and the data processing unit 14, which will be described later, according to commands sent from the devices (host CPU) A1, B1 via the
An identification number setting section (for setting the PU section 11 and the identification numbers (device number, device address) of the device 10 on the buses A and B, that is, the identification numbers IDA and IDB of the device 10 as seen from the buses A and B. (hereinafter referred to as ID setting section) 12A,
It has 12B. The ID setting units 12A and 12B are, for example, switches. The bus connection device 10 also includes bus control signal interfaces 13A and 13B that manage input and output of control signals on the buses A and B, and data transferred between the buses A and B so as to be compatible with the architecture of the destination bus. (Conversion of data width, bit position, e.g. LSB and MS
This is a data processing unit that has a data conversion function (such as conversion of B) and a buffer for temporarily holding converted data when the transfer destination bus cannot be obtained. This data processing section 1
4 is a hardware mechanism that performs data conversion specified by the CPU unit 11;

Next, the operation of the configuration shown in FIG. 1 will be explained using an example in which a device (host CPU) A1 connected to bus A attempts to access device B2 connected to bus B.

When the device A1 attempts to access the device B2 on the bus B side, the device A1 first accesses the device B2 on the bus A side using a well-known method.
get. Next, the device A1 issues a specific access request command to the bus connection device 10 indicating a “request for access to the device B2 on the bus B”. The destination address (DA) of this command is the address (identification number) IDA on bus B of the bus connection device 10, and the source address (SA
) is the address of the access requesting device A1.

Bus connection device 10 issued from device A1
The specific access request command addressed to the bus A is transferred to the CPU unit 11 in the bus connection device 10. C
The PU unit 11 sends the specific access request command to bus A.
, the destination address is the identification number I (on bus A of the own device 10) set in the ID setting section 12A.
It is checked whether they match the DA, and if they match, the command is fetched (because the command is addressed to the device itself). Then, the CPU section 11 interprets the fetched specific access request command and recognizes that access from the device A1 on the bus A to the device B2 on the bus B is requested.

Next, the CPU section 11 provides the device A1 with the access requested by the specific access request command from the device A1.
In order to execute this on behalf of , first, the bus control signal interface 13B is controlled to issue a bus B acquisition request. When this bus acquisition request is received by a bus arbitration circuit (not shown) that arbitrates for bus B and bus B is acquired, CPU unit 11 confirms via bus B that device B2 is accessible. . When the CPU unit 11 confirms that the device B2 is accessible, it sends a message to that effect (as a response to the specific access request command) via the bus A.
The device A1 is notified via.

[0017] The bus A is accessed after the device A1 acquires the bus A and issues the above-mentioned specific access request command.
The configuration may be such that it is not released until a response is returned from the bus connection device 10 to the device A1, or it may be configured to be released immediately after the transfer of the specific access request command is completed. In the latter configuration, although bus A can be used effectively, bus connection device 10 needs to acquire bus A when returning a response to device A1.

Now, when the device A1 receives the response from the bus connection device 10 to the above-mentioned specific access request command, it thereafter sends commands (such as read commands or write commands) to the device B2 (device B2
(instead of) to bus connection device 10, device B2 can be accessed as if it were directly connected to bus A, as described below.

Now, assume that device A1 issues a read command on bus A with bus connection device 10 as the destination. This read command on bus A is taken in by the CPU section 11 of the bus connection device 10 that is its destination.

When the CPU unit 11 receives a read command from the device A1, it first reads the bus control signal interface 1.
3B to acquire bus B, and in this state issues a read command on bus B with device B2 on bus B as the destination. When device B2 receives a read command addressed to its own device on bus B, device B2 reads the data specified by the command and sends the data via bus B to bus connection device 10.
Transfer to.

The read data transferred from the device B2 to the bus connection device 10 via the bus B is processed by the data processing unit 14 in the bus connection device 10 to have a data width that is compatible with the architecture of the transfer destination bus A. Conversion or conversion of bit positions, for example between LSB and MSB, etc. is performed. Here, only data conversion is performed, compared to traditional bus connection devices that also had to convert bus control signals.
Hardware configuration becomes extremely simple. It should be noted that the bus control signals are directly inputted and outputted to and from devices on the buses A and B to which they are connected via the bus control signal interfaces 13A and 13B, so there is no need for conversion unlike in the past.

The CPU section 11 in the bus connection device 10 controls the bus A using the bus control signal interface 13A to transfer read data converted by the data processing section 14 to match the architecture of the bus A.
The request is transferred to the requesting device A1 above.

In the above embodiment, a case was explained in which a device on bus A accesses a device on bus B. However, when accessing a device on bus A from a device on bus B, the bus connection device It is clear that the proxy access of 10 is performed in the same manner as in the previous embodiment.

Furthermore, in the above embodiment, the bus connection device 10
We have explained the case where bus A and bus B connected by It is also applicable when connecting an expansion bus.

[0025]

[Effects of the Invention] As detailed above, according to the present invention,
When an access request is given to the device of the present invention from a device connected to one of two buses with different architectures (request source device) to a device connected to the other (request destination device), , the requesting device acquires the other bus on behalf of the requesting device and accesses the requesting device, and also converts the data transferred between both buses to match the architecture of the other bus. teeth,
It is now possible to access a request destination device without being aware of differences in bus architecture or controlling the bus on the request destination device side. The request destination device can be accessed in a manner similar to the above, and overhead is reduced.

[0026] In addition, it is only necessary to convert data according to the difference in bus architecture, and there is no need to convert bus control signals, etc., which would complicate the configuration. Therefore, connections between buses with significantly different architectures can be easily made. This can be easily achieved through configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a computer system in which two buses are connected by a bus connection device of the present invention.

[Explanation of symbols]

A, B...bus, A1-A3, B1-B3...device, 10...
Bus connection device, 11...CPU section (control means), 12A,
12B...ID setting unit, 13A, 13B...bus control signal interface (bus control signal processing means), 14...data processing unit.

Claims (1)

[Claims] 1. A bus connection device that connects a first bus of a first architecture and a second bus of a second architecture, wherein the bus connection device is identified on the first and second buses, respectively. identification information setting means for setting first and second identification information for the purpose of the above-described data processing; and data processing means for converting data transferred between the first and second buses so as to be compatible with the architecture of the other bus. and an access request from a device connected to one of the first and second buses to a device connected to the other,
When the first and second identification information is given to the bus connection device by designation of identification information corresponding to one of the buses, a request is made via the other bus on behalf of the request source device. control means for accessing the above device and controlling the data processing means; and bus control signal processing means for controlling the first and second buses respectively under the control of the control means. A bus connection device characterized by: